JPH0360885U - - Google Patents

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Publication number
JPH0360885U
JPH0360885U JP11799889U JP11799889U JPH0360885U JP H0360885 U JPH0360885 U JP H0360885U JP 11799889 U JP11799889 U JP 11799889U JP 11799889 U JP11799889 U JP 11799889U JP H0360885 U JPH0360885 U JP H0360885U
Authority
JP
Japan
Prior art keywords
current
circuit
output
differential
subtraction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11799889U
Other languages
Japanese (ja)
Other versions
JPH0729748Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989117998U priority Critical patent/JPH0729748Y2/en
Publication of JPH0360885U publication Critical patent/JPH0360885U/ja
Application granted granted Critical
Publication of JPH0729748Y2 publication Critical patent/JPH0729748Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Rectifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例のカレントミラー整
流回路部分の回路図、第２図は従来の整流回路の
回路図である。 １……信号源、２……定電流源、３……バイア
ス電源、４……出力端子、５……定電流源、６…
…基準電源、７……定電流源、８……出力端子、
２１，２２……引算回路、２３，２４……差動回
路、２５……加算回路。 FIG. 1 is a circuit diagram of a current mirror rectifier circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional rectifier circuit. 1... Signal source, 2... Constant current source, 3... Bias power supply, 4... Output terminal, 5... Constant current source, 6...
... Reference power supply, 7 ... Constant current source, 8 ... Output terminal,
21, 22... Subtraction circuit, 23, 24... Differential circuit, 25... Addition circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) 信号源の電圧を同相の非反転電流と逆相の
反転電流に変換する電圧／電流変換回路と、上記
非反転電流から上記反転電流を差し引いた電流を
取り出す第１の引算回路、上記反転電流から上記
非反転電流を差し引いた電流を取り出す第２の引
算回路、及び該第１及び第２の引算回路から得ら
れる電流を整流する整流出力回路を有するカレン
トミラー整流回路とからなる整流回路において、 上記整流出力回路を、上記第１の引算回路の第
１の極性のみの出力電流に応じた電流を吐き出す
第１の差動回路と、上記第２の引算回路の上記第
１の極性のみの出力電流に応じた電流を吐き出す
第２の差動回路と、該第１及び第２の差動回路の
出力電流を加算する加算回路とから構成したこと
を特徴とする整流回路。 (2) 上記第１及び第２の差動回路を、夫々上記
第１の極性のみの出力電流を吸い込む差動回路に
代えたことを特徴とする特許請求の範囲第１項記
載の整流回路。[Claims for Utility Model Registration] (1) A voltage/current conversion circuit that converts the voltage of a signal source into an in-phase non-inverting current and an opposite-phase inverting current, and a current that is obtained by subtracting the inverting current from the non-inverting current. a first subtraction circuit for extracting a current, a second subtraction circuit for extracting a current obtained by subtracting the non-inversion current from the inversion current, and a rectification output circuit for rectifying the current obtained from the first and second subtraction circuits. and a current mirror rectifier circuit having a current mirror rectifier circuit, wherein the rectifier output circuit is connected to a first differential circuit that outputs a current according to an output current of only the first polarity of the first subtraction circuit; A second differential circuit that discharges a current corresponding to the output current of only the first polarity of the second subtraction circuit, and an addition circuit that adds the output currents of the first and second differential circuits. A rectifier circuit characterized by comprising: (2) The rectifier circuit according to claim 1, wherein the first and second differential circuits are each replaced with a differential circuit that sucks an output current of only the first polarity.
JP1989117998U 1989-10-09 1989-10-09 Rectifier circuit Expired - Fee Related JPH0729748Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989117998U JPH0729748Y2 (en) 1989-10-09 1989-10-09 Rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989117998U JPH0729748Y2 (en) 1989-10-09 1989-10-09 Rectifier circuit

Publications (2)

Publication Number Publication Date
JPH0360885U true JPH0360885U (en) 1991-06-14
JPH0729748Y2 JPH0729748Y2 (en) 1995-07-05

Family

ID=31666192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989117998U Expired - Fee Related JPH0729748Y2 (en) 1989-10-09 1989-10-09 Rectifier circuit

Country Status (1)

Country Link
JP (1) JPH0729748Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008144405A (en) * 2006-12-07 2008-06-26 Hayashiguchi Kogyo Kk Roll screen device
US11482945B2 (en) 2019-10-03 2022-10-25 Asahi Kasei Microdevices Corporation Rectifying circuit to reduce DC offset current

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225358A (en) * 1982-06-25 1983-12-27 Mitsubishi Electric Corp Absolute value circuit
JPS60187262A (en) * 1984-03-02 1985-09-24 Rohm Co Ltd Full-wave rectifier circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58225358A (en) * 1982-06-25 1983-12-27 Mitsubishi Electric Corp Absolute value circuit
JPS60187262A (en) * 1984-03-02 1985-09-24 Rohm Co Ltd Full-wave rectifier circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008144405A (en) * 2006-12-07 2008-06-26 Hayashiguchi Kogyo Kk Roll screen device
US11482945B2 (en) 2019-10-03 2022-10-25 Asahi Kasei Microdevices Corporation Rectifying circuit to reduce DC offset current

Also Published As

Publication number Publication date
JPH0729748Y2 (en) 1995-07-05

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