JPH0361343B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This method relates to a method suitable for manufacturing a semiconductor device called I ² L, which combines a horizontal transistor and a vertical transistor. A method for manufacturing a semiconductor device including a lateral transistor and a vertical transistor, the purpose of which is to easily realize a semiconductor device having an improved switching characteristic by eliminating carrier accumulation in such a region. A step of forming an insulating film on the surface of a semiconductor layer of one conductivity type, and a step of forming a buried insulating film that insulates a horizontal transistor region and a vertical transistor region by selective oxidation. Next, a step of opening a window exposing the semiconductor layer by removing a bird's beak portion at a predetermined side of the buried insulating film, and then a step of opening a window exposing the semiconductor layer in the lateral transistor region. forming a conductor layer made of polycrystalline silicon containing impurities of opposite conductivity type to connect the window and the window in the vertical transistor region, and then diffusing the impurity in the conductor layer to The structure includes a step of forming an emitter region and a collector region in the transistor region, and a base contact region in the vertical transistor region.

[Industrial Application Field] The present invention relates to a method suitable for manufacturing a semiconductor device called I ² L, which is a combination of a lateral transistor and a vertical transistor.

I ² L is a so-called planar bipolar transistor in which the emitter and collector are reversed.
It is a logic element with a composite structure of an inverted vertical transistor and a complementary lateral transistor whose collector is the base of this transistor. This logic element applies a DC power supply voltage to the emitter of the lateral transistor, which causes the transistor to form an inverted vertical structure.
It operates as an injector that injects charge into the base of the transistor, and an inverted vertical transistor operates as an inverter, allowing high-speed operation with small logic amplitude, low electrode consumption, and high integration. It is attracting attention as a device that can coexist with conventional bipolar integrated circuits on the same chip.

[Conventional technology]

FIGS. 13a and 13b show a cutaway side view and a plan view of a main part for explaining a conventional I ² L device.

In the illustrated I ² L device, p-type regions 2 and 3 are formed in an epitaxially grown n ^- type semiconductor layer 1, and an n-type region 4 is formed in the p-type region 3. The part Q _L surrounded by is the pnp lateral transistor for the injector, and the part Q _V surrounded by the broken line is for the inverter.
They constitute each npn vertical transistor, and the junctions included in the active regions, Q _L and Q _V , are necessary for transistor action and constitute other junctions. The parts act as conductors in operation.

This I ² L device can be manufactured by applying a normal bipolar integrated circuit manufacturing method, and a partial oxidation technique is used to isolate the I ² L element group.

The feature of I ² L is that a collector, which corresponds to a conventional emitter, is formed in a single relatively large base region, and there is no need to isolate the collectors from each other, making it possible to achieve the above-mentioned high degree of integration. There is.

[Problem to be solved by the invention]

Considering the function of I ² L described above, the semiconductor region necessary for I ² L is the opposing p-type region in the case of a pnp lateral transistor, and the area under the collector region in the case of an npn vertical transistor. It is limited to the base area and emitter area of
The other base region portions not only play a role as a conductor, but also deteriorate the switching characteristics due to the capacitance of the junction and the accumulated charge of the carrier in the unnecessary region portions.

According to the present invention, in the above-mentioned type of semiconductor device, by leaving only the necessary active region and forming an insulating layer on other unnecessary parts, it is possible to easily realize a semiconductor device with improved switching speed and other functions. like,
In addition, in order to easily realize an I ² L device in which the base region of the vertical transistor of the I ² L device is divided and the bases are connected to each other on the buried insulating film, The bird's beak portion of the insulating film is removed and impurities are introduced into the exposed semiconductor layer to form the emitter region and collector region of the lateral transistor as well as the base contact region of the vertical transistor. , attempts to easily realize an I ² L device having a conductor layer connecting the base contact region and the collector region.

[Means to solve the problem]

According to the present invention, in a semiconductor device including a horizontal transistor and a vertical transistor, the vertical transistor includes (a) a base region having an area necessary for transistor operation and distributed in a dispersed manner; a buried insulating film that surrounds each base region and insulates them from each other; (c) a conductive layer that is on the buried insulating film and connects each base region; (d) provided on a part of the conductive layer. a base connection; and (e) a collector connection formed on each of the distributed base regions.

That is, a plurality of mesa portions are formed on one surface of a semiconductor substrate of one conductivity type. The emitter region and collector region of the lateral transistor in the I ² L device are formed in the first mesa portion, and the vertical transistor is formed in the second mesa portion. A buried insulating film that surrounds a plurality of mesa portions and insulates them from each other is provided on one surface of the substrate. Preferably, the lateral and vertical transistors have the minimum dimensions necessary for transistor operation; for this purpose, the emitter and collector of the lateral transistor and the base contact area of the vertical transistor are It is formed locally adjacent to the embedded insulating film. In order to form these regions, it is preferable to expose a predetermined side portion of the upper surface of the mesa portion, and introduce impurities from the exposed mesa portion to form the above-mentioned local region. Most preferably, the bird's beak generated at the same time as the buried insulating film is formed by local oxidation is removed by etching, and the impurity is introduced through the exposed mesa portion, thereby achieving the minimum dimension. Each area can be realized. The collector region of the lateral transistor and the base contact region of the vertical transistor are electrically connected by a conductive layer disposed on a buried insulating film between them. The plurality of vertical transistors are formed in a series of plural mesa parts, and these are insulated from each other by a buried insulating film, and in order to have each base at a common potential, the base contact layer of the adjacent vertical transistors are conductively connected by the conductor layer. A feature of the present invention is that a buried insulating film is applied to the I ² L vertical transistor, thereby achieving high speed I ² L devices.

As described above, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a lateral transistor and a vertical transistor, and includes a semiconductor layer of one conductivity type (for example, an n ^- type). A process of forming an insulating layer (for example, an oxide film 14, etc.) on the surface of the semiconductor layer 13), and then forming a buried insulating film (for example, a thick oxide film 1) that insulates the horizontal transistor region and the vertical transistor region.
6) by selective oxidation;
a step of opening a window exposing the semiconductor layer by removing a bird's beak portion on a predetermined side of the buried insulating film; A step of forming a conductor layer (for example, a polycrystalline silicon film 20) made of polycrystalline silicon containing an impurity of an opposite conductivity type and connecting the window in the transistor region, and then diffusing the impurity in the conductor layer. The method includes a step of forming an emitter region and a collector region in the horizontal transistor region, and a base contact region in the vertical transistor region.

[Effect]

By adopting the above-mentioned means, it is possible to easily manufacture an I ² L type semiconductor device in which only the necessary active region is present, and unnecessary portions are made into insulating layers to improve switching characteristics.

Embodiment FIGS. 1a and 1b are plan explanatory diagrams of the main parts of a semiconductor device manufactured according to an embodiment of the present invention, and the main parts cut along the line A-A' shown in a and seen in the direction of the arrow. It represents a cut side explanatory view.

In the figure, 11 is a silicon semiconductor substrate, 12
13 is an n ⁺ type buried layer, 13 is an n ⁻ type semiconductor layer, 16 is an oxide film, 18 is a p ⁻ type active base region, 19 is an n type region, 20 is a polycrystalline silicon film, 21 is a p ⁺ type region, 22 is the p ⁺ type region of the injector, 23 is the oxide film, 24 is the n ⁺ type contact region, 25 and 2
6 indicates electrodes. Note that the pnp type transistor part and the npn transistor part are a in the figure.
Instructions are given in .

Figures 2 to 7 are cross-sectional side views of important parts at key points in the process to explain the manufacturing of the semiconductor devices shown in Figures 1a and b. I will explain while referring to it. Furthermore, the first
Symbols used in the drawings indicate the same parts or have the same meaning.

See Figure 2 (2)-1 A p-type or n-type silicon semiconductor substrate 11 (see Figure 1) with an n ⁺ type buried layer 12 and a thickness of ~2
Conventional techniques are used until the epitaxial growth of the n ^- type semiconductor layer 13 of about [μm] is formed.

(2)-2 By applying a thermal oxidation method, an oxide film 14 having a thickness of, for example, about 1000 to 1300 [Å] is formed.

(2)-3 Chemical vapor deposition
By applying the deposition (CVD) method,
A silicon nitride film 15 having a thickness of, for example, about 2500 Å is formed, and this is patterned using normal photolithography technology, leaving a layer covering the active region such as the PNP transistor formation region and the NPN transistor formation region. and remove the others.

Refer to FIG. 3 (3)-1 By applying a selective thermal oxidation method, a thick oxide film 16 having a thickness of, for example, about 1.5 [μm] is formed. It goes without saying that this includes the oxide film 14.

(3)-2 In the next step, the oxide films 16 and 14 are etched to expose a part of the n ^- type semiconductor layer 13 around the active region, and in a later step, p-type impurities are added to the exposed portion. In order to prevent short-circuiting between adjacent elements due to ^{the p + impurity} region,
The extent to which oxide films 16 and 14 are etched must be limited.

Therefore, in this step, a mask 17 made of a photoresist film is formed (see especially the sandy area in FIG. 1a). That is, etching of the oxide film 16 in the region between adjacent elements 51 is prevented, and the n ^- type semiconductor layer is prevented from being exposed. Note that the symbol 52 indicates the area where the bird's beak is formed.

Refer to FIG. 4 (4)-1 Etching the oxide film 16 and side etching the oxide film 14.

By adopting this step, the n ^- type semiconductor layer portion 13 is exposed in a portion commonly called a bird's beak. The remaining thickness of the oxide film 16 at this time was about 7000 [Å].

See Figure 5 (5)−1 The silicon nitride film 15 is removed.

(5)-2 Photo area covering the pnp transistor formation area
A resist film mask (not shown) is formed.

(5)-3 By applying the ion implantation method, the acceleration energy was increased to 180 [KeV] and the dose was increased to 2×
The base region 18 is formed by implanting boron ions at a concentration of 10 ¹² [cm ^-2 ].

(5)-4 By applying the same ion implantation method,
Boron ions were implanted at an acceleration energy of 360 [KeV] and a dose of 3×10 ¹³ [cm ^-2 ] to form an n-type region 19 corresponding to the collector region.
form.

See Figure 6 (6)-1 By applying the CVD method, the thickness, e.g.
A polycrystalline silicon film 20 having a thickness of about 4000 [Å] is grown.

(6)-2 Patterning of the polycrystalline silicon film 20 is performed by applying photolithography technology.

(6)-3 Diffuse boron to make the polycrystalline silicon film 20 conductive. At this time, boron is also diffused into the n ^- type semiconductor layer portion 13 exposed at the bird's beak portion, forming a p ⁺ type region 21 and a p ⁺ type region 22 of the injector. Incidentally, since the thermal diffusion treatment is performed in an oxidizing atmosphere, an oxide film 23 having a thickness of, for example, about 3000 Å is formed on the entire surface.

Refer to Figure 7 (7)-1 By applying photolithography technology, windows for impurity diffusion are opened in the oxide films 23 and 14, and then n-type impurities are diffused to form n ⁺
A mold contact region 24 is formed.

(7)-2 Opening windows for electrode contacts is performed by applying photolithography technology, and then forming 25 and 26.

In the semiconductor device manufactured in this way, all the unnecessary parts explained with reference to FIG. 13 are made into oxide films 16.

Now, in the case of the present invention, it is important to expose a part of the n ^- type semiconductor layer by etching the bird's beak portion, so one of the preferred methods will be explained.

FIGS. 8 to 10 are cross-sectional side views of essential parts of a semiconductor device for explaining the preferred method, and the following description will be made with reference to these figures.

See FIG. 8 (8)-1 The silicon semiconductor substrate 31 is thermally oxidized to form an oxide film 32 having a thickness of, for example, about 500 to 1000 Å.

(8)-2 By applying the CVD method, the thickness, e.g.
A silicon nitride film 33 having a thickness of approximately 1000 to 4000 Å is formed.

(8)-3 By applying the CVD method, the thickness, e.g.
Silicon dioxide film 34 of about 1000 to 4000 [Å]
form.

(8)-4 By applying photolithography technology, the silicon dioxide film 34 and the silicon nitride film 33 are patterned to expose the portion where a thick oxide film is to be formed.

(8)-5 Selective oxidation is performed by applying a thermal oxidation method to form a thick oxide film 35 having a thickness of, for example, about 8,000 to 15,000 [Å].

Refer to FIG. 9 (9)-1 During the thermal oxidation treatment in step (8)-5, the thickness formed on the exposed portion (end surface portion) of the silicon nitride film 33 is, for example, about 50 to 200 [Å]. Remove the oxide film by etching.

(9)-2 Side etching of the silicon nitride film 33 is performed by applying, for example, a dipping method using hot phosphoric acid as an etchant. The effective amount is approximately 5,000 to 10,000 [Å] in the lateral direction.

Refer to Figure 10 (10)-1 Etching the oxide film 35 and
A portion of the silicon semiconductor substrate 31 is exposed at the beak portion. At this time, the silicon dioxide film 34
are also removed by the etching.

(10)-2 The silicon nitride film 33 is replaced by the silicon dioxide film 34
Remove with.

According to this technique, the substrate 31 can be exposed in the bird's beak portion while maintaining the thick oxide film 35 and the thin oxide film 32 in a practically sufficient state.

As can be seen from the above description, in the I ² L type semiconductor device obtained according to the present invention, the so-called active region is kept to the necessary minimum in order to obtain the junction necessary for transistor operation. All the parts that conventionally had only the function of a conductor are now oxide films, and the conductor function is taken care of by the silicon layer on the oxide film. It is possible to eliminate the reduction in switching speed caused by the presence of a switch.

By the way, it has been proposed that the propagation delay time t _pd and drive current or power of an I ² L device generally have the relationship shown in FIG. 11a.

In other words, in a region where the drive current is relatively small, the extrinsic delay time is expressed as _tde , and as the current increases, the delay time becomes the intrinsic delay time.・It has characteristics determined by time) _tdi and resistive delay time (resistive delay time) _tdr . And (a) t _de depends on the junction capacitance and wiring capacitance and is inversely proportional to the current. That is, p・t _de ≒1/42−αα′/αVΔV (C _EB +2C _CB ) However, p is the power consumption per gate V is the injector voltage ΔV is the logic amplitude α is the common base current gain α′ is the reverse base Ground current gain C _EB indicates emitter-base junction capacitance C _CB indicates base-collector junction capacitance.

In conventional I ² L devices, C _EB /2C _CB ≒ 1/1~
2/1, and in the I ² L device obtained according to the present invention, the dimensions of the conventional I ² L device are
When defined as shown in Figure 1b, the area of C _EB is 6(l ₁ + l ₂ ) d/L・W d:p The width of ^{the +} type region 21, which can be reduced to less than 1/10. be.

(b) t _di depends on the rise of the collector current IC and the amount of charge accumulated in the n ^- type region 13, and t _di ∝Q _N- /I _C ∝1/N _D・S _E /S _C However, Q _N- is the amount of accumulated charge in the n ^- region N _D is the impurity concentration S _E in the n ^- region, and the emitter area S _C is expressed as the collector area.

In the structure of the semiconductor device obtained according to the present invention, S _E /S _C can be reduced to several times by reducing S _E .

(c) t _dr depends on the base lateral resistance, t _dr and t _de
t _pd cannot be realized below the point where . In the semiconductor device obtained according to the present invention, a polycrystalline silicon film is doped with boron at a high concentration when forming the base region, and a sheet resistance ρ _s similar to that of a normal base can be achieved.

There are advantages such as

The present invention can be modified in various ways, and other embodiments will now be described.

In general, a shot collector structure is known as an I ² L device, and such a structure can also be used in the present invention without going through the step (7)-1, that is, n ⁺ type contact area type 24
This can be achieved by entering the following steps (7)-2 and below without forming.

Further, in the embodiment, the polycrystalline silicon film 20
However, this polycrystalline silicon film 20 is made of, for example, a heat-resistant metal doped with boron, such as tungsten, molybdenum, platinum,
Alternatively, such silicides can be substituted, and in that case, a refractory metal doped with boron is formed and patterned, and then an oxide film 23 is preferably formed and the diffusion is performed therein. It is preferable to form the p ⁺ type regions 21 and 22 by performing a process.

Furthermore, the steps (6)-1 to (6)-3 can be modified as follows.

(6)-1 By applying an ion implantation method or the like, the exposed n ^- type semiconductor layer portion 13 is doped with boron to form p ⁺ type regions 21 and 22.

(6)-2 A metal layer such as Al, Mo, MoSi, etc. is deposited on the entire surface and then patterned.

(6)-3 The insulating film 23 is formed by applying a normal vapor phase growth method or the like.

In the above step (6)-2, when a heat-resistant metal material such as Mo is used, the step in the above embodiment
By performing the steps after (7)-1, an external base connection using a metal conductor instead of polycrystalline silicon can be obtained. Furthermore, when a metal material that does not have heat resistance such as Al is used, it may be applied when forming a silicon collector that does not require a subsequent diffusion process.

In the semiconductor device shown in FIG. 1, when exposing the n ^- type semiconductor layer 13, it was done on all four sides of the rectangular silicon nitride film in the npn transistor part, but in order to miniaturize the device, it was The n ^- type semiconductor layer 13 may be exposed by etching only two sides, or in some cases, only one side.

FIG. 12a is an explanatory plan view of the main part of the npn transistor part in an I ² L device in which the semiconductor layer 13 is exposed only on two opposing sides, and FIG. 12b is a line B-B seen in a. Each figure is a cross-sectional explanatory view of the main part taken along the line 1, and the symbols used in FIGS. 1 to 7 indicate the same parts or have the same meanings.

In the step (4)-5, the oxide films 16 and 14 are
As shown in FIG. 12a, the n ^- type semiconductor layer 13 is exposed only in the area indicated by the symbol 52, and the p ⁺ type region 21 is formed by performing p ⁺ type diffusion there. When forming the mask and opening the window as in step (7)-1 above, alignment margin can be obtained by making the upper and lower ends of the mask overlap the thick oxide film 16.

〔Effect of the invention〕

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a lateral transistor and a vertical transistor, the method comprising:
a step of forming an insulating film on the surface of the semiconductor layer of one conductivity type, a step of forming a buried insulating film that insulates the horizontal transistor region and the vertical transistor region by selective oxidation; a step of opening a window exposing the semiconductor layer by removing a bird's beak portion on a predetermined side of the buried insulating film; forming a conductor layer made of polycrystalline silicon containing impurities of opposite conductivity type to be connected to the window in the transistor region, and then diffusing the impurity in the conductor layer to form a conductor layer in the lateral transistor region. forming emitter and collector regions in the vertical transistor regions and base contact regions in the vertical transistor regions.

By employing the above structure, it is possible to easily manufacture an I ² L type semiconductor device in which only necessary active regions exist and unnecessary parts are made into insulating layers to improve switching characteristics.

[Brief explanation of drawings]

FIGS. 1a and 1b are an explanatory plan view of the main part of a semiconductor device manufactured according to an embodiment of the present invention, and a cutaway side view of the main part taken along the line A-A' shown in FIG.
2 to 7 are cut-away side views of essential parts of a semiconductor device at key points in the process to explain one embodiment of the present invention, and FIGS. 8 to 10 illustrate preferred examples of oxide film etching. FIG. 11a is an explanatory cross-sectional side view of the main part of the semiconductor device at key points in the process for manufacturing the semiconductor device. FIG. 11b is an explanatory plan view of essential parts showing the dimensions of a conventional I ² L device, and FIGS. 12 a and b are longitudinal directions of an I ² L device according to another embodiment of the present invention. Figures 13a and 13b are explanatory plan views and cross-sectional side views of the main parts of the ^transistor section, respectively. each represents. In the figure, 11 is a silicon semiconductor substrate, 12
13 is an n ⁺ type buried layer, 13 is an n ⁻ type semiconductor layer, 16 is an oxide film, 18 is a p ⁻ type active base region, 19 is an n type region, 20 is a polycrystalline silicon film, 21 is a p ⁺ type region, 22 is the p ⁺ type region of the injector, 23 is the oxide film, 24 is the n ⁺ type contact region, 25 and 2
6 indicates electrodes.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including a lateral transistor and a vertical transistor, comprising: forming an insulating film on the surface of a semiconductor layer of one conductivity type; and then forming a lateral transistor region. forming a buried insulating film by selective oxidation that insulates the vertical transistor region; and then removing bird's beak portions at predetermined sides of the buried insulating film. opening a window exposing the layer; and then a conductor made of polycrystalline silicon containing impurities of opposite conductivity type connecting the window in the lateral transistor region and the window in the vertical transistor region. forming a layer, and then diffusing impurities in the conductor layer to form an emitter region and a collector region in the lateral transistor region and a base contact region in the vertical transistor region. A method for manufacturing a semiconductor device, comprising: