JPH0361386B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] After converting the received high-speed serial data into parallel data and detecting whether the bits at the same position in each frame are the same data or different data, the data error detection circuit converts the received high-speed serial data into parallel data. A plurality of outputs obtained by inverting the detection output and performing a logical product are stored, and it is detected whether or not this pattern matches a specific pattern to detect errors in low-speed data.

[Industrial application field]

The present invention relates to a data error detection circuit used in a data transmission system in which low-speed data of a plurality of channels are each repeated n times and transmitted over a high-speed transmission path.

Generally, there are various methods for transmitting low-speed data over high-speed transmission lines, one of which is to repeat the low-speed data of multiple channels n times each.
A high-speed method in which the repeated first part is inserted into the first high-speed frame, and the n-th part is inserted into the n-th high-speed frame, thereby converting it into serial data and transmitting the same data N times over a high-speed transmission line. There is a universal transmission method.

FIG. 4 shows the format for transmitting low-speed data using the high-speed universal transmission method.

In the figure, the low-speed data is the same data from the rising edge of the "low-speed data clock" (indicated by an upward arrow) to the next rising edge, but this part is referred to as the "high-speed universal clock" and the "low-speed data clock". The number of repetitions is determined by the speed ratio with "Tsuku".

For example, if the speed ratio is 5, the first bit of channel 1 (hereinafter abbreviated as CH1) is D _1-1 to _{D 1-5.}
The same data is inserted into the first to fifth high-speed frames as shown in "high-speed universal data", . . . in FIG. 4.

The same data of other CHs are also inserted into the first to fifth high speed frames in the same way.

On the other hand, the number of CHs for low-speed data that can be transmitted depends on the ratio of "high-speed frame" to "high-speed universal clock." For example, if this ratio is 8, the number of CHs will be 8, but as shown in the figure, the number of CHs for low-speed data The number is 6 because the F and S bits indicating the beginning and end of the data must be inserted.

When transmitting low-speed data using such a transmission system, it is desired to be able to detect errors in the low-speed data in the state of high-speed universal data without reducing transmission capacity.

[Conventional technology]

When transmitting low-speed data using the high-speed universal transmission method using the frame format shown in Figure 4, the receiving side receives high-speed frames and high-speed universal data, but since the low-speed data clock is not sent, the data is transmitted at a low speed. The number of divided transmissions of the same data is unknown.

Therefore, in the state of high-speed universal data, errors in low-speed data that occur on the transmission path are not detected and output as is.

[Problem that the invention seeks to solve]

However, if a low-speed data clock is sent from the transmitting side, the number of divisions between this clock and the high-speed universal clock extracted from high-speed universal data can be determined, making it possible to detect errors in low-speed data in the state of high-speed universal data. However, since information unrelated to data transmission must be sent, the transmission capacity decreases or additional lines must be installed. Therefore, there is a problem in that errors in low-speed data must be detected in the state of high-speed universal data (hereinafter referred to as high-speed serial data) even if the low-speed data clock is not sent.

[Means for solving problems]

As shown in Fig. 1, the above problem is caused by the serial/parallel converting means 1 that converts received high-speed serial data into parallel data, and the output of the serial/parallel converting means at the same position in each frame. Sameness/difference detection means 2 for sequentially detecting whether certain bits are the same data or different data; and a memory section 3 for storing the output obtained by inverting the outputs of the sameness/difference detection means and performing a logical product.
This problem is solved by the data error detection circuit of the present invention, which comprises: and an error detection means 4 which detects whether the pattern stored in the memory section matches a specific pattern and sends out an error alarm when the pattern matches the specific pattern. .

[Effect]

When transmitting low-speed data using a high-speed universal transmission method, the present invention transmits the same data multiple times in high-speed frames, so by utilizing the redundancy of this transmission method, bits at the same position in each high-speed frame are Errors in the data can be detected from the results.

That is, high-speed serial data is converted into serial/parallel converter 1.
After converting the data into parallel data using the same/difference detection means 2 to detect whether the bits at the same position in each frame are the same or different, this output is inverted and the ANDed data is stored in the memory section 3. store. When the pattern stored here is a specific pattern, it is determined that the error has occurred in an isolated bit, and the error detection means sends out a warning.

As a result, errors in low-speed data can be detected in the state of high-speed serial data even if the low-speed data clock is not sent.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. The shift registers 11, 12, and 13 are serial/parallel conversion means 1, the AND circuit 21, the AND circuit 22 with input inversion, the all 1/all 0 detection means 2, the AND circuit 31 with input inversion, and the 4-bit shift register 32. The memory section 3, the AND circuit 41, the AND circuit 42 with partial input inversion, and the OR circuit 43 are components of the error detection means 4.

Below, as shown in Figure 3, the first bit of the low-speed data on CH5 is 1, the second bit is 0, and the third bit is 0. The operation in FIG. 2 will be explained with reference to FIG. 3 assuming that an error has occurred (the part marked * in the figure).

First, the high-speed serial data shown in Figure 3 is input to the serial/parallel converting means 1.
Since shift registers (hereinafter abbreviated as SR) 11, 12, and 13 that can store data for frames are connected in cascade, three frames of high-speed serial data can be stored. Next, as shown in Figure 3-
The first bit, a total of 3 bits, is taken out in parallel from SR11, 12, and SR13 and added to the AND circuit 21 and the AND circuit 22 with input inversion, and from there, 1,
0 is output (see Figure 3).

And this output is AND circuit 3 with input inversion
The AND is performed again on 1, and as shown in Figure 3, 0 is output and stored in the 4-bit SR32.
As shown in FIG. 3, the data of CH5 is sequentially inputted to this SR from SRs 11, 12, and 13 via the same/difference detection means 2 and the AND circuit 31 with input inversion. Therefore, the 4-bit pattern stored while being updated one after another is applied to an AND circuit 41 and an AND circuit 42 with input inversion in order to determine whether or not it matches a specific pattern.

Here, according to the simulation, Figure 3-
As shown in the figure, 1 is output from the AND circuit 31 with input inversion when the frame changes or when the data is 1.
In the former case, there are two consecutive 1's,
In the latter case, it was found that there were three consecutive cases. Also, if the condition of the transmission path is poor and there are many errors, use SR32.
Since the output of is all 1, the specific pattern is 0, 1, 1, 1 and 1, 1, considering both states.
1, 1.

Therefore, if a 1 is output from the AND circuit 42 when a pattern is added from the SR 32, an isolated error has occurred, and if a 1 is output from the AND circuit 42, there are many errors. An alarm 1 is output through the OR circuit 43 as shown in FIG.

Note that when the SR 32 has n stages, the specific pattern is (n-1) or "all 1s".

〔Effect of the invention〕

As described above in detail, the present invention has the advantage that errors in low-speed data can be detected in the state of high-speed serial data even without a low-speed data clock.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is a high-speed universal transmission method for transmitting low-speed data. This shows the frame format at the time. In the figure, 1 is a serial/parallel conversion means, 2 is an identity/difference detection means, 3 is a memory section, and 4 is an error detection means.

Claims (1)

[Claims] 1. Low-speed data of multiple channels are each repeated n times, and the repeated first part is inserted into the first high-speed frame, and the n-th part is inserted into the n-th high-speed frame over several frames. In a data transmission method that converts the received high-speed serial data into parallel data and transmits it through a high-speed transmission line by , a sameness/difference detection means 2 for sequentially detecting whether bits at the same position in each frame are the same data or different data, and an output obtained by inverting the outputs of the sameness/difference detection means and performing a logical product is stored. A data error characterized in that it is comprised of a memory section 3 and an error detection means 4 that detects whether or not the pattern stored in the memory section matches a specific pattern and sends out an error alarm when they match. detection circuit.