JPH0361700U - - Google Patents

Info

Publication number
JPH0361700U
JPH0361700U JP12185789U JP12185789U JPH0361700U JP H0361700 U JPH0361700 U JP H0361700U JP 12185789 U JP12185789 U JP 12185789U JP 12185789 U JP12185789 U JP 12185789U JP H0361700 U JPH0361700 U JP H0361700U
Authority
JP
Japan
Prior art keywords
redundant
memory cell
circuit
cell
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12185789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12185789U priority Critical patent/JPH0361700U/ja
Publication of JPH0361700U publication Critical patent/JPH0361700U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の冗長回路の回路図
、第2図は従来の冗長回路の回路図である。 1,5……制御回路、2,3,4,6,7……
インバータ、A,B,C,D,E,F,H,I…
…制御信号、G,J……出力信号、Q1,Q11
……EPROMセル、Q2,Q12,Q16……
Nチヤンネル型デイプレツシヨントランジスタ、
Q3,Q4,Q5,Q6,Q13,Q14,Q1
7,Q18……Pチヤンネル型エンハンストラン
ジスタ、Q7,Q8,Q9,Q10……Nチヤン
ネル型エンハンストランジスタ。
FIG. 1 is a circuit diagram of a redundant circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional redundant circuit. 1, 5... control circuit, 2, 3, 4, 6, 7...
Inverter, A, B, C, D, E, F, H, I...
...Control signal, G, J...Output signal, Q1, Q11
...EPROM cell, Q2, Q12, Q16...
N-channel type depletion transistor,
Q3, Q4, Q5, Q6, Q13, Q14, Q1
7, Q18...P channel type enhancement transistor, Q7, Q8, Q9, Q10...N channel type enhancement transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メインセルとの冗長代替情報を、パツケージ封
入前、後にそれぞれ書込むことができる第1,第
2のメモリセルを備え、前記第1のメモリセルの
情報を前記第2のメモリセルに転送せしめる回路
を設けたことを特徴とする冗長回路。
A circuit comprising first and second memory cells in which redundant alternative information to the main cell can be written before and after packaging, respectively, and transferring information in the first memory cell to the second memory cell. A redundant circuit characterized by being provided with.
JP12185789U 1989-10-17 1989-10-17 Pending JPH0361700U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12185789U JPH0361700U (en) 1989-10-17 1989-10-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12185789U JPH0361700U (en) 1989-10-17 1989-10-17

Publications (1)

Publication Number Publication Date
JPH0361700U true JPH0361700U (en) 1991-06-17

Family

ID=31669878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12185789U Pending JPH0361700U (en) 1989-10-17 1989-10-17

Country Status (1)

Country Link
JP (1) JPH0361700U (en)

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