JPH0361767U - - Google Patents
Info
- Publication number
- JPH0361767U JPH0361767U JP12196689U JP12196689U JPH0361767U JP H0361767 U JPH0361767 U JP H0361767U JP 12196689 U JP12196689 U JP 12196689U JP 12196689 U JP12196689 U JP 12196689U JP H0361767 U JPH0361767 U JP H0361767U
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- detection output
- video detection
- separation circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 4
- 230000005856 abnormality Effects 0.000 claims 2
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Picture Signal Circuits (AREA)
- Television Receiver Circuits (AREA)
Description
第１図は本考案の一実施例に係る自動利得制御
回路が組込まれたテレビジヨン受像機を示すブロ
ツク図、第２図は実施例の動作を説明するための
グラフ、第３図はテレビジヨン受像機を示すブロ
ツク図、第４図は第３図中のＡＧＣ回路６の構成
を具体的に示す回路図、第５図は第４図の動作を
説明するためのタイミングチヤート、第６図はゴ
ースト妨害を受けた場合の検波出力を示す波形図
、第７図は従来の自動利得制御回路を示す回路図
、第８図は第７図の問題点を説明するためのグラ
フである。
４……ＶＩＦアンプ、５……映像検波回路、１
０……端子、１１……ＡＧＣ制御部、１２……時
定数切換部、１３……オペアンプ、１５……同期
分離回路、１６……選局回路、Ｃ１，Ｃ３……コ
ンデンサ、ＳＷ……スイツチ。
FIG. 1 is a block diagram showing a television receiver incorporating an automatic gain control circuit according to an embodiment of the present invention, FIG. 2 is a graph for explaining the operation of the embodiment, and FIG. 4 is a circuit diagram specifically showing the configuration of the AGC circuit 6 in FIG. 3, FIG. 5 is a timing chart for explaining the operation of FIG. 4, and FIG. 6 is a block diagram showing the receiver. FIG. 7 is a waveform diagram showing the detection output when ghost interference is received, FIG. 7 is a circuit diagram showing a conventional automatic gain control circuit, and FIG. 8 is a graph for explaining the problems in FIG. 7. 4...VIF amplifier, 5...video detection circuit, 1
0...terminal, 11...AGC control section, 12...time constant switching section, 13...operational amplifier, 15...synchronization separation circuit, 16...tuning circuit, C1, C3...capacitor, SW...switch .
Claims (1)
比較結果に基づいて第１のコンデンサを充放電す
ることによりＡＧＣ制御電圧を発生して映像中間
周波増幅器の利得を制御する自動利得制御回路に
おいて、 ＡＧＣの応答特性を遅くするために前記第１の
コンデンサに並列接続される第２のコンデンサと
、 前記第１コンデンサと第２のコンデンサとの間
に接続されスイツチング信号によつて前記第１及
び第２のコンデンサの並列接続を遮断するスイツ
チング素子と、 前記映像検波出力を同期分離して水平同期パル
スを出力する同期分離回路と、 前記水平同期パルスのパルス数をカウントする
ことにより前記映像検波出力の異常を検出し、こ
の異常検出時、電源投入時及び選局時に前記スイ
ツチング信号を出力する制御手段とを具備したこ
とを特徴とする自動利得制御回路。[Claims for Utility Model Registration] Comparing the video detection output level with a predetermined reference potential and charging and discharging the first capacitor based on the comparison result to generate an AGC control voltage and control the gain of the video intermediate frequency amplifier. In an automatic gain control circuit, a second capacitor is connected in parallel to the first capacitor in order to slow down the response characteristics of the AGC, and a second capacitor is connected between the first capacitor and the second capacitor and is connected to the switching signal. Therefore, a switching element that interrupts the parallel connection of the first and second capacitors; a sync separation circuit that synchronously separates the video detection output and outputs a horizontal sync pulse; and a sync separation circuit that synchronously separates the video detection output and outputs a horizontal sync pulse; and a sync separation circuit that counts the number of horizontal sync pulses. An automatic gain control circuit comprising control means for detecting an abnormality in the video detection output and outputting the switching signal when the abnormality is detected, when the power is turned on, and when a channel is selected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12196689U JPH0361767U (en) | 1989-10-17 | 1989-10-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12196689U JPH0361767U (en) | 1989-10-17 | 1989-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0361767U true JPH0361767U (en) | 1991-06-17 |
Family
ID=31669987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12196689U Pending JPH0361767U (en) | 1989-10-17 | 1989-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0361767U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003202169A (en) * | 2002-01-07 | 2003-07-18 | Denso Corp | Method for removing foreign matter in steam compression type refrigerator and foreign matter removing tank |
-
1989
- 1989-10-17 JP JP12196689U patent/JPH0361767U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003202169A (en) * | 2002-01-07 | 2003-07-18 | Denso Corp | Method for removing foreign matter in steam compression type refrigerator and foreign matter removing tank |
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