JPH036177A - Vertical outline compensating circuit of interpolating signal - Google Patents

Abstract

PURPOSE:To prevent the generation of flickering by adding an output signal of a non-linear processing circuit to an adaptive type interpolating signal obtained by mixing the present video signal and a first and a second delay signals and outputting an interpolating signal to which a vertical outline compen sation is performed. CONSTITUTION:The present video signal A, an output 263H delay signal B of a 1H delaying circuit 2 and a 262H delaying circuit 1 and an output C of a 1H delaying circuit 10 are inputted to an interpolating filter 13, and by mixing them, an adaptive type interpolating signal is obtained. In this state, an inter- field difference signal of an interpolating signal outputted from a subtracting circuit 15 passes through an LPF 16 and applied to a non-linear processing circuit 17. A vertical outline compensating component signal of an interpolating signal outputted from this non-linear processing circuit 17 is inputted to an adding circuit 18, and added to an adaptive type interpolating signal applied from the interpolating filter circuit 13. In such a way, from the adding circuit 18, the adaptive type interpolating signal brought to vertical outline compensa tion is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical contour compensation circuit for creating an interpolation signal necessary for progressive scan conversion and for applying vertical contour enhancement to this interpolation signal.

Conventional technologyIn response to demands for higher image quality in television receivers, IDTV
, EDTV, and other systems have been developed or realized. These methods perform sequential scanning (non-interlaced scanning), which requires the creation of interpolation signals. This interpolation signal is created by interpolation between lines or interfields, but depending on the presence or absence of movement in one image and its degree, interpolation between lines or interfields can be switched as appropriate, or the video signal between lines or fields can be mixed. It is said that it is preferable to change the ratio. In addition, to create an interpolated signal,
It is desirable to take measures to prevent flickering (line flicker) as much as possible.

On the other hand, in order to improve the sharpness of one image, not only horizontal edge enhancement but also vertical edge enhancement is necessary.

Since the interpolation signal is a type of average value signal, it works in the direction of blurring one contour, so vertical contour compensation is an essential technique.

Vertical edge enhancement is generally performed by adding an inter-field difference signal or an inter-frame difference signal to the original signal, but it is necessary to take into account the degree of movement of one image. This is because the level of the difference signal mentioned above is related to the vertical contour when there is little or no movement, but as the movement increases, more difference components due to movement are included.

Problems to be Solved by the Invention The present invention provides a circuit that creates an interpolation signal that can prevent the occurrence of flickering and performs appropriate contour compensation on this interpolation signal.

Means for Solving the Problems A vertical contour compensation circuit for interpolation signals according to the present invention includes a first delay circuit that delays an input current video signal by 1H, a second delay circuit that delays an input current video signal by 263H, and an input current video signal. The current video signal to be output, the 1H delay signal output from the first delay circuit, and the 263H delay signal output from the second delay circuit are input, and according to the comparison result of the levels of these three input signals, An interpolation filter circuit that creates and outputs an adaptive interpolation signal by mixing these three input signals, an interfield difference signal creation circuit that creates and outputs an interfield difference signal of the interpolation signal, and an interfield difference signal as described above. A nonlinear processing circuit that performs predetermined nonlinear processing for vertical contour compensation on the interfield difference signal output from the creation circuit according to the level of the interfield difference signal, and a nonlinear processing circuit that performs the nonlinear processing on the adaptive interpolation signal. An adder circuit is provided that adds the output signals of the circuits and outputs an interpolated signal subjected to vertical contour compensation.

The interpolation filter circuit includes a comparison processing circuit that detects the level difference between the current video signal and the 263H delayed signal, and a level difference between the 263H delayed signal and the 1H delayed signal, and mixes and controls the output signals of the comparison processing circuit. It is controlled by a decoding circuit that converts the current video signal into a signal, and a mixing control signal given from the decoding circuit.
It is composed of a mixing circuit that outputs an adaptive interpolation signal by mixing a 3H delayed signal and a 1H delayed signal at a predetermined ratio according to the above-mentioned level difference.

Function: The current video signal, the 1H delayed signal of the same field, and the 263H delayed signal of the previous field are input, and the adaptive video signal is created by changing the mixing ratio of these signals according to the level difference between these signals. An interpolated signal is created. This adaptive interpolation signal is subjected to vertical contour enhancement processing. That is, the level of the interfield difference signal of the interpolated signal is detected,
Nonlinear processing is performed on this inter-field difference signal according to the detected level. By adding the non-linearly processed inter-field difference signal to the adaptive interpolation signal, an adaptive interpolation signal with vertical contour compensation is finally obtained.

Embodiment FIG. 1 shows a vertical contour compensation circuit according to an embodiment of the present invention. This vertical contour compensation circuit performs vertical contour compensation on both the current video signal and the interpolation signal created from it, and has the feature that a part of the five circuits can be shared.

First, the vertical contour compensation operation for the current video signal will be explained.

The video signal (luminance signal after Y/C separation) (this is called the current video signal) input to the input terminal is processed by a 262H delay circuit (field memory)1. The signal is applied to a subtraction circuit 5 and an addition circuit 8. The output signal of the 262H delay circuit 1 is given to the 1H delay circuit (line memory) 2. After all, the output of 1H delay circuit 2 is.

It is delayed by 263H from the input current video signal.

The 262H delay signal output from the 262H delay circuit 1 and the 263H delay signal output from the 1H delay circuit 2 are added in the adder circuit 3, and then multiplied by 1/2 in the 1/2 coefficient unit 4, resulting in addition. averaged. As shown in FIG. 2, the 263H delayed signal and the 262H delayed signal are signals of the previous field in interlaced scanning, and are also video signals on horizontal scanning lines that sandwich the horizontal scanning line of the current video signal above and below. Therefore, the output signal of the 21/2 coefficient unit 4 will be referred to as the previous field average video signal.

The previous field average video signal output from the 1/2 coefficient unit 4 is applied to a subtraction circuit 5. By subtracting the previous field average video signal from the current video signal in the subtraction circuit 5, an inter-field difference signal of the current video signal is obtained.

The inter-field difference signal output from the subtraction circuit 5 passes through a low-pass filter 6 and is input to a nonlinear processing circuit 7. This inter-field difference signal includes a high frequency component in the vertical direction of the image (specifically, a 15.7 KHz signal and its high frequency). The low pass filter 6 is 0.5MHz or I
It allows signals of about MHz or less to pass through, thereby removing high frequency components in the horizontal direction (which is generally high frequency noise) from the interfield difference signal. In this way, only the vertical signal component is input to the first nonlinear processing circuit 7. An example of a specific configuration of the nonlinear processing circuit 7 will be described later, but it has characteristics as shown in FIG. A signal component (contour compensation component of the current video signal) representing the vertical contour to be emphasized is output according to the current video signal.

The output signal of the nonlinear processing circuit 7 is then given to an adder circuit 8. This adding circuit 8 is supplied with a current video signal, and by adding the output signal of the nonlinear processing circuit 7 to this current video signal, a current video signal with vertical contour compensation is output from the adding circuit 8. It turns out.

Next, a vertical contour compensation circuit for interpolation signals for progressive scan conversion will be described.

The input current video signal is sent to the 1HH extension circuit 10. Addition circuit 11
and the interpolation filter circuit 13.

The output signal of the 1HH extension circuit 10 is given to an addition circuit 11 and an interpolation filter circuit 13, respectively. therefore,
The current video signal and the 1HH extended signal (see Figure 3) output from the 1HH extended circuit are added in the adder circuit 11, and further multiplied by 1/2 in the 1/2 coefficient unit 12 to generate a line interpolation signal. be done. These 1HH extension circuits 10
．． The adder circuit 11 and the 1/2 coefficient unit 12 constitute a line interpolation circuit that creates a line interpolation signal.

! The line interpolation signal output from the /2 coefficient unit 12 is given to a subtraction circuit 15. This subtraction circuit 15 is supplied with a 263H delay signal (previous field signal) output from the 1HH delay circuit 2 (2132H delay circuit 1 and 1HH delay circuit 2).
The line interpolation signal is subtracted from the 263H delay signal to obtain an interfield difference signal of the interpolation signal. As shown in Figure 3, the line interpolation signal is the arithmetic average of the current video signal and the 1HH extended signal, so 263H
It will be on the scanning line that exactly corresponds to the delayed signal. The above-described line interpolation circuit, one-field delay circuit, and subtraction circuit 15 constitute an inter-field difference signal generation circuit.

As mentioned above, the interpolation filter circuit 13 receives the current video signal (
This is represented by the symbol A) and the 1HH extended signal (this is represented by the symbol C.
) in addition to 2 output from the 1HH extension circuit 2
A 63H delayed signal (represented by symbol B) is input. As will be detailed later, the interpolation filter circuit 13 detects the level difference between signals A and B and the level difference between signals B and C, and adjusts the signals A, B, and C to predetermined values according to the detection results. An adaptive interpolation signal is created and output by mixing at a ratio of . This adaptive interpolation signal is applied to adder circuit 18.

The interfield difference signal of the interpolation signal output from the subtraction circuit 15 is passed through a low-pass filter 16 to the nonlinear processing circuit 1.
7 is given. The vertical contour compensation component signal of the interpolation signal outputted from the nonlinear processing circuit 17 is input to the addition circuit 18 and added to the adaptive interpolation signal provided from the interpolation filter circuit 13. In this way, the adder circuit 18
An adaptive interpolation signal subjected to vertical contour compensation is output from the .

The specific configuration of the interpolation filter circuit 13 will be described with reference to FIGS. 4 to 11.

FIG. 4 shows a schematic configuration of the interpolation filter circuit 13. The interpolation filter circuit 13 includes a comparison processing and decoding circuit 31 and a mixing circuit 32. Current video signal A,
A 263H delay signal B and a 1H delay signal are provided to both circuits 31 and 32, respectively. The comparison processing and decoding circuit 31 receives two input signals A, B, and C.
Based on the comparison process, control signals 81 to S4 for controlling changeover switches in the mixing circuit 32, which will be described in detail later, are created and given to the mixing circuit 32.

The comparison processing and decoding circuit 31 is composed of a comparison processing circuit and a decoding circuit. Details of the comparison processing circuit are shown in FIG. 5, and details of the decoding circuit are shown in FIG. 7.

In FIG. 5, the comparison processing circuit includes two subtraction circuits 33, 3.
Contains 4. One subtraction circuit 33 inputs 263
Subtract the current video signal A from the H delayed signal B.

The result is given to the absolute value circuit 35. Therefore, the absolute value circuit 35 outputs a signal having a level represented by lB-AI. The other subtraction circuit 34 subtracts the 1H delayed signal B from the 263H delayed signal B, and the result is given to the absolute value circuit 36 to be converted into an absolute value, so this circuit 36 outputs a signal representing the level of IB-CI. is output.

The comparison processing circuit further includes seven comparators 37L.

Includes 37M, 37S, 38L, 38M, 38S and 39. Comparators 37L, 37M and 3
Reference levels R, R, and R are applied to the positive input terminal of 7S, respectively. The relationship is R>R>R8. The output signal IB-AI of the absolute value circuit 35 is applied to the negative input terminals of these comparators 37L, 37M and 37S. Therefore, the output B-A l of the absolute value circuit 35
is smaller than the reference level R8, all comparators 37
S, 37M, 37L output DAs'DAM, DAL
becomes H level. This state is called "equivalence." Signal I
When the level of B-AI is between the reference levels R and R, only 8M of the outputs DAs are at the L level, and the other outputs DAM'AL are kept at the H level. This state is called "start". When the level of signal B-AI is between reference levels R and RL, outputs DAs and DAM75 (become L level, and output DAL is H level).
keep level. This state is called "epithysis." Signal IB
- When the level of AI exceeds the reference level Rt, the output DAL "AM" AS of all the comparators 37L, 37M, and 37S becomes L level. This state is called "insertion." The above comparative operations are summarized in a table in FIG. In this table, the H level of the output signal is expressed by 0, and the L level of the output signal is expressed by 1.

Similarly, reference levels R, R, and R are applied to the positive input terminals of comparators 38L, 38M, and 38S, respectively. These comparators 38L, 38M.

The negative input terminal of 311S receives the output signal B of the absolute value circuit 36.
-Cl is inputting. These comparators 38L, 38
M and HS compare the level of the input signal IB-CI with reference levels R, R, and R, respectively, and output signals representing the comparison results. L “CM” C8
Output. This output signal DCL "CM" O8 is also summarized in FIG.

The comparator 39 outputs the absolute value signal I B-A I and B-Cl
It is used to compare the size of.

When IB-AI<IB-CI, a signal T1 at H level (represented by 0) is output, and when the opposite is true, a signal T1 at L level (represented by 1) is output.

The AND circuit 40 connects the output DA8 of the comparator 37S and the comparator 3.
When the outputs Dcs of 8S are both at H level, that is, when the signals I B-A I and I B-Cl are both small (when there is almost no difference between the signals A, B, and C), the H level ( A signal T2 (represented by code 0) is output.

Output signal DAL ``AM ``As'' 1, T2°DCL representing the above-mentioned comparison result of the comparison processing circuit (FIG. 5)
"CM" C8 is given as an input signal to the decoding circuit shown in FIG. This decoding circuit uses switching control signals 51 (1 bit)), S2 (MSB and LS
Consisting of 2 bits of B), 53 (1 bit), and S
4 (consisting of 2 bits, MSB and LSB), and as shown in FIG.
a.

41b, 41c, OR circuit 42a, 42b, 4
2c, 42d.

42e, NAND circuit 43. NOT circuits 44a, 44
b.

It is constituted by a combination of AND circuits 45a, 45b and changeover switch 4B. The changeover switch 46 is O.
Switching is controlled by the output (0 or 1) of the R circuit 42d as indicated by 0 and 1 adjacent to the switch 4B. Further, although the switch 4B is shown as a contact point, it goes without saying that it is constituted by a semiconductor element or the like. These matters also apply to other changeover switches described later.

The operation of this decoding circuit, ie, the relationship between its input signals and output signals, is shown in the form of a table in FIG. Also in Figure 8. The output mixed signal of the mixing circuit 32 whose mixing ratio is controlled by signals 81 to S4 (interpolation filter circuit 1
3 output adaptive interpolation signal) is also shown. Here, the mixed signal expressed in fractional form is the input signal A in the mixing circuit 32.

It represents a mixed state of B and C. For example (A10)
/2 represents the arithmetic average of input signals A and C.

In Fig. 8, the difference between signals A and B and signals B and C (IB-
A1. IB-CI) decreases toward the top and increases toward the bottom. For example, the top D -0
The Dcs-0 column represents the case where the difference signals 5B-AI and IB-CI are extremely small (equivalent), and in this case, the arithmetic average signal (AIC) of the current video signal A and the 1H delayed signal color. )/2 is output as an adaptive interpolation signal (line interpolation). Furthermore, in the case of D -0 and Dcs-1^S, there is almost no difference between signals A and B (equal) and there is a slight difference between signals B and C (young), and this is a state. In this case, the current video signal A is output as an interpolation signal. Further, in the case of DAs""DO8"0, the signal is output as a 1H delayed signal color interpolation signal.

When the difference between signals A and B or between signals B and C becomes large, signal B from the previous field is used in addition to signals A and C from the current field to create an interpolation signal (field interpolation). . The mixing ratio of signals A, B, and C is determined by the magnitude of the difference between these signals. In extreme cases, that is, when the difference is extremely large (D p, L""
1 (DCL-1), the 263H delayed signal B is output as an interpolation signal.

If the difference between signals A and B and the difference between signals B and C become large, flickering is likely to occur in the image when interpolated signals are created by simple line interpolation. Since this interpolation filter circuit 13 uses the 263H delayed signal B to create an interpolation signal as described above, flickering can be prevented from occurring. In particular, since this interpolation filter circuit mixes the signal B of the previous field, it is suitable for creating an interpolation signal for an image with no or little movement.

A specific example of the mixing circuit 32 that achieves the above-mentioned mixing process is shown in the ninth example.
As shown in the figure.

The mixing circuit in FIG. 9 is a first-stage mixing circuit that mixes input signals A and C (including when the mixing ratio is 1:0), and
．． This mixing result is further mixed with signal B (mixing ratio is 1
:0) second-stage mixing circuit.

The first stage mixing circuit converts the input signals A and C into a control signal S2.
11! Mix under II (mixing output is α1)
Arithmetic average α2 of coefficient switching circuit 51 and two human input signals A and B
- Addition circuit 52 that takes (AIC)/2, and a changeover switch that selects either one of the outputs α and α of these circuits 51 and 52 according to the control signal S1 (the selected output is α) It consists of 53.

A specific example of the configuration of the coefficient switching circuit 51 is shown in FIG. The mixing ratio of C and the output signal α1,2.α) are shown in FIG. 1(a).

The configuration and operation of the coefficient switching circuit 51 are clear from FIGS. 10 and 11(a), but will be briefly explained. This circuit is A/4, 3A/4. It includes a circuit that creates C/4°3C/4, a changeover switch that changes these signals including inputs A and C, and an addition circuit that adds the switching results.

1/2 coefficient unit 81a, 1/4 coefficient unit 82a, and addition circuit 6
3a creates a signal representing 3A/4. Either A or 3A/4 is selected by the changeover switch 64a. The selector switch 85g selects either the signal representing A/4, which is the output of the 1/4 coefficient multiplier 82a, or the signal representing 0. These changeover switches 8
4a and 85a are controlled by the LSB of control signal S2. Either one of the outputs of the changeover switches 64a and 85a is selected by the changeover switch 86a. This changeover switch 68a is controlled by the MSB of the control signal S2.

1/2 coefficient unit Blb, 1/4 coefficient unit 62b, and addition circuit 8
3b creates a signal representing 3C/4. Either C or 3C/4 is selected by changeover switch $4b. The changeover switch 85b selects either the signal representing C/4, which is the output of the 1/4 coefficient multiplier 82b, or the signal representing 0. These changeover switches 6
4b and θ5b are controlled by the LSB of the control signal S2 which is inverted by the NOT circuit 86b. Either one of the outputs of the selector switch 64b and B5b is the selector switch 8.
8b. This changeover switch 66b is set to MS inverted by the NOT circuit 88a of the control signal S2.
Controlled by B.

The output signals of the changeover switches 66a and 66b are sent to the adder circuit 67.
are added to form the output signal α1.

The second-stage mixing circuit includes a coefficient switching circuit 54 that mixes the output α of the first-stage mixing circuit and the input signal B under the control of the control signal S4 (the mixed output is set to β1), and an addition circuit 55 that takes the arithmetic mean β2−(α+B)/2 with B;
Control signal S
3 and a changeover switch 56 that selects according to 2. The output signal of the changeover switch 56 becomes an adaptive interpolation signal.

The specific configuration example of the coefficient switching circuit 54 is the same as that shown in FIG. The same applies. Further, the operation of the second stage mixing circuit including the operation of this coefficient switching circuit 54 is shown in FIG. 11(b).

Nonlinear processing circuits 7 and 17 can have the same configuration, and specific configuration examples thereof are shown in FIGS. 12 and 1.
This will be explained with reference to FIG. Figure 12 shows the nonlinear processing circuit 7.
．． 17 is a circuit diagram showing an example of the circuit. FIG. 13 is a graph showing the relationship between the input difference signal and the output signals of the nonlinear processing circuits 7 and 17.

As is clear from FIG. 13, the nonlinear processing circuit shown in FIG. 12 maintains the value of the input X until the input Output 2 (hereinafter nonlinear processing circuit 7 or 17)
Let Z be the signal output from ) is kept at zero. input
From a predetermined value to 2D, the level of input X and the level of output Z are in a proportional relationship. Further, when the input X becomes 2D or more, the output Z is kept at a constant value DS up to 3D. When the input X exceeds 3D, the output Z decreases linearly with a constant slope, and when the input X exceeds 4D, the output Z is kept at zero. In this way, this nonlinear processing circuit.

It is configured to generate an output Z whose level changes in a trapezoidal manner as the level of human power X increases.

In addition to the component representing the vertical contour, the input difference signal X includes a noise component and a component representing image motion. It is considered that there are many noise components in the portion where the level of the input difference signal X is low. It is also considered that the level of the input difference signal X increases as the component representing motion increases. In the nonlinear processing circuit shown in Fig. 12, the output signal Z is kept at zero when the level of human power By keeping the output signal Z at zero, one edge is not emphasized. This is an ideal nonlinear processing circuit for contour compensation that emphasizes contours according to the level of the input signal when the level of the input X is in the range of D to 4D.

Referring to FIG. 12, difference signal X input to nonlinear processing circuit 7 or 17 is absolute value circuit 71. It is applied to the sign discrimination circuit 72 and the coefficient unit 73a in the first coefficient unit group 73. The absolute value circuit 7I converts the input difference signal X into an absolute value, and its output signal is applied to one input terminal of four comparators 78a to 78d in a comparator group 78, which will be described later. The sign discrimination circuit 72 discriminates whether the input difference signal is positive or negative, and the discrimination signal is given as a switching control signal to a switching circuit 77, which will be described later.

The first coefficient unit group 73 includes two coefficient units 73a.

73b is included. These coefficient units 73a, 73
Both signals b are for multiplying the human input signal by a coefficient S and outputting the result. One coefficient multiplier 73a multiplies the input difference signal by a coefficient of 8 and outputs Z
, -SX are applied to subtracters 80 and 81.

In this embodiment, it is possible to switch the degree of edge enhancement into two levels, and for this purpose, a threshold generation circuit 74 is provided that generates two types of thresholds: D, D, and 2.
is provided. These threshold values D1 and D2 are applied to two input terminals of the switching circuit 75, respectively. The switching circuit 75 is supplied with an external threshold selection signal specifying the degree of edge enhancement, and the threshold D1 or D2 is selected in accordance with this selection signal. The signal representing the selected threshold value D (the two types of threshold values D1 and D2 are collectively expressed as D) output from the switching circuit 75 is as follows.

Five coefficient units 76a, 7[i
b, 76c, 7Bd, 78e and comparator 78
is applied to the other input terminal of a. Second coefficient unit group 7B
The coefficient multiplier 78a multiplies the input threshold value by 1, and the coefficient multiplier 78b multiplies the manually input threshold value by -1, and outputs a signal representing them. Coefficient unit 76a,
The output signal of 78b is applied to two input terminals of switching circuit 77, respectively.

The switching circuit 77 performs switching based on the discrimination signal from the code discrimination circuit 72. That is, the switching circuit 77 selects the threshold value inputted from the coefficient multiplier 76a if the input difference signal X discriminated by the sign discrimination circuit 72 is positive, and selects the threshold value -D given from the coefficient multiplier 78b if it is negative. do.

The threshold value or 10 selected by the switching circuit 77 is applied to the coefficient multiplier 73b in the first coefficient multiplier group 73, and
The signal is multiplied and given to the switching circuit 79 as -Z2-DS (D includes a negative value), and also given to the coefficient multiplier 76f.

The coefficient multipliers 78c, 7[id, and 78e each double the signal representing the threshold value given from the switching circuit 75.

Multiply by 3 and 4, comparators 78b, 78c, 71
respectively to the other input terminal of fd. Further, the coefficient multiplier 78f multiplies the signal representing Z2-DS outputted from the coefficient multiplier 73b by four and outputs the signal representing 4DS to the subtracter 81.
give to

In the subtracter 81, 4DS-3X is calculated.

A signal Z3 representing the result of this calculation is input to the switching circuit 79. Further, a signal representing Z2-Ds outputted from the coefficient unit 73b has been input to the subtracter 8o, Z-5X-DS is calculated by the subtracter 80, and a signal Z1 representing the result of this calculation is sent to the switching circuit. 79.

On the other hand, in the comparators 78a to 78d in the comparator group 78.

The absolute value input difference signal X and these comparators 78a~
The reference value (threshold value) given to 78d.

2D, 3D, and 4D), and a signal representing the results of these comparisons is input to the switching circuit 79 as a switching control signal. In response to this switching control signal, the switching circuit 79 changes the level of the input difference signal X.

If it is below the threshold, the grounded Z4 terminal becomes 0.
Outputs a level signal, and when D<X≦2D, Zl-
Outputs SX-DS, and outputs signal Z when 2D<X≦3D.
2-DS, and if 3Dx≦4D, signal z3
~4DS-8X is output, and when X exceeds 4D, it is switched to output a 0 level signal from the grounded Z4 terminal. Further, a signal for turning on and off the contour compensation circuit is given to the switching circuit 79, and when the on signal is given, the comparator circuit 79 performs the above operation according to the output of the comparator group 78, but when the off signal is given,
It is switched to the grounded Z4 terminal, and the output Z becomes 0.

Effects of the Invention According to the present invention, as described above, the current video signal, the 1H delayed signal of the same field, and the 2H delay signal of the previous field.
An adaptive interpolation signal is created by using the 63H delayed signal and changing the mixing ratio of these three types of signals according to the level difference between these signals. Especially the front field 2
Since the 63H delayed signal is used, it is possible to prevent the occurrence of flickering that tends to occur when the difference between the signals is large. The adaptive interpolation signal according to the present invention is particularly effective in improving the image quality of still images without movement or images with little movement.

Further, according to the present invention, vertical contour enhancement processing is performed on the above-mentioned adaptive interpolation signal. That is, the level of the interfield difference signal of the interpolated signal is detected.

Nonlinear processing is performed on this inter-field difference signal according to the detected level. By adding the non-linearly processed inter-field difference signal to the adaptive interpolation signal, an adaptive interpolation signal with vertical contour compensation is finally obtained. In this manner, according to the present invention, an adaptive interpolation signal with proper vertical contour compensation for progressive scanning can be generated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing the relationship between the current video signal, the 262H delay signal, and the 263H delay signal, and FIG. 3 is a diagram showing the relationship between the current video signal, the 1H delay signal, and the 263H delay signal. FIG. 4 is a block diagram showing the schematic configuration of the interpolation filter circuit, FIG. 5 is a circuit diagram showing the configuration of the comparison processing circuit, FIG. 6 is a diagram showing the comparison operation collectively, and FIG. 7 is the configuration of the decoding circuit. A circuit diagram showing. FIG. 8 is a diagram showing the decoding operation and mixing output together, and FIG. 9 is a block diagram showing the configuration of the mixing circuit.
The figure is a circuit diagram showing the configuration of the coefficient switching circuit.
) and (b) are diagrams collectively showing the operation of the mixing circuit. FIG. 12 is a circuit diagram showing an example of a nonlinear processing circuit. FIG. 13 is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. 1...262H delay circuit. 2.10...1H delay circuit. 3. s, ti, ts...addition circuit. 4, I2... 1/2 coefficient unit. 5゜15...Subtraction circuit. 7.17...Nonlinear processing circuit. 13...Interpolation filter circuit. 31... Comparison processing and decoding circuit. 32...Mixing circuit.

Claims (4)

[Claims] (1) A first delay circuit that delays the input current video signal by 1H, a second delay circuit that delays the input current video signal by 263H, the input current video signal, and the 1H output from the first delay circuit. The adaptive interpolation signal is generated by inputting the delayed signal and the 263H delayed signal output from the second delay circuit, and mixing these three input signals according to the comparison result of the levels of these three input signals. An interpolation filter circuit that creates and outputs an interfield difference signal, an interfield difference signal creation circuit that creates and outputs an interfield difference signal of the interpolation signal, and an interfield difference signal creation circuit that creates and outputs an interfield difference signal of the interpolation signal. A nonlinear processing circuit performs predetermined nonlinear processing for vertical contour compensation according to the level of the difference signal, and vertical contour compensation is performed by adding the output signal of the nonlinear processing circuit to the adaptive interpolation signal. A vertical contour compensation circuit for interpolated signals, comprising: an adder circuit that outputs an interpolated signal; (2) The interpolation filter circuit detects the level difference between the current video signal and the 263H delayed signal and the level difference between the 263H delayed signal and the 1H delayed signal, and the output signal of the comparison processing circuit. is controlled by a decoding circuit that converts the signal into a mixing control signal, and a mixing control signal given from the decoding circuit, and mixes the current video signal, the 263H delayed signal, and the 1H delayed signal at a predetermined ratio according to the level difference. 2. The vertical contour compensation circuit for interpolation signals according to claim 1, further comprising: a mixing circuit for creating and outputting an adaptive interpolation signal. (3) A line interpolation circuit in which the inter-field difference signal creation circuit creates and outputs a line interpolation signal that is an average signal of the current video signal and the video signal 1H before the current video signal, which corresponds to the line interpolation signal. A 1-field delay circuit that outputs the previous field video signal to the horizontal scanning line, and an inter-field difference signal representing the difference between the line interpolation signal and the previous field video signal output from the 1-field delay circuit is calculated and output. The vertical contour compensation circuit for an interpolated signal according to claim 1, further comprising a subtraction circuit that performs the following steps. (4) The nonlinear processing circuit for vertical contour compensation includes a first circuit that creates a first signal having a level proportional to the level of the interfield difference signal, and a first circuit that generates a first signal having a level proportional to the level of the interfield difference signal; a second circuit that creates a second signal with a constant level; a third circuit that creates a third signal whose level decreases as the level of the inter-field difference signal increases; The first and second signal levels are different.
, a comparison circuit that compares the signal with a third and fourth reference level and outputs a signal representing a comparison result; and a level of the inter-field difference signal is lower than or equal to a first reference level according to the output signal of the comparison circuit. When the signal is at zero level, when the signal is between the first reference level and the second reference level, the first signal is used, and when the signal is between the second reference level and the third reference level, the signal is at zero level. 2nd above
When the signal is between the third reference level and the fourth reference level, the third signal is selected, and when the signal is above the fourth reference level, the zero level signal is selected and output. The vertical contour compensation circuit for interpolation signals according to claim 1, comprising: a switching circuit;