JPH0361951B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a biological signal display device that stores images in a digital memory, reads out the stored images, and displays them on a television, and is particularly used in an ultrasound diagnostic device equipped with a digital television monitor. The present invention relates to a biological signal display device that displays biological signals and the like together with ultrasound images and the like.

Conventionally, electrostatic or electromagnetic deflection type X/Y has been used to visualize biological signals, but in recent years, devices have been proposed that can display ultrasound tomographic images and biological signals together using a digital television monitor. To explain in more detail, for example, a digital television monitor as shown in FIG.
(for example, cardiac waves), in order to obtain data in units of 1 pixel corresponding to 1 square divided in the horizontal and vertical directions of the screen, a cycle with a width of 1 pixel is used, as shown in Figure 3. The biological signals A and B are sampled at T. The data obtained is temporarily stored in a digital memory, etc., and read out in synchronization with the scanning of the television to create a tomographic US image, as shown in Figure 4.
I am trying to display it together with something like this, but it ends up being displayed as a dot. For this reason, a method of connecting and displaying sampled data as shown in Figure 5 (○ marks are sample data) can be considered, but in this case the sampling clock is limited to one pixel wide. Figure 6 (○
As shown in (marked is sample data), when the biological signal becomes high frequency, sufficient data cannot be obtained.
There was a problem with not being able to display accurate waveforms.

SUMMARY OF THE INVENTION An object of the present invention is to provide a biological signal display device for use in ultrasonic diagnostic equipment, etc., which eliminates the drawbacks of the prior art and is capable of depicting good biological signals.

In order to achieve such an objective, the present invention
Basically, there is an analog-to-digital converter that samples biological signals consisting of analog output at a cycle shorter than the display pixel width and converts them into digital signals, and a section for each pixel width from the output of the analog-to-digital converter. a maximum value/minimum value measuring circuit that sequentially calculates the maximum value/minimum value, respectively, and a maximum value/minimum value measuring circuit that sequentially calculates the maximum value/minimum value, and the maximum value and minimum value that are output from the maximum value/minimum value measuring circuit for each section corresponding to the pixel width; and an embedded circuit that displays all pixels corresponding to values between those values, and the maximum value/minimum value measuring circuit measures the maximum value and minimum value of the section to be measured. , the maximum value and the minimum value in the previous section that have been measured are regarded as the minimum value and maximum value, respectively, and the initial value is determined as a reference.

In the biosignal display device configured as described above, first, biosignals consisting of analog outputs are sampled at a cycle shorter than the display pixel width using an analog-to-digital converter, and each sample is converted into a digital signal.

Then, from this digital signal, the maximum value and minimum value are sequentially determined for each section corresponding to each pixel width by a maximum value/minimum value measuring circuit.

Thereafter, an embedding circuit measures a value that includes the maximum value and minimum value that are output from the maximum value/minimum value measurement circuit for each section corresponding to the pixel width, and that corresponds to a value between these values. All pixels are displayed.

In this way, data for each pixel width can be displayed not in a dot-like manner but in a bar-like manner, without being separated from the data on the adjacent pixel side.

However, when the sampling period for converting biological signals into digital signals is reduced,
There may be cases where the data is not necessarily connected to the data on the adjacent pixel side, but is separated by a large distance.

Therefore, the maximum value/minimum value measuring circuit converts the maximum value and minimum value of the section to be measured into the maximum value and minimum value, respectively, of the previous section that has been measured. The configuration is such that the calculation is performed based on the assumed initial value.

In this way, even if the sampling period is small, either the maximum or minimum value of the measurement target section will be the same as the maximum or minimum value of the previous measurement period. .

Therefore, the bar-shaped display for each pixel width can be displayed in a state where the end thereof is completely connected to the end of the bar-shaped display on the adjacent pixel side without being separated.

FIGS. 7 to 14 are diagrams for explaining the principle of the present invention in more detail, and the .marks indicate the maximum values, and the .largecircle. marks indicate the minimum values.

As shown in FIG. 7, the principle of the present invention is to sample biological signals at intervals t shorter than the period T of the pixel width, and to obtain the maximum value [Fmax(t)] in each pixel.
and find the minimum value [Fmin(t)]. Then, when displaying on the screen, each pixel is connected by embedding the space between the determined maximum value and minimum value in synchronization with the period T of the pixel width. A display image obtained by this method is shown in FIG.

As can be seen from FIG. 8, in the above method, it is possible to draw in pixel units in the horizontal direction, and in the vertical direction, it is possible to draw an area in which the area between the maximum value and the minimum value is embedded, so that the conventional problems can be solved to some extent.

However, as shown in Figure 7, the maximum or minimum value of the pixel is separated from the minimum or maximum value of the next pixel at the boundary between pixels, and as shown in Figure 8, It may be discontinuous. In order to solve this problem, as shown in Figure 9, the maximum and minimum values found in each pixel are exchanged, and these values are used as the initial values for calculating the maximum and minimum values in the next pixel. Find the maximum and minimum values in that pixel. That is, find the maximum and minimum values of the first pixel, swap the maximum and minimum values in this pixel, use them as the initial values of the next second pixel, and calculate the maximum and minimum values in this second pixel. seek. Similarly, the maximum and minimum values in the second pixel are exchanged to find the maximum and minimum values in the next third pixel. This operation is repeated for the 4th, 5th, etc., and the maximum and minimum values in each pixel are sequentially determined, and as in the case of Fig. 7, the space between the maximum and minimum values in each pixel is filled in, and each pixel is Connect between. The display image obtained by this method is a continuous analog signal-like image, as shown in FIG. To make the principle of this method easier to understand, we will explain it with an example.

(1) In the case of an upward-sloping waveform As shown in Figure 11, the maximum value a _o1 found in the first pixel is set as the initial sampling value in the second pixel, and the minimum value b ₀ is set as the minimum value b Let _o1 be the maximum value a ₀ .

If we continue sampling the second pixel with this minimum value b ₀ and maximum value a ₀ as initial values, the minimum value b ₀
is held, and the maximum value a ₀ changes to a ₁ , a ₂ , a ₃ . . . a _o , and finally the maximum value a _o2 in the second pixel is determined. That is, the maximum value a _o1 in the first pixel
and the second minimum value b ₀ match, so there is no gap between pixels.

Similarly, the maximum and minimum values of each pixel are determined based on the relationship between the second and third pixels, the third and fourth pixels, and so on.

(2) Case of rising to the right In the same way as in Figure 11, as shown in Figure 12, the maximum value a _o1 in the first pixel is the minimum value of the initial sampling value in the second pixel. b ₀ , and the minimum value b _o1 in the first pixel becomes the initial maximum value a ₀ . Then, the maximum value a ₀ becomes the maximum value a _o2 in the second pixel and is held, and the minimum value b ₀ changes to b ₁ , b ₂ , b ₃ ... _bo , and finally becomes 2
It becomes the minimum value b _o2 in the th pixel. That is, the minimum value b _o1 of the first pixel and the maximum value of the second pixel
Since a _o2 (=a ₀ ) match, there is no gap between pixels. Similarly, the second and third pixels, 3
The maximum value and minimum value in each pixel are determined based on the relationship between the th pixel, the fourth pixel, and so on.

(3) When the value decreases in the middle In the same way as in cases (1) and (2) above, as shown in Figure 13, the minimum value b _o1 and maximum value a _o1 in the first pixel are the same as in the second pixel. The initial values in the pixel are held as the maximum value a ₀ and minimum value b ₀ , but if a point smaller than the minimum value b ₀ is found, the minimum value b ₁ ,
b ₂ , b ₃ ...b _o and finally the minimum value b _o2
is obtained, and the maximum value a _o2 is obtained in the same manner as in the upward-sloping case in (1) above.

(4) When it rises midway In the same way as in the case (3) above, as shown in Figure 14, the maximum value a _o1 and minimum value b _o1 in the first pixel are the initial values in the second pixel. is maintained as the maximum value a ₀ and minimum value b ₀ , but the maximum value a ₀
Find a point that is larger than the maximum value a ₁ , a ₂ , a ₃
...a _o , and finally the maximum value a _o2 is found, and the minimum value b _o2 is found in the same way as in the case of upward slope in (2) above.

Next, embodiments based on the principle of the present invention will be described.

FIGS. 15 to 19 are block diagrams showing the configuration of an embodiment of the present invention.

In the figure, 1 is a biological signal receiving circuit such as an electrocardiograph, and 2 is an analog-to-digital converter (hereinafter referred to as an A/D converter), which converts biological signals into a high-frequency (sampling interval t) A/D conversion clock. It samples and converts it into a digital signal. 3 is the first
This is a sampling clock generation circuit, which generates an A/D conversion clock for sampling of the A/D converter 2. 4 is a maximum value measuring circuit;
As shown in FIG. 6, it is composed of a maximum value judgment comparator 4A, a gate circuit 4B, and a maximum value measurement latch circuit 4C. 5 is a minimum value measuring circuit, which includes a minimum value judgment comparator 5A, as shown in FIG.
It is composed of a gate circuit 5B and a latch circuit 5C. 6 is a maximum value storage section, which, as shown in FIG. 18, includes a write latch circuit 6A, a read latch circuit 6B, a memory device 6C, a write signal generation circuit 6D, a write address generation circuit 6E, and a read address generation circuit 6F. , a read signal generation circuit 6G. 7 is a minimum value storage section, and the first
As shown in FIG. 9, a write latch circuit 7A, a read latch circuit 7B, a memory device 7C, a write signal generation circuit 7D, and a write address generation circuit 7.
E, a read address generation circuit 7F, and a read signal generation circuit 7G. Reference numeral 8 designates a second sampling clock generation circuit for creating timing for writing into the storage units 6 and 7, and reference numeral 9 represents a television synchronization signal generation circuit. 10 is an embedded circuit that embeds between the maximum value and the minimum value, and a Y-axis address generator 10
A, comparators 10B and 10C, and an AND gate circuit 10D. 11 is a display device.

Next, the operation of this embodiment will be explained with reference to FIGS. 15 to 19.

The biological signal received by the biological signal receiving circuit 1 is A/
Input to D converter 2. The A/D converter 2 is a first
A biological signal is sampled by an A/D conversion clock with a sampling interval t from the sampling clock generation circuit 3 and converted into a digital signal. This sample digital signal is transmitted to the maximum value judgment comparator 4A of the maximum value measurement circuit 4 and the maximum value measurement latch circuit 4.
The output of the maximum value measurement latch circuit 4C is compared with the sample digital signal, and when the output of the maximum value measurement latch circuit 4C is smaller, the output of the maximum value judgment comparator 4A is input to the gate circuit 4B. is opened, and a new sampled digital signal is stored as the maximum value in the maximum value measurement latch circuit 4C using the sampling clock t. Minimum value measurement circuit 5
Similarly, the sample digital signal is input to
When the output of the minimum value measurement latch circuit 5C is larger than the sample digital signal input to the minimum value judgment comparator 5A, the sampling clock t sets the sample digital signal as the minimum value and sets the minimum value measurement latch circuit. It is stored in the circuit 5C. The maximum and minimum values of the sample digital signal obtained in this way are determined by the sampling clock T of the pixel width.
The write latch circuits 6A and 7 of the maximum value storage section 6 and minimum value storage section 7 are activated by the TV monitor synchronization signal.
A, stored in storage devices 6C and 7C via write signal generation circuits 6D and 7D. Storage device 6C
The sample digital data stored in
G and 7G are read from the storage devices 6C and 7C, and input to the comparators 10B and 10C of the embedding circuit 10, which fill in the gap between the maximum value and the minimum value, through the read latch circuits 6B and 7B.

Here, as shown in FIG. 20, the comparator 10B
and 10C compares the Y-axis address (vertical direction of the TV) with the maximum value, and when the Y-axis address is smaller than the maximum value, it is output from comparator 10B, and similarly when the Y-axis address is larger than the minimum value. , output from the comparator 10C, AND gate circuit 10D
AND is performed, and the output is input to the display device 11 to embed the area between the maximum value and the minimum value.

Next, FIG. 21 shows a circuit configuration for exchanging the maximum value and minimum value. In FIG. 21, the same parts as in FIG. 15 are given the same reference numerals, and their explanation will be omitted.

In FIG. 21, 12 and 13 are selection circuits, and the selection circuit 12 receives the switching signal S from the second sampling clock generation circuit 8' as shown in FIG.
When is at a low level (L), the minimum value is output to the maximum value measuring circuit 4', and when it is at a high level (H), the output of the A/D converter 2 is output to the maximum value measuring circuit. Also,
The selection circuit 13 outputs the maximum value to the minimum value measuring circuit 5' when the switching signal S is at a low level (L), and outputs the output of the A/D converter 2 to the minimum value measuring circuit when it is at a high level (H). It is now output to .

The maximum value measuring circuit 4' includes a gate circuit 4D for gating the output of the second sampling clock generating circuit 8' in the maximum value measuring circuit 4 shown in FIG.
OR gate the outputs of gate circuits 4B and 4D
An OR gate circuit 4E is provided. Also,
The minimum value measuring circuit 5' is also the same as the minimum value measuring circuit 5 shown in FIG. 15 with a gate circuit 5D and an OR gate circuit 5E, and has the same circuit configuration as the maximum value measuring circuit 4'. It is omitted in Figure 21. The second sampling clock generation circuit 8' outputs the sampling clock T similarly to the second sampling clock generation circuit 8 shown in FIG. A switching signal S as shown is generated.

Next, the operation of this circuit will be explained with reference to FIGS. 21 and 22.

The maximum value and the minimum value are measured in the same manner as in FIG. At the same time, the maximum value is transferred through the selection circuit 13 to the minimum value measurement latch circuit 5C of the minimum value measurement circuit 5'. In the case of the minimum value, in the same way, the minimum value is transferred from the minimum value measurement latch circuit 5C of the minimum value measurement circuit 5' to the writing latch circuit 7A of the minimum value storage section 7, and at the same time, the maximum value is measured through the selection circuit 12. Latch circuit 4 for maximum value measurement of circuit 4'
Transfer the minimum value to C.

In this way, the maximum value storage section 6 and the minimum value storage section 7 store the maximum value and the minimum value, and at the same time,
The maximum value measuring circuit 4' uses the minimum value as an initial value for measuring the maximum value in the next pixel, and the minimum value measuring circuit 5'
The measurement is repeated using the maximum value as the initial value for measuring the minimum value in the next pixel.

Next, when considering the maximum value measuring section 4', the data exchanged and inputted to the maximum value measuring circuit 4' and the minimum value measuring circuit 5' are the sampling clock T output from the sampling clock generating circuit 8'. The gate circuit 4D is opened by the switching signal S, and the maximum value is stored in the latch circuit 4C for measuring the maximum value. The replaced data stored in the maximum value measurement latch circuit 4C is compared with the new sample data, and when the new sample data is larger than the replaced data, the maximum value measurement comparator 4A
When this output is present and it is not switching, the gate circuit 4B is opened and new sample data is stored in the maximum value measurement latch circuit 4C by the sampling clock t.

Here, when there is an output from the maximum value measurement comparator 4A, it is a case of an upward-sloping waveform as shown in Fig. 11, and when there is no output, it is a case of an upward-sloping waveform as shown in Fig. 12. This is the case for waveforms. It can be seen that when there is an output from the maximum value measurement comparator 4A, a new maximum value is obtained, but when there is no output, the previous minimum value is held and becomes the maximum value in this pixel.

It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without changing the gist thereof.

As explained above, according to the present invention, each pixel is connected by finding the maximum and minimum values in a pixel and embedding between them, so that biological signals can be displayed as lines instead of dots. be able to.

Also, when calculating the maximum and minimum values in the pixel, the maximum and minimum values are exchanged, and the maximum and minimum values in this pixel are calculated as the initial values of the next pixel. Continuity can be provided by concatenation, and even biological signals with frequency components in the high range can be displayed accurately like analog signals. As a result, images suitable for diagnosis can be provided.

[Brief explanation of drawings]

Figures 1 to 6 are diagrams for explaining the problems of conventional biological signal display devices that display biological signals together with ultrasound images, and Figures 7 to 14 illustrate the principle of the present invention. 15 to 22 are diagrams for explaining one embodiment of the present invention. 1... Biological signal receiving circuit, 2... A/D converter, 3... First sampling clock generation circuit,
4, 4'... Maximum value measuring circuit, 5, 5'... Minimum value measuring circuit, 6... Maximum value storage section, 7... Minimum value storage section, 8... Second sampling clock generation circuit, 9 . . . Television synchronization signal generation circuit, 10 . . . Circuit embedded between maximum value and minimum value, 11 . . . Display device.

Claims (1)

[Claims] 1. An analog-to-digital converter that samples biological signals consisting of analog output at a cycle shorter than the display pixel width and converts each into digital signals;
A maximum value/minimum value measurement circuit that sequentially calculates maximum and minimum values for each section corresponding to each pixel width from the output of the analog-to-digital converter, and a maximum value and minimum value for each section corresponding to the pixel width. and an embedded circuit that displays all pixels corresponding to values that include the maximum value and the minimum value that are output from the measurement circuit and are between those values, the maximum value/minimum value measurement The circuit calculates the maximum and minimum values of the measurement target section based on the initial values, which are the maximum and minimum values of the previous measurement section, respectively. A biological signal display device comprising: