JPH0362025B2 - - Google Patents
Info
- Publication number
- JPH0362025B2 JPH0362025B2 JP58085330A JP8533083A JPH0362025B2 JP H0362025 B2 JPH0362025 B2 JP H0362025B2 JP 58085330 A JP58085330 A JP 58085330A JP 8533083 A JP8533083 A JP 8533083A JP H0362025 B2 JPH0362025 B2 JP H0362025B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- wiring
- diffusion region
- region
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
Landscapes
- Wire Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置の構造に係り、特にシリコ
ンを含むアルミニウム合金配線の付設方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the structure of a semiconductor device, and particularly to a method for attaching aluminum alloy wiring containing silicon.
(b) 従来技術と問題点
半導体集積回路(IC)等の半導体装置に於て
は、半導体層即ち機能領域に直に接する配線にシ
リコン(Si)を1〜2〔%〕程度含んだアルミニ
ウム(Al)合金配線が多く用いられる。これは
配線が形成された後に行われる表面保護絶縁膜の
化学気相成長、チツプ・ボンデイング、ケース封
止等の工程に於て、該配線が400〜500〔℃〕程度
に昇温せしめられた際、Al配線に接している機
能領域のSiがAl中に溶け込み、該機能領域の持
つ接合が破壊されるのを防止するためである。(b) Prior art and problems In semiconductor devices such as semiconductor integrated circuits (ICs), aluminum (containing about 1 to 2%) of silicon (Si) is used in the semiconductor layer, that is, the wiring directly in contact with the functional area. Al) alloy wiring is often used. This is because the temperature of the wiring is raised to about 400 to 500 degrees Celsius during processes such as chemical vapor deposition of the surface protection insulating film, chip bonding, and case sealing that are performed after the wiring is formed. At this time, this is to prevent Si in the functional area in contact with the Al wiring from dissolving into Al and destroying the bond in the functional area.
しかし上記Siを含むAl合金配線を使用した場
合には、前記のように配線形成後に行われる加熱
工程を経ると、Al配線中に合金成分として含ま
れている常温に於て過剰なSiが、該Al合金配線
に接するSi層即ち機能領域の表面に、Alがドー
プされたp型のSi結晶となつて析出する。 However, when using the above-mentioned Al alloy wiring containing Si, if the heating process is carried out after wiring formation as described above, excessive Si contained as an alloy component in the Al wiring will be removed at room temperature. Al-doped p-type Si crystals are precipitated on the surface of the Si layer, that is, the functional region, in contact with the Al alloy wiring.
そのため特にn型の機能領域から該Al合金配
線が導出される場合には、該Al合金配線に接す
るn型機能領域面に析出した前記p型Si結晶と該
n型機能領域間にp−n接合が形成され該配線の
コンタクト抵抗が増大するという問題がある。 Therefore, especially when the Al alloy wiring is derived from the n-type functional region, there is a p-n There is a problem that a junction is formed and the contact resistance of the wiring increases.
そして第1図に上面図イ及び断面図ロを示した
ように、電極コンタクト窓1内に表出するn型機
能領域2面から該電極コンタクト窓1を介して絶
縁膜3上に導出される前記Al合金配線4に面積
の大きいボンデイング・パツド5が形成される場
合には、電極コンタクト窓1内に表出するn型機
能領域2面に特に該ボンデイング・パツド部から
移動してきた多量のp型Si結晶6が析出し、更に
該半導体ICが高密度高集積化され、電極コンタ
クト窓1が微細化された際には、該コンタクト窓
1内に表出するn型機能領域2の全面をp型Si結
晶6が覆い、該Al合金配線4が該n型機能領域
2に対して非導通の状態になる。(図中、7はp
型Si基板、8はフイールド酸化膜、9は薄い酸化
膜)
(c) 発明の目的
本発明は、配線体にシリコンを含むアルミニウ
ム合金を用いる半導体装置に於て、該配線体中に
含まれるシリコンが、電極コンタクト窓中に表出
する機能領域上に析出するのを抑制する配線の付
設構造を提供するものであり、その目的とすると
ころは上記問題点を除去して半導体装置の性能及
び信頼性を向上せしめるにある。 As shown in the top view A and the cross-sectional view B in FIG. When a bonding pad 5 having a large area is formed on the Al alloy wiring 4, a large amount of p that has moved from the bonding pad portion is deposited on the surface of the n-type functional region 2 exposed in the electrode contact window 1. When the type Si crystal 6 is precipitated and the semiconductor IC is further integrated with high density and the electrode contact window 1 is miniaturized, the entire surface of the n-type functional region 2 exposed within the contact window 1 is Covered with p-type Si crystal 6, the Al alloy wiring 4 becomes non-conductive to the n-type functional region 2. (In the figure, 7 is p
type Si substrate, 8 is a field oxide film, 9 is a thin oxide film) (c) Object of the Invention The present invention provides a semiconductor device using an aluminum alloy containing silicon in a wiring body, However, the present invention provides a wiring attachment structure that suppresses the deposition of metal on the functional area exposed in the electrode contact window, and its purpose is to eliminate the above-mentioned problems and improve the performance and reliability of semiconductor devices. The purpose is to improve sexuality.
(d) 発明の構成
即ち本発明は半導体装置に於いて、n型を有し
素子を構成する第1の拡散領域と、該第1の拡散
領域に隣接し、且つ該第1の拡散領域と分離され
て配設されたn型の第2の拡散領域とを有するp
型の半導体基板と、該半導体基板上に配設され該
第1の拡散領域及び第2の拡散領域面に達する第
1及び第2の開孔を有する絶縁膜と、該第2の開
孔内の該第2の拡散領域上に析出されたn型シリ
コン結晶と、該第1の拡散領域面から該第1の開
孔を介して該絶縁膜上に導出され、該第2の開孔
を介して少なくとも該n型シリコン結晶に接し、
且つ更に該第2の開孔から該絶縁膜上に延在せし
められたシリコンを含むアルミニウム合金配線と
を有してなることを特徴とする。(d) Structure of the Invention In other words, the present invention provides a semiconductor device including a first diffusion region having n-type and constituting an element, and a first diffusion region adjacent to the first diffusion region and connected to the first diffusion region. and an n-type second diffusion region arranged separately.
an insulating film disposed on the semiconductor substrate and having first and second openings reaching the surfaces of the first diffusion region and the second diffusion region; an n-type silicon crystal deposited on the second diffusion region, and an n-type silicon crystal that is led out from the surface of the first diffusion region through the first opening onto the insulating film, and in contact with at least the n-type silicon crystal through the
Moreover, it is characterized in that it further includes an aluminum alloy wiring containing silicon extending from the second opening onto the insulating film.
(e) 発明の実施例
以下本発明を、MOS型半導体装置に於ける一
実施について、第2図に示す要部上面模式図イ及
びそのA−A矢視断面図ロを用いて詳細に説明す
る。(e) Embodiments of the Invention The present invention will be described below in detail regarding one implementation in a MOS type semiconductor device with reference to a schematic top view of the main part shown in FIG. do.
本発明を適用したMOS型半導体装置は、例え
ば第2図イ及びロに示すように、例えばp型シリ
コン(Si)基板11面にフイールド配化膜12及
びその下部のp+型チヤネル・カツト領域13に
よつて個々の画定分離された第1の基板面表出領
域14と第2の基板面表出領域15とが隣接して
設けられており、前記第1の基板面表出領域14
に例えばゲート酸化膜16,多結晶Siゲート電極
17,n+型ソース領域18及びn+型ドレイン領
域19によつて構成されるnチヤネルMOSトラ
ンジスタ(Tr)が、又第2の基板面表出領域1
5にソース、ドレイン領域18,19と等しい例
えば3000〜5000〔Å〕程度の深さを有し、素子を
構成しないn+型ダミー拡散領域20がそれぞれ
形成されている。 A MOS type semiconductor device to which the present invention is applied includes, for example, a field interconnection film 12 on a p-type silicon (Si) substrate 11 and a p + -type channel cut region below it, as shown in FIGS. 2A and 2B. A first substrate surface exposing area 14 and a second substrate surface exposing area 15 are provided adjacent to each other and separated by individual boundaries 13, and the first substrate surface exposing area 14
For example, an n-channel MOS transistor (Tr) composed of a gate oxide film 16, a polycrystalline Si gate electrode 17, an n + type source region 18, and an n + type drain region 19 is also exposed on the second substrate surface. Area 1
5, n + -type dummy diffusion regions 20 are formed, which have a depth equal to that of the source and drain regions 18 and 19, for example, about 3,000 to 5,000 Å, and which do not constitute an element.
そして該基板上に例えばりん珪酸ガラス
(PSG)よりなる絶縁膜21が配設され、該絶縁
膜21に前記ソース領域18,ドレイン領域1
9,ダミー拡散領域20等に達する第1,第2,
第3のコンタクト窓(開孔)22a,22b,2
2cが設けられる。そして該絶縁膜21上に、前
記第1のコンタクト窓22aを介してソース領域
18面から導出された例えばSiを1〔%〕程度含
むAl−Si合金よりなる、ソース配線23a及び
前記第2のコンタクト窓22bを介しドレイン領
域19面から導出され、前記第3のコンタクト窓
22cを介して少なくともシリコン結晶25に接
し、更に該第3のコンタクト窓22c部から絶縁
膜21上に延在し、先端部に例えば100〔μm〕角
程度の広い面積を有するボンデイング・パツド2
4が配設された前記Al−Si合金よりなるドレイ
ン配線23bが形成されてなつている。 An insulating film 21 made of, for example, phosphosilicate glass (PSG) is disposed on the substrate, and the source region 18 and the drain region 1 are covered with the insulating film 21.
9. The first, second, and
Third contact window (opening) 22a, 22b, 2
2c is provided. Then, on the insulating film 21, a source wiring 23a made of, for example, an Al-Si alloy containing about 1% of Si and the second It is led out from the surface of the drain region 19 through the contact window 22b, contacts at least the silicon crystal 25 through the third contact window 22c, further extends from the third contact window 22c onto the insulating film 21, and has a tip. The bonding pad 2 has a large area of, for example, about 100 [μm] square.
A drain wiring 23b made of the Al--Si alloy is formed, and the drain wiring 23b is made of the Al--Si alloy.
即ち該実施例に於ては、n+型ドレイン領域1
9からコンタクト窓22bを介して絶縁膜21上
に導出された先端部に広い面積のボンデイング・
パツド24を有するAl−Si合金ドレイン配線2
3bは、前記ドレイン領域19上のコンタクト窓
22bと前記ボンデイング・パツド24との中間
に於て、コンタクト窓22cを介し素子を構成し
ないn+型ダミー拡散領域20上に形成されたシ
リコン結晶25に接触せしめられている。 That is, in this embodiment, the n + type drain region 1
A large area of bonding is provided at the tip of the insulating film 21 from the contact window 22b through the contact window 22b.
Al-Si alloy drain wiring 2 with pad 24
3b is located between the contact window 22b on the drain region 19 and the bonding pad 24, and contacts the silicon crystal 25 formed on the n + type dummy diffusion region 20 that does not constitute a device through the contact window 22c. I am forced into contact with them.
従つて該構造に於ては、該配線形成が終つた後
に、表面保護絶縁膜(例えばカバーPSG膜)の
形成、チツププ・ボンデイング・ケース封止等の
工程に於て該Al−Si合金ドレイン配線が350〜
450〔℃〕程度の熱履歴を経た際、大面積を有する
ボンデイング・パツド部に含まれる多量のSiは主
としてコンタクト窓22c内に表出しているダミ
ー拡散領域20上にp型結晶25となつて析出す
るので、コンタクト窓22bに於てn+型ドレイ
ン領域19上に析出するp型Si結晶25の量は極
くわずかになる。そのため該実施例に於ては、ボ
ンデイング・パツドを有するAl−Si合金ドレイ
ン配線23bのドレイン領域19に対するコンタ
クト抵抗を、ボンデイング・パツド等大面積の領
域を持たない例えばソース配線23aのコンタク
ト抵抗と同等の低い値に形成することができた。 Therefore, in this structure, after the wiring formation is completed, the Al-Si alloy drain wiring is formed in the process of forming a surface protection insulating film (for example, a cover PSG film), chipping, bonding, and sealing the case. is from 350
After undergoing a thermal history of about 450 degrees Celsius, a large amount of Si contained in the large bonding pad portion becomes p-type crystal 25 mainly on the dummy diffusion region 20 exposed in the contact window 22c. Therefore, the amount of p-type Si crystal 25 deposited on n + -type drain region 19 in contact window 22b becomes extremely small. Therefore, in this embodiment, the contact resistance of the Al-Si alloy drain wiring 23b having a bonding pad to the drain region 19 is made equal to the contact resistance of, for example, the source wiring 23a, which does not have a large area such as a bonding pad. could be formed to a low value.
なお上記実施例に於ては、Al−Si合金配線と
シリコン結晶25との接触部(ダミー・コンタク
ト部)を該Al−Si合金配線に於ける機能領域
(ドレイン領域)とのコンタクト部とボンデイン
グ・パツド部の間に1個所設けたが、更に効果を
大ならしめるために、ダミー・コンタクト部を直
列又は並列に2個所以上設けることもある。この
場合、ダミー拡散領域は1領域として形成して共
通に用いても良く、又個々に設けても良い。 In the above embodiment, the contact portion (dummy contact portion) between the Al-Si alloy wiring and the silicon crystal 25 is bonded to the contact portion with the functional region (drain region) of the Al-Si alloy wiring.・Although one dummy contact portion is provided between the pad portions, two or more dummy contact portions may be provided in series or in parallel to further enhance the effect. In this case, the dummy diffusion region may be formed as one region and used in common, or may be provided individually.
又上記ダミー・コンタクト部を設けることは、
ボンデイング・パツドを有する配線に限らず、機
能領域から絶縁膜上に長く延出される配線に対し
ても上記同様の効果を生ずる。 Also, providing the above dummy contact part,
The same effect as described above is produced not only for wirings having bonding pads but also for wirings extending long from a functional area onto an insulating film.
(f) 発明の効果
以上説明したように本発明によれば、半導体装
置の配線材料にシリコンを含むアルミニウム合金
を用いる際、配線形成後に与えられる熱負荷によ
つて配線中を移動してくるシリコンが、該配線と
電気回路的に機能する領域とのコンタクト部に達
するのが抑止されるので、該コンタクト部に析出
するp型シリコン結晶の量は著しく減少し、該シ
リコンを含むアルミニウム配線の該機能領域に対
するコンタクト抵抗は減少する。そしてこのコン
タクト抵抗を減少せしめる効果はn型機能領域に
対して特に顕著である。(f) Effects of the Invention As explained above, according to the present invention, when an aluminum alloy containing silicon is used as the wiring material of a semiconductor device, silicon moves through the wiring due to the heat load applied after the wiring is formed. is prevented from reaching the contact area between the wiring and the area that functions as an electric circuit, so the amount of p-type silicon crystal deposited in the contact area is significantly reduced, and the amount of p-type silicon crystal deposited in the contact area is significantly reduced. Contact resistance to the functional area is reduced. This effect of reducing contact resistance is particularly remarkable for the n-type functional region.
従つて本発明によれば、シリコンを含むアルミ
ニウム合金を配線材料として用いる半導体ICの
性能及び信頼性を向上せしめることができる。 Therefore, according to the present invention, it is possible to improve the performance and reliability of a semiconductor IC using an aluminum alloy containing silicon as a wiring material.
第1図は従来の配線付設構造を示す上面図イ及
び断面図ロで、第2図はMOS型半導体装置に於
ける本発明の一実施例を示す要部上面模式図イ及
びそのA−A矢視断面図ロである。
図に於て、11はp型シリコン基板、12はフ
イールド酸化膜、13はp+型チヤネル・カツト
領域、14は第1の基板面表出領域、15は第2
の基板面表出領域、16はゲート酸化膜、17は
多結晶シリコン・ゲート電極、18はn+型ソー
ス領域、19はn+型ドレイン領域、20はn+型
ダミー拡散領域、21は絶縁膜、22a,22
b,22cはコンタクト窓、23aはアルミニウ
ム−シリコン合金ソース配線、23bはアルミニ
ウム−シリコン合金ドレイン配線、24はボンデ
イング・パツド、25は析出したp型シリコン結
晶を示す。
Fig. 1 is a top view A and a cross-sectional view B showing a conventional wiring installation structure, and Fig. 2 is a schematic top view A and its A-A It is a cross-sectional view B as viewed from the arrow. In the figure, 11 is a p-type silicon substrate, 12 is a field oxide film, 13 is a p + type channel cut region, 14 is a first substrate surface exposed region, and 15 is a second
16 is a gate oxide film, 17 is a polycrystalline silicon gate electrode, 18 is an n + type source region, 19 is an n + type drain region, 20 is an n + type dummy diffusion region, and 21 is an insulation region. membrane, 22a, 22
b, 22c are contact windows, 23a is an aluminum-silicon alloy source wiring, 23b is an aluminum-silicon alloy drain wiring, 24 is a bonding pad, and 25 is a deposited p-type silicon crystal.
Claims (1)
と、該第1の拡散領域に隣接し、且つ該第1の拡
散領域と分離されて配設されたn型の第2の拡散
領域とを有するp型の半導体基板と、該半導体基
板上に配設され該第1の拡散領域及び第2の拡散
領域面に達する第1及び第2の開孔を有する絶縁
膜と、該第2の開孔内の該第2の拡散領域面上に
析出されたn型シリコン結晶と、該第1の拡散領
域面から該第1の開孔を介して該絶縁膜上に導出
され、該第2の開孔を介して少なくとも該n型シ
リコン結晶に接し、且つ更に該第2の開孔から該
絶縁膜上に延在せしめられたシリコンを含むアル
ミニウム合金配線とを有してなることを特徴とす
る半導体装置。1. A first n-type diffusion region constituting an element, and an n-type second diffusion region adjacent to and separated from the first diffusion region. a p-type semiconductor substrate having a p-type semiconductor substrate; an insulating film having first and second openings disposed on the semiconductor substrate and reaching the surfaces of the first diffusion region and the second diffusion region; An n-type silicon crystal deposited on the second diffusion region surface in the opening, and an n-type silicon crystal deposited on the insulating film from the first diffusion region surface through the first opening an aluminum alloy wiring containing silicon, which is in contact with at least the n-type silicon crystal through the second opening, and further extends from the second opening onto the insulating film. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58085330A JPS59210667A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58085330A JPS59210667A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59210667A JPS59210667A (en) | 1984-11-29 |
| JPH0362025B2 true JPH0362025B2 (en) | 1991-09-24 |
Family
ID=13855620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58085330A Granted JPS59210667A (en) | 1983-05-16 | 1983-05-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59210667A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6278878A (en) * | 1985-10-01 | 1987-04-11 | Mitsubishi Electric Corp | Semiconductor device |
| WO1992007380A1 (en) * | 1990-10-15 | 1992-04-30 | Seiko Epson Corporation | Semiconductor device having switching circuit to be switched by light and its fabrication process |
| JP5998169B2 (en) | 2014-03-26 | 2016-09-28 | 株式会社豊田中央研究所 | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4875169A (en) * | 1972-01-12 | 1973-10-09 |
-
1983
- 1983-05-16 JP JP58085330A patent/JPS59210667A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59210667A (en) | 1984-11-29 |
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