JPH0362053B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a level shift circuit using complementary field effect transistors.

Traditionally, complementary field effect transistors (hereinafter referred to as
(simply called a transistor). When _{constructing a level} shift circuit _using It was a circuit consisting of cross-connecting each other's gates and drains. Here, the level shift circuit 2 composed of transistors M ₁ to _{M 4} is connected to the power supply (-V _D ), and the signal output circuit 1 composed of transistors M ₅ and M ₆ is connected to the power supply (-V _D /2). has been done. This is because it is common to connect a battery to the (-V _D /2) power supply terminal and use a voltage doubler circuit to create a (-V _D ) power supply, so the inputs of transistors M ₁ and M ₂ are of course 0
It has only an amplitude of ~(-V _D /2). Therefore, in order for this circuit to operate, as shown in FIG. 2, transistors M ₁ and M ₄ are off and transistors M ₂ and
When M ₃ is on, the inputs of transistors M ₁ and M ₂ change, turning transistor M ₁ on and transistor M ₂ off, which is determined by the on state of transistor M ₁ and the on state of transistor M ₃ . The design must be such that the node potential Vl is pulled up to the ground potential side and the transistor _M4 is turned on from off. This is the threshold voltage and power supply voltage (-V _D /2) of each transistor,
It is possible to design if (−V _D ) is determined, but in recent years, in integrated circuit systems using solar cells, the power supply voltage (−V _D /2), (−V _D ) gradually falls from the ground potential. It is structured so that it can be used.

Figure 3 is a characteristic diagram for explaining the operation of each transistor in an integrated circuit system using extremely high impedance solar cells as described above. Taking the power supply voltage (-V), _the predetermined (-V _D ),
It is shown that a voltage value of (-V _D /2) is reached. Now, if the voltage is gradually lowered from 0, it will be lowered along the straight line (-V _D ) in the same figure, and at t ₁ when the value of the voltage reaches the threshold voltage V _TN of transistors M ₃ and M ₄ . Transistors M ₃ and M ₄ are turned on, and then transistors M ₁ and M ₂ are turned on only at time t ₂ when the voltage value reaches twice the threshold voltage V _TP of transistors M ₁ and M ₂ . Become. Therefore, in this case, the node potential Vl, as shown by the solid line in the figure, once becomes the same potential as the power supply voltage (-V _D ), and then is raised to the ground potential.

At this time, the integrated circuit system often uses a large number of level shift circuits, and since these change simultaneously with the characteristics shown in Figure 3, the current consumption of this integrated circuit system has the peak shown in Figure 4. Becomes a characteristic.

Here, solar cells are generally made of silicon, but their internal impedance is an order of magnitude higher than that of ordinary batteries, especially when the illuminance of light is low.
For example, it can be 500KΩ or more. At this time, when looking at the load characteristics of the power supply in the integrated circuit system, this peak value may intersect with the load straight line R _L of the power supply. In this state, there are stable points at points A and B, and when the voltage is gradually lowered from the ground potential, it stops at point A and cannot reach point B. As a result, if the power supply does not reach a predetermined value and this condition occurs, the integrated circuit system will naturally not operate.

In other words, conventional level shift circuits have the disadvantage that the peak current that occurs when the operation of the level shift circuit is reversed makes it impossible to level shift a predetermined voltage, making it impossible for an integrated circuit system using the circuit to operate. It was hot.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks, thereby making it possible to make the magnitude of the peak current very small or completely zero even when the operation is reversed, and to stably shift the level of a predetermined voltage. The purpose of this invention is to provide a level shift circuit.

[Structure of the invention]

The level shift circuit of the present invention has a source connected to one terminal of a first power supply, and a gate connected to a second voltage having a voltage smaller than the absolute value of the voltage value of the first power supply.
first and second field effect transistors of one conductivity type to which a first input signal from a signal output circuit including a power supply and a second input signal having an opposite phase to the first input signal are input; a third field effect transistor of an opposite conductivity type connected to the drain of the first field effect transistor and having a gate connected to the drain of the second field effect transistor; and a third field effect transistor having a drain connected to the drain of the second field effect transistor. and the output terminal and the gate is connected to the first
a fourth field effect transistor of an opposite conductivity type connected to the drain of the field effect transistor, and a source-drain path between the other terminal of the first power supply and the sources of the third and fourth field effect transistors. and a fifth field effect transistor of an opposite conductivity type, the gate of which is connected to the second power source.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 shows a circuit diagram of a first embodiment of the present invention. Note that FIG. 5 also shows a signal output circuit to the level shift circuit.

According to FIG. 5, in this embodiment, the first input signal 14 from the signal output circuit 11 whose source is connected to the ground terminal of the power supply (-V _D ) and whose gates each include the power supply (-V _D /2) and this first input signal 1
P-channel type first and second transistors M ₁₁ , M ₁₂ to which a second input signal 15 having a phase opposite to 4 is inputted.
and an N-channel transistor _M13 whose drain is connected to the drain of the transistor _M11 and whose gate is connected to the drain of the transistor _M12 .
The drain is connected to the drain of the transistor M ₁₂ and the gate connected to the output terminal V ₀ is the transistor
N-channel transistor _M14 connected to the drain of _M11 , power supply (-V _D ) and transistor
It is inserted between the drains of _M13 and _M14 and the power supply (-V _D /
2) and a power switch circuit 13 controlled by.

In the voltage control circuit 13, both gates are connected to the power supply (-V _D /2), both sources are connected to the power supply (-V _D ), and drains are connected to the sources of the transistor M ₁₃ and the transistor M ₁₄ , respectively. The signal output circuit 11 consists of N-channel type transistors M ₁₅ and M ₁₆ , whose gates are both connected to the input signal terminal _VI , and whose gates are connected to the power supply (-V _D /2).
It consists of a so-called complementary field effect transistor inverter consisting of a series connection circuit of a P channel type transistor _M18 and an N channel type transistor _M17 inserted between the ground terminal and the ground terminal.

That is, this embodiment is constructed by adding a power switch circuit 13 to the conventional circuit shown in FIG.

Next, the operation of this embodiment will be explained.

As shown in Figure 5, the drive side transistor
Between the drains of M ₁₁ and M ₁₂ and the power supply (−V _D ),
transistors connected in series
There are M ₁₃ and M ₁₅ and transistors M ₁₄ and M ₁₆ , the gate of transistor M ₁₃ is at the connection point of transistor M ₁₂ and transistor M ₁₄ , and the gate of transistor M ₁₄ is at the connection point of transistor M ₁₁ and transistor M ₁₃ . , the gates of transistors M ₁₅ and M ₁₆ are connected to the power supply (-V _D /2). For this reason,
The circuit of transistors M ₁₁ to _{M 16} corresponding to transistors M ₁ to _{M 4} in the conventional example in FIG.
If the threshold voltage of M ₁₅ and M ₁₆ is V _TN , the magnitude of the voltage of the power supply (-V _D /2) is the threshold voltage V _TN
The transistors M ₁₅ and M ₁₆ do not turn on and do not operate until the voltage exceeds the threshold. As a result, if the threshold voltages of the transistors M ₁₃ to _{M 16} are larger in absolute value than the threshold voltages of the transistors M ₁₁ and M ₁₂ , the drive-side transistors M ₁₁ and M ₁₂ are activated first. , no fluctuations in the node potential as shown in FIG. 3 are observed.

Also, the relationship between the threshold voltages and the transistor _M13
In the reverse case where the value of ~M ₁₆ is smaller than the value of transistors M ₁₁ and M ₁₂ , conventionally, the gate of transistor M ₃ is turned on instead of the ground potential, but in this embodiment, transistors M ₁₅ , It can be seen that the peak current is small because only (-V _D /2) is applied to the gate of _M16 . Furthermore, under normal operating conditions, transistors M ₁₅ and M ₁₆ act as resistors, but
Since this circuit is a ratioless circuit, if the switching speed is very fast, it will be affected by the time constant determined by CR, but this will not be a problem in normal use.

As explained above, according to this embodiment, when the negative power supply is gradually lowered from zero, the peak current flowing through the level shift circuit can be suppressed to a very small level, or even completely depending on the combination of the threshold voltages of the transistors. A level shift circuit with no current is obtained.

FIG. 6 shows a circuit diagram of a second embodiment of the invention. This embodiment is based on the transistor of the voltage control circuit 13 in the circuit of the first embodiment shown in FIG.
M ₁₅ and M ₁₆ are combined into one transistor M ₁₉
The operation is the same as that of the first embodiment.

FIG. 7 shows a circuit diagram of a third embodiment of the present invention.

In this embodiment, the power supplies for a plurality of level shift circuits are combined, and the transistors M ₁₅ ,
The transistor _M16 and the transistor _M19 in FIG. 6 are replaced by one transistor _M20 , and its basic operation is the same as in the first and second embodiments.

Although the above description has been made with reference to a P-well type complementary field effect transistor with a negative power source, it goes without saying that the present invention is similarly applicable to an N-well type or a positive power source.

Furthermore, the substrate potentials of transistors M ₁₃ , M ₁₃ ′, M ₁₄ , and M ₁₄ ′ shown in FIGS. 5, 6, and 7 are not connected to any source or power supply. (-V _D ).

〔Effect of the invention〕

As explained above in detail, the level shift circuit of the present invention has a power switch circuit, so even if the power supply voltage is increased from zero, the field effect transistor on the drive side remains unchanged as in the conventional case. Because the field effect transistor on the drive side always turns on first without the field effect transistor on the load side turning on first, the value of the peak current that occurs when the operation is reversed can be minimized or completely reduced. This has the effect of stably shifting the level of a predetermined voltage. Therefore, by using the level shift circuit of the present invention, it is possible to stably operate an integrated circuit system using solar cells.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional level shift circuit, Figure 2 is a partial circuit diagram for explaining its operation, Figures 3 and 4 are operational characteristic diagrams of the circuit in Figure 1, 5, 6, and 7 are the first and second embodiments of the present invention.
FIG. 7 is a circuit diagram showing second and third embodiments. 1... Signal output circuit, 2... Level shift circuit, 11... Signal output circuit, 12... Level shift circuit, 13... Power switch circuit, M ₁ , M ₂ ,
_M5 ...P channel field effect transistor,
M ₃ , M ₄ , M ₅ ... N-channel field effect transistor, M ₁₁ , M ₁₁ ′, M ₁₂ , M ₁₂ ′, M ₁₈ ... P-channel field effect transistor, M ₁₃ , M ₁₃ ′,
M ₁₄ , M ₁₄ ′, M ₁₅ , M ₁₆ , M ₁₇ , M ₁₉ , M ₂₀ ……N
Channel field effect transistor, (−V _D ), (−
V _D /2)...Power supply, V _I ...Input terminal. V ₀ ...Output terminal.

Claims (1)

[Claims] 1 a first input signal from a signal output circuit whose source is connected to one terminal of the first power supply and whose gate includes a second power supply having a voltage smaller than the absolute value of the voltage value of the first power supply; first and second field effect transistors of one conductivity type to which a second input signal having a phase opposite to the input signal is input; a drain is connected to the drain of the first field effect transistor, and a gate is connected to the drain of the second field effect transistor; a third field effect transistor of an opposite conductivity type connected to the drain of the field effect transistor; a third field effect transistor having a drain connected to the drain and the output terminal of the second field effect transistor and having a gate connected to the drain of the first field effect transistor; A fourth field effect transistor of opposite conductivity type is connected, and a source-drain path is connected between the other terminal of the first power source and the sources of the third and fourth field effect transistors, and the gate is connected to the second field effect transistor. and a fifth field effect transistor of an opposite conductivity type connected to a power source.