JPH036693B2 - - Google Patents
Info
- Publication number
- JPH036693B2 JPH036693B2 JP59002982A JP298284A JPH036693B2 JP H036693 B2 JPH036693 B2 JP H036693B2 JP 59002982 A JP59002982 A JP 59002982A JP 298284 A JP298284 A JP 298284A JP H036693 B2 JPH036693 B2 JP H036693B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- channel
- circuit
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
本発明は相補型MIS電界効果型トランジスタ
（以下Ｃ−MISFETと略す。）によつて構成され、
入力電圧変動によるオフセツト電圧の発生を防ぐ
電圧比較回路に関するものである。[Detailed Description of the Invention] The present invention is constituted by a complementary MIS field effect transistor (hereinafter abbreviated as C-MISFET),
This invention relates to a voltage comparison circuit that prevents offset voltage from occurring due to input voltage fluctuations.
従来例としてＣ−MISFETにより構成される
電圧比較回路の一例を第１図ａとｂに示す。第１
図ａはMISFET１〜４により構成される電圧比
較部と、MISFET６と７により構成されるイン
バータ部とに分けられる。入力電圧端子１０に電
圧V1、他の入力端子１１，１２電圧V2を入力す
る。一方の入力電圧V1の値V1(1)、V1(2)、V1(3)に
対して他の一方の入力電圧V2を可変にしたとき、
電圧比較部の出力反転特性を第２図に示す。入力
電圧V1の値がV1(1)→V1(2)→V1(3)と高くなるのに
ともない、出力反転電圧Voutの急峻な部分の電
圧幅は狭まつていく。これにともない次段インバ
ータのしきい値電圧VTHIが最適に設計されている
場合のしきい値電圧VTHIの値をVTHI(1)、入力電圧
V1の値がV1(3)のときにおいてミスマツチをおこ
す場合のしきい値電圧VTHIの値がVTH(2)である。
VTHI(2)の場合、オフセツト電圧がV2＝V1(3)にお
いて急に増加し回路動作不良をおこす。 An example of a conventional voltage comparator circuit constructed of C-MISFETs is shown in FIGS. 1a and 1b. 1st
Figure a is divided into a voltage comparator section made up of MISFETs 1 to 4 and an inverter section made up of MISFETs 6 and 7. A voltage V 1 is input to the input voltage terminal 10, and a voltage V 2 is input to the other input terminals 11 and 12. When one input voltage V 1 is made variable with respect to the other input voltage V 1 (1), V 1 (2), V 1 (3),
FIG. 2 shows the output inversion characteristics of the voltage comparator. As the value of the input voltage V 1 increases from V 1 (1) to V 1 (2) to V 1 (3), the voltage width of the steep portion of the output inversion voltage Vout becomes narrower. Accordingly, the value of the threshold voltage V THI when the threshold voltage V THI of the next stage inverter is optimally designed is V THI (1), the input voltage
The value of the threshold voltage V THI when a mismatch occurs when the value of V 1 is V 1 (3) is V TH (2).
In the case of V THI (2), the offset voltage suddenly increases when V 2 = V 1 (3), causing circuit malfunction.
通常のCMISインバータを増幅段に用いた従来
の回路においては回路の温特、入力電圧によつて
はミスマツチをおこしやすいという欠点があつ
た。なお、第１図ａにおいて電圧比較部はＰチヤ
ネルMISFET１，２とＮチヤネルMISFET３，
４により構成されており、出力インバータ部はＰ
チヤネルMISFET６とＮ形MISFET７により構
成されている。電源端子１３，１４と入力端子１
０，１１、出力端子１２から成つている。第１図
ｂは定電流駆動の電圧比較回路で定電圧回路１５
と定電流制御用MISFET５を供えている。 Conventional circuits that use ordinary CMIS inverters in the amplification stage have the disadvantage that mismatches can easily occur depending on the temperature characteristics of the circuit and the input voltage. In addition, in FIG. 1a, the voltage comparison section includes P channel MISFETs 1 and 2 and N channel MISFETs 3,
4, and the output inverter section is P
It is composed of a channel MISFET 6 and an N-type MISFET 7. Power terminals 13, 14 and input terminal 1
0, 11, and an output terminal 12. Figure 1b shows a voltage comparator circuit driven by a constant current, and the constant voltage circuit 15
and MISFET5 for constant current control.
本発明は上記のような欠点をとり除くために成
されたものであり、設計が容易で且つ入力電圧範
囲が広く、オフセツト電圧の低いＣ−MIG電圧
比較回路を提供するものである。 The present invention has been made to eliminate the above-mentioned drawbacks, and provides a C-MIG voltage comparator circuit that is easy to design, has a wide input voltage range, and has a low offset voltage.
以下、図面を用いて本発明を詳述する。 Hereinafter, the present invention will be explained in detail using the drawings.
第３図の本発明の第１の実施例の回路図を示
す。電圧比較部の出力電圧端子３２が次段増幅部
のＰチヤネルMISFET２５のゲートに接続して
あり、ＮチヤネルMISFET２６のゲートは、第
１の入力端子２９と接続してある。Ｎチヤネル
MISFET２６のゲートが、第１の入力端子２９
と接続されているため、MISトランジスタ２５と
２６とから成る次段インバータの反転のしきい値
電圧は第１の入力電圧にともなつて変動する。 FIG. 3 shows a circuit diagram of the first embodiment of the present invention in FIG. 3; The output voltage terminal 32 of the voltage comparison section is connected to the gate of the P-channel MISFET 25 of the next stage amplification section, and the gate of the N-channel MISFET 26 is connected to the first input terminal 29. N channel
The gate of MISFET 26 is connected to the first input terminal 29
Therefore, the inversion threshold voltage of the next-stage inverter made up of MIS transistors 25 and 26 changes in accordance with the first input voltage.
この様子を第５図と第６図に示す。第５図は、
ＮチヤネルMISFET２６の電流電圧特性ａとＰ
チヤネルMISFET２５の電流電圧特性ｂを示し
ている。第６図はMISFET２１，２２，２３と
２４から成るコンパレータ部の出力反転特性と
MISFET２５と２６から成る後段インバータの
反転動作点VTHI(A)、VTHI(B)、VTHI(C)を示してい
る。MISFET２５のゲートがコンパレータ部の
出力電圧でバイアスされていて、一方Ｐチヤネル
MISFET２６のゲートはコンパレータの入力２
９の電圧でバイアスされており、従つて後段イン
バータの反転の閾値は常にコンパレータ部の反転
特性の最も急峻に変化する電圧に一致し、第６図
のコンパレータの反転特性に示す如く、入力電圧
値V2に対し後段インバータの反転の閾値電圧は
VTHI(A)、VTHI(B)、VTHI(C)のように変化していく。
このようにインバータの反転動作点が入力電圧と
共に変化して、インバータの動作点が最適の動作
点に移動していくことが、本発明の最大の特長で
ある。 This situation is shown in FIGS. 5 and 6. Figure 5 shows
Current-voltage characteristics a and P of N-channel MISFET26
The current-voltage characteristic b of the channel MISFET 25 is shown. Figure 6 shows the output inversion characteristics of the comparator section consisting of MISFETs 21, 22, 23 and 24.
The inverting operating points V THI (A), V THI (B), and V THI (C) of the rear-stage inverter consisting of MISFETs 25 and 26 are shown. The gate of MISFET25 is biased by the output voltage of the comparator section, while the P channel
The gate of MISFET26 is the input 2 of the comparator
Therefore, the inversion threshold of the subsequent inverter always matches the voltage at which the inversion characteristic of the comparator section changes most steeply, and as shown in the inversion characteristic of the comparator in Figure 6, the input voltage value The threshold voltage for inversion of the subsequent inverter with respect to V 2 is
It changes like V THI (A), V THI (B), V THI (C).
The greatest feature of the present invention is that the inverting operating point of the inverter changes with the input voltage in this way, and the operating point of the inverter moves to the optimal operating point.
Ｐ形MISFET２５は電圧比較部３２の出力電
圧変動にともなつてオン、オフし、従つて、電圧
比較部３２の出力反転特性の最も急峻な電圧値に
常に次段インバータの閾値電圧がマツチングして
いるのでミスマツチングがなく広い入力電圧値に
わたつてオフセツトの変動がなく、且つオフセツ
ト電圧値の小さい、電圧比較回路として最適の特
性が得られる。第１の実施例では、Ｐチヤネル
MISFET２１，２３，２５とＮチヤネル
MISFET２２，２４，２６から構成されており、
入力電圧端子２９，３０と出力電圧端子３１を有
している。 The P-type MISFET 25 turns on and off as the output voltage of the voltage comparator 32 changes, so that the threshold voltage of the next stage inverter always matches the steepest voltage value of the output inversion characteristic of the voltage comparator 32. Since there is no mismatching, there is no offset variation over a wide range of input voltage values, and the offset voltage value is small, optimum characteristics as a voltage comparison circuit can be obtained. In the first embodiment, the P channel
MISFET21, 23, 25 and N channel
It is composed of MISFET22, 24, and 26,
It has input voltage terminals 29 and 30 and an output voltage terminal 31.
本発明の第２の実施例を第４図に示す。この例
は定電流駆動を施した電圧比較回路であり、定電
圧回路４８と回路に定電流を供給している
MISFET４５を有している。次段インバータの
ＮチヤネルMISFET４６は、Ｐチヤネル
MISFET４５に対しＫ値が1/2のMISFETであ
り、第１の電流他I1と第２の電流値I2と第３の電
流値I3は等しく製造されている。このことは第３
図の実施例においても同様である。また、各電流
値を一定にするためには、これらの電圧比較回路
を構成するＰチヤネルMISFETの閾値電圧はい
ずれも等しく、同様にＮチヤネルMISFETの閾
値電圧も等しく設計されていなければならない。 A second embodiment of the invention is shown in FIG. This example is a voltage comparison circuit that is driven with constant current, and supplies constant current to the constant voltage circuit 48 and the circuit.
It has MISFET45. The N-channel MISFET46 of the next stage inverter is the P-channel
The MISFET has a K value of 1/2 that of MISFET 45, and is manufactured so that the first current value I1 , the second current value I2, and the third current value I3 are equal. This is the third
The same applies to the illustrated embodiment. Furthermore, in order to keep each current value constant, the threshold voltages of the P-channel MISFETs constituting these voltage comparison circuits must be designed to be equal, and similarly, the threshold voltages of the N-channel MISFETs must also be designed to be equal.
更に、第７図に本発明の第３の実施例を示す。 Further, FIG. 7 shows a third embodiment of the present invention.
第１と、第２の例ではＮチヤネルMISFETを
入力電圧で駆動するタイプを示したが第３の例は
ＰチヤネルにMISFETを駆動している。電圧比
較部はＰチヤネルMISFET６０，６２，６４と、
ＮチヤネルMISFET６１，６３から成る。終段
インバータ部はＰチヤネルMISFET６５，６７
とＮチヤネルMISFET６６から成る。また定電
圧をＰチヤネルMISFETに供給する定電圧回路
をＰチヤネルMISFET６９とＮチヤネル
MISFET６８で作つている。その他入力電圧端
子７０，７１と、電源端子７３，７２とから成
る。 In the first and second examples, an N-channel MISFET is driven by an input voltage, but in the third example, a P-channel MISFET is driven. The voltage comparison section includes P channel MISFET60, 62, 64,
Consists of N-channel MISFET61,63. The final stage inverter section is P channel MISFET65,67
and N-channel MISFET66. In addition, the constant voltage circuit that supplies constant voltage to the P channel MISFET is connected to the P channel MISFET69 and the N channel.
It is made with MISFET68. Other components include input voltage terminals 70 and 71 and power supply terminals 73 and 72.
以上詳述したように、本発明のCMIS電圧比較
回路によれば電圧比較部の出力反転特性の最も急
峻な電圧範囲内に常に次段のインバータのしきい
値電圧とマツチングするので入力電圧変動にとも
なうオフセツト電圧の変動がなく且つオフセツト
電圧は低くおさえられ、設計も容易で有用な電圧
比較回路を提供するものである。 As detailed above, according to the CMIS voltage comparator circuit of the present invention, the threshold voltage of the next stage inverter is always matched within the steepest voltage range of the output inversion characteristic of the voltage comparator, so it is not affected by input voltage fluctuations. The present invention provides a voltage comparator circuit which is easy to design and useful, since there is no accompanying fluctuation in offset voltage and the offset voltage is kept low.
第１図ａ及び、第１図ｂは従来の電圧比較回路
の回路図、第２図は従来の電圧比較回路の出力反
転特性を示グラフ、第３図は本発明による電圧比
較回路の第１実施例の回路図、第４図は本発明の
電圧比較回路の第２実施例の回路図、第５図は本
発明の終段インバータの電流電圧特性を示すグラ
フ、第６図は本発明の終段インバータの反転のし
きい値電圧を示すグラフ、第７図は本発明の第３
の実施例を示す回路図である。
２１，２３……電圧比較部Ｐチヤネル
MISFET、２２，２４……電圧比較部Ｎチヤネ
ルMISFET、２５……インバータ部Ｐチヤネル
MISFET、２６……インバータ部Ｎチヤネル
MISFET、２９，３０……入力電圧端子、３１
……出力電圧端子、２７……Voo端子、２８……
Vss端子。
1a and 1b are circuit diagrams of a conventional voltage comparison circuit, FIG. 2 is a graph showing the output inversion characteristics of the conventional voltage comparison circuit, and FIG. 4 is a circuit diagram of the second embodiment of the voltage comparison circuit of the present invention, FIG. 5 is a graph showing the current-voltage characteristics of the final stage inverter of the present invention, and FIG. 6 is the circuit diagram of the second embodiment of the voltage comparison circuit of the present invention. A graph showing the inversion threshold voltage of the final stage inverter, FIG.
FIG. 2 is a circuit diagram showing an embodiment of the present invention. 21, 23...Voltage comparison section P channel
MISFET, 22, 24... Voltage comparison section N channel MISFET, 25... Inverter section P channel
MISFET, 26...Inverter section N channel
MISFET, 29, 30...Input voltage terminal, 31
...Output voltage terminal, 27...Voo terminal, 28...
Vss terminal.
Claims (1)
スタのドレインと第２導電型の第２のMIS電界効
果型トランジスタのドレインとを直列に接続した
回路と、第１導電型の第３のMIS電界効果型トラ
ンジスタのドレインと第２導電型の第４のMIS電
界効果型トランジスタのドレインとを直列に接続
した回路と、第１導電型第５のMIS電界効果型ト
ランジスタのドレインと第２導電型の第６のMIS
電界効果型トランジスタのドレインとを直列に接
続した回路とを電源に対して並列に接続し、前記
第１と第２のMIS電界効果型トランジスタの接続
点と前記第１と第３のMIS電界効果型トランジス
タのゲート電極を接続し、前記第３と第４のMIS
電界効果型トランジスタの接続点と前記第５の電
界効果型トランジスタのゲート電極とを接続し、
前記第２と第６の電界効果型トランジスタのゲー
トとゲートとを接続したことを特徴とする電圧比
較回路。1. A circuit in which the drain of a first MIS field-effect transistor of a first conductivity type and the drain of a second MIS field-effect transistor of a second conductivity type are connected in series, and a third MIS field-effect transistor of a first conductivity type. A circuit in which the drain of a field effect transistor and the drain of a fourth MIS field effect transistor of the second conductivity type are connected in series, and the drain of the fifth MIS field effect transistor of the first conductivity type and the drain of the fourth MIS field effect transistor of the second conductivity type are connected in series. 6th MIS
A circuit in which the drains of the field effect transistors are connected in series is connected in parallel to the power supply, and a connection point between the first and second MIS field effect transistors and the first and third MIS field effect transistors are connected in parallel to the power supply. Connect the gate electrodes of the type transistors and connect the third and fourth MIS
connecting the connection point of the field effect transistor and the gate electrode of the fifth field effect transistor;
A voltage comparison circuit characterized in that the gates of the second and sixth field effect transistors are connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59002982A JPS60146521A (en) | 1984-01-11 | 1984-01-11 | Voltage comparison circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59002982A JPS60146521A (en) | 1984-01-11 | 1984-01-11 | Voltage comparison circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60146521A JPS60146521A (en) | 1985-08-02 |
| JPH036693B2 true JPH036693B2 (en) | 1991-01-30 |
Family
ID=11544576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59002982A Granted JPS60146521A (en) | 1984-01-11 | 1984-01-11 | Voltage comparison circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60146521A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0690238B2 (en) * | 1985-04-10 | 1994-11-14 | ソニー株式会社 | C-MOS oscillator circuit |
| JP2009071653A (en) * | 2007-09-14 | 2009-04-02 | Yamaha Corp | Comparator |
| CN104158517B (en) * | 2014-08-26 | 2016-08-31 | 深圳市华星光电技术有限公司 | Comparator |
-
1984
- 1984-01-11 JP JP59002982A patent/JPS60146521A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60146521A (en) | 1985-08-02 |
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