JPH0362228A - Pseudo instruction generation system for virtual machine system - Google Patents

Abstract

PURPOSE:To attain a simulation process via a virtual machine monitor at the middle point of a privilege instruction by actuating a pseudo instruction production means via the virtual machine monitor despite the occurrence of a virtual machine stop event. CONSTITUTION:When the information recorded by a virtual processor stop state storage means 7 shows the middle point of an instruction, a virtual machine monitor 2 produces a pseudo instruction as if a pseudo instruction production means 12 produces a simulation request to the monitor 2 after a privilege instruction 41 carried out an action up to the middle point of the instruction via a virtual processor, e.g., a virtual processor 4. Then the monitor 2 can carry on the process of the instruction 41 kept on the middle point of a process. Thus, the monitor 2 can continue the process to the instruction 41 which is kept on the middle point of the process carried out by a virtual machine 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a virtual computer system, and particularly to a pseudo instruction generation method in a virtual computer system when a privileged instruction is executed on a virtual computer.

[Conventional technology]

Conventionally, in this type of virtual computer system, when an event that causes a virtual computer to stop (hereinafter referred to as a virtual computer stop event) occurs, the following processing is performed.

First, when some kind of virtual machine stop event occurs in the virtual machine monitor, execution of the virtual machine is stopped, processing for the cause of the stop is performed, and execution of the virtual machine is resumed after the processing for the cause of the stop is completed. At this time, the virtual processor of the virtual machine that has resumed execution starts executing the instruction from when it transitioned to the stopped state.

[Problem to be solved by the invention]

In the conventional virtual machine system described above, privileged instructions on the virtual machine that are processed by the virtual machine monitor are sent to the virtual machine monitor to control execution as a re-execution request at the end of the instruction, that is, at a point where the instruction can be re-executed. was passed, so even for privileged instructions whose operations up to the middle of the instruction can be directly executed by the CPU/FW (Central Processing Unit/Firmware), all operations of that privileged instruction are simulated by the virtual machine monitor. However, this method has the disadvantage of increasing the overhead in terms of processing time for privileged instructions.

In view of the above-mentioned points, an object of the present invention is to perform operations from the middle of a privileged instruction when a virtual processor is stopped in the middle of a privileged instruction that can be directly executed by a CPtJ/FW. An object of the present invention is to provide a method for generating pseudo instructions in a virtual computer system that enables simulation processing using a virtual computer monitor.

[Means to solve the problem]

The pseudo instruction generation method in the virtual computer system of the present invention includes:
A virtual machine stopping means that transitions the virtual machine to a stopped state when some kind of virtual machine stopping event that stops the virtual machine occurs, and a plurality of virtual machines running on the virtual machine that is transitioned to the stopped state by this virtual machine stopping means. A virtual processor stop state storage means for storing the state of a virtual processor, a virtual machine stop event processing means for processing a virtual machine stop event that caused a virtual machine to stop, and a virtual machine stop event caused by the virtual machine stop event processing means. virtual machine execution starting means for restarting the execution of the virtual machine after the processing of a virtual processor stop state determining means for determining the stop state of the virtual processor when the machine is stopped;
a virtual processor start means for restarting the virtual processor when the state of the virtual processor is determined to be at an instruction break by the virtual processor stop state determination means; The state of the CPU executes the operation up to the middle of the instruction.
/If it is determined that the privileged instruction is in the middle of a privileged instruction that can be directly executed by the FW, this privileged instruction will be displayed on the virtual machine monitor on the virtual processor after directly executing the operation up to the middle of the instruction on the CPU/FW. and pseudo-instruction generation means for generating an instruction in a pseudo manner as if a simulation request had been generated.

(Operation) In the pseudo-instruction generation method in the virtual computer system of the present invention, the virtual machine stopping means transitions the virtual machine to a stopped state when some kind of virtual machine stopping event that stops the virtual machine occurs, and stores the virtual processor stopped state. The means stores the states of a plurality of virtual processors running on the virtual machine that has been transitioned to a stopped state by the virtual machine stopping means, and the virtual machine stopping event processing means stores a virtual machine stopping event that caused the stopping of the virtual machine. and the virtual machine execution start means resumes execution of the virtual machine after the virtual machine stop event processing means processes the virtual machine stop event, and the virtual processor stop state determination means causes the virtual machine execution start means to resume execution of the virtual machine. Later, the virtual processor stop state is determined based on the state of the virtual processor stored by the virtual processor stop state storage means when the virtual machine is stopped, and the virtual processor start means determines the state of the virtual processor by the virtual processor stop state determination means. If it is determined that the instruction is at a break, the virtual processor is restarted, and the pseudo-instruction generation means uses the virtual processor stop state determination means to enable the CPU/FW to directly execute operations until the state of the virtual processor reaches the middle of the instruction. If it is determined that the privileged instruction is in the middle of a privileged instruction, the CPU/FW executes the operation as if the privileged instruction was in the middle of the instruction.
After directly executing the command, the command is generated on the virtual processor in a pseudo manner as if a simulation request was issued to the virtual machine monitor.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a virtual computer system to which a pseudo instruction generation method according to an embodiment of the present invention is applied. This virtual computer system is configured to: from a virtual computer stop event 1, a virtual computer monitor 2, and a virtual computer 3;
Its main parts are composed of:

On the virtual machine 3, multiple virtual processors 4...
, 5 are being executed.

The virtual computer monitor 2 monitors the virtual computer a when a virtual computer stop event 1 that causes the virtual computer 3 to stop occurs.
a plurality of virtual processors 4 . ...
, 5, and a virtual machine stop event processing means 8 that processes the virtual machine stop event 1 that caused the virtual calculation 1a3 to stop.
virtual machine execution start means 9 for restarting execution of virtual computation 113 after processing of virtual machine stop event l by virtual machine stop event processing means 8; and virtual processor 4. ...,
Based on the state of virtual processor 4.5 when the virtual machine 3 is stopped, . ..., 5
If it is determined that the state of virtual processor 4 is at an instruction break, virtual processor 4. . ..., if it is determined that state 5 is in the middle of a privileged instruction that can directly execute the operation up to the middle of the instruction by the CPU/FW, this privileged instruction will execute the operation up to the middle of the instruction by the CPU/FW. After direct execution on FW, virtual processor 4. .

FIG. 2 is a diagram showing the operation when the privileged instruction 41 is executed on the virtual processor 4 in the virtual machine 3 and the operation when the privileged instruction 51 is executed on the virtual processor 5. The privileged instruction 41 allows the CPU to execute the operation up to the middle of the instruction.
/This is a privileged instruction that can be directly executed by the FW, and includes instruction analysis processing 42 and operation processing for the instruction (partially executed) 4
3 and a simulation request issuing process 44 to the virtual machine monitor. Further, the privileged instruction 51 is a privileged instruction whose operation up to the middle of the instruction cannot be directly executed by the CPU/FW, and consists of an instruction analysis process 52 and a simulation request issuing process 53 to the virtual machine monitor.

Next, the operation of the pseudo instruction generation method in the virtual computer system of this embodiment configured as described above will be explained.

Some kind of virtual computer stop event 1 for virtual calculation 813
When this occurs, the virtual machine monitor 2 causes the virtual machine stopping means 6 to execute a process of transitioning the virtual machine 3 to a stopped state, thereby stopping all the virtual processors 4 . . . 5 is stopped, and the virtual calculation a3 is transitioned to the stopped state.

Next, the virtual machine monitor 2 uses the virtual processor stop state storage means 7 to store all the virtual processors 4. ..., stores the state immediately before the stop of 5.

Here, for example, the virtual processor 4 operating in the virtual machine 3 is processing a privileged instruction 41 whose operation up to the middle of the instruction can be directly executed by the CPU/FW, and this privileged instruction 4
As the first operation, an instruction analysis process 42 is performed, then an operation process for the instruction (partially executed) 43 is performed, and in a simulation request issuing process 44 to the virtual machine monitor, the process immediately before passing control to the virtual machine monitor 2 is performed. If so, the virtual processor stop state storage means 7 records that the virtual processor 4 of the virtual machine 3 is in the middle of executing an instruction. Note that even if the privileged instruction 41 allows the CPU/FW to directly execute the operation up to the middle of the instruction, the state other than immediately before passing control to the virtual machine monitor 2 in the simulation request issuing process 44 to the virtual machine monitor When it is, the virtual processor stop state storage means 7 stores the virtual calculation!
The virtual processor 4 of 113 records this as an instruction break.

On the other hand, for example, the virtual processor 5 operating in the virtual machine 3 is processing a privileged instruction 51 whose operation up to the middle of the instruction cannot be directly executed by the CPU/FW, and the operation of this privileged instruction 51 is , the instruction analysis process 52 is performed, and the simulation request issuance process 52 to the virtual machine monitor is performed without performing the operation process for the instruction, and control is just about to be transferred to the virtual machine monitor 2. records that the virtual processor 5 of the virtual machine 3 is at an instruction break, that is, the instruction can be re-executed. In addition, the operation up to the middle of the command is
In the case of an instruction other than the privileged instruction 41 that can be directly executed by the PU/FW, in any case, the virtual processor stop state storage means 7 stores the instruction break, the virtual processor 5 of the virtual machine 3, In other words, it is recorded that the instruction can be re-executed.

Next, the virtual machine monitor 2 uses the virtual machine stop event processing means 8 to analyze and process the stop cause for the virtual machine stop event l.

As a result, the virtual needle X machine 3 becomes in a state where it can be executed again.
The virtual computer monitor 2 causes the virtual computer execution start means 9 to transition the virtual needle [13 to an executable state.

Then, the virtual machine monitor 2 uses the information recorded by the virtual processor stop state storage means 7 by the virtual processor stop state determination means 10 to determine whether each virtual processor 4 existing in the virtual machine 3 . ...Determine how to start a virtual processor in units of 5.

Here, if the information recorded by the virtual processor stop state storage means 7 indicates an instruction break, that is, a state in which the instruction can be re-executed, the virtual machine monitor 2 uses the virtual processor start means 11 to detect a virtual processor, for example, a virtual The execution of the processor 5 is started. At this time, the virtual processor 5 that resumes execution starts executing the instruction from which it entered the stopped state.

On the other hand, when the information recorded by the virtual processor stop state storage means 7 is in the middle of an instruction, the virtual machine monitor 2 uses the pseudo instruction generation means 12 to generate a privileged instruction 41 on the virtual processor, for example, the virtual processor 4. generates an instruction in a pseudo manner as if it issued a simulation request to the virtual computer monitor 2 after executing the operation up to the middle of the instruction, and causes the virtual computer monitor 2 to execute the processing for the privileged instruction 41 that is in the middle of processing. This allows continued execution.

As described above, even when the virtual machine stop event 1 occurs, the pseudo instruction generating means 1 is displayed on the virtual machine monitor 2.
By operating 2, it is possible for the virtual machine monitor 2 to continue processing the privileged instruction 41 that is in the middle of an instruction on the virtual machine 3.

〔Effect of the invention〕

As explained above, the present invention provides a privilege that allows the CPLJ/FW to directly execute the operation up to the middle of the instruction by operating the pseudo instruction generation means by the virtual computer monitor even when a virtual machine stop event occurs. It is now possible to restart processing from the middle of the instruction, and as a result, the privileged instructions on the virtual machine that are processed by the virtual machine monitor will be restarted after the processing that was directly executed by the CPU/FW up to the middle of the instruction. This has the effect of reducing the overhead of instruction processing time due to virtual machine monitor simulation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a pseudo-instruction generation method in a virtual computer system according to an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing the operation when a privileged instruction is executed on a virtual processor; and the operation when a privileged instruction is executed on a virtual processor. In the figure, 1...Virtual computer stop event, 2...Virtual computer monitor, 3...Virtual computer, 4.5.Virtual processor, 6...Virtual computer stopping means, 7. - 8.. 9・ ・ 10 ・ l 1 ・ 12 ・ 4 l ・ 42 ・ 43 ・ 44 ・ 52 ・ 53 ・ Virtual processor stop state storage means, virtual machine stop event processing means, virtual machine execution start means, virtual processor stop state determination means, virtual Processor start means, pseudo-instruction generation means, privileged instructions, instruction analysis processing, operation processing for instructions (partial execution), simulation request issuing processing to the virtual machine monitor, privileged instructions, instruction analysis processing, simulation to the virtual machine monitor This is request issuing processing.

Claims (1)

[Scope of Claims] In a virtual machine monitor of a virtual computer system, there is provided a virtual machine stopping means for transitioning the virtual machine to a stopped state when some kind of virtual machine stopping event that causes the virtual machine to stop occurs, and the virtual machine stopping means A virtual processor stop state storage means that stores the states of multiple virtual processors running on a virtual machine that has been transitioned to a stop state, and a virtual machine stop event process that processes a virtual machine stop event that caused the virtual machine to stop. means, a virtual machine execution start means for restarting execution of the virtual machine after the virtual machine stop event processing means has processed the virtual machine stop event, and stopping the virtual processor after the virtual machine execution start means resumes execution of the virtual machine. a virtual processor stop state determination means for determining the stop state of the virtual processor when the virtual machine is stopped based on the state of the virtual processor stored by the state storage means; a virtual processor start means that restarts the virtual processor when it is determined that the virtual processor is at the end of the instruction; and a virtual processor stop state determination means that allows the CPU/FW to directly execute operations up to the middle of the instruction. If it is determined that the privileged instruction is in the middle of a privileged instruction, the operation up to the middle of the instruction is
A virtual computer system characterized by having a pseudo-instruction generation means that pseudo-instructions are generated as if a simulation request was generated to a virtual computer monitor on a virtual processor after being directly executed in a U/FW. Pseudo-instruction generation method.