JPH0362233A - Address match timing tracing mechanism - Google Patents

Abstract

PURPOSE:To improve the debugging efficiency by writing the various information into a trace memory at memory access and updating the address of the trace memory every time the address match is detected by an address match detecting mechanism at memory access. CONSTITUTION:When the address match is detected by an address match detection means 15 at memory access, the various pieces of information stored in a system are written into a trace memory 18. Then the address of a counter means 19 is updated and the next address is designated to the memory 18. Thus the various pieces of information are traced by the memory 18 at each time point of plural address match detecting actions. Thus, the various pieces of information can be traced by the memory 18 with plural address match detecting actions of the past. Then the debugging efficiency is improved with the use of the information on the memory 18.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention provides an address match detection function suitable for efficiently debugging or troubleshooting hardware/software in a computer system. The present invention relates to an address match timing trace mechanism having an address match timing trace mechanism.

(Prior Art) Computer systems are generally equipped with an address matching mechanism to facilitate hardware/software debugging. This address matching mechanism is
It captures access to a specific address on the main memory, that is, detects an address match, and either stops program execution or generates an interrupt. In reality, access to the target address is not limited to one time, so in order to use the address matching mechanism more effectively, it is necessary to generate an interrupt and use the software handler to obtain various information. It is desirable to do so. however,
If an interrupt is involved, before and after address match detection,
It is required to maintain program continuity.

(Problems to be Solved by the Invention) As described above, the conventional address match mechanism employs a method of stopping program execution or generating an interrupt when an address match is detected. However, simply stopping when an address match is detected limits the scope of use and is often not actually useful. In addition, when generating an interrupt, it is necessary to maintain program continuity before and after address match detection, but this is difficult for computers that use a pipeline system or have an instruction set with complex operations.
It is extremely difficult to realize this. Furthermore, the acquired information may lack immediacy and may not be useful for investigating hardware problems. In particular, when generating an interrupt to obtain information, performance naturally deteriorates. This is unacceptable for some uses of the system and is not suitable for troubleshooting.

This invention was made in view of the above circumstances, and its purpose is to make it possible to use the address match detection mechanism more effectively when debugging or troubleshooting hardware/software, without deteriorating performance, and to improve program performance. An object of the present invention is to provide an address match timing trace mechanism that enables immediate acquisition of information without impairing continuity.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an address match register means for holding an address to be detected for an address match, and an address match register means for holding an address to be detected for an address match. an address match detection means that compares the contents of the address match register means (memory address) and the contents of the address match register means and determines whether there is a match (that is, the presence or absence of an address match); and a trace memory for storing multiple sets of various information at the time of memory access. A trace memory in which a storage operation is performed every time an address match is detected by the address match detection means at the time of memory access, and an address of this trace memory are specified, and an address is specified each time a storage operation of the memory is performed. The present invention is characterized in that it is provided with a counter means that is updated.

(Operation) According to the above configuration, when an address match is detected by the address match detecting means at the time of memory access, various information in the system at that time is written to the trace memory. The above-mentioned various information includes, for example, data at the time of corresponding memory access, information specifying the issued instruction (program status word, program counter, branch trace register, instruction word, etc.).

When the above information is written, the address of the counter means is updated, and the next address for the trace memory is specified. In this way, regarding address match detection performed multiple times, various information at each detection time is traced to the trace memory.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block configuration around an address match timing trace mechanism provided in a computer system. In the figure, 11 is a memory address register (MA) for holding a memory address that specifies a memory access destination.
R), 12-1 to 12-n are various registers inside the computer system (hereinafter referred to as internal registers), and 13 is an address match timing trace mechanism. The address match timing trace mechanism 13 includes an address match register (AMR) 14 for holding an address for which a match with a target address of memory access is to be detected, that is, a memory address subject to address match detection, and a memory A comparator 15 for comparing both contents of the address register 11 and detecting a match (address match), an output of this comparator 15 (address match detection result) and a memory address register 1
(AND) 17 for detecting that all memory access signals 16 indicating that there is an access to the address specified by 1 are true. The address match timing trace mechanism 13 further enters a writable state in accordance with the state of the output signal of the AND gate 17, and the trace memory into which information held in the memory address register 11 and internal registers 12-1-12-n is written. 18, and a counter 19 for specifying the address of this trace memory 18. This counter 19 is designed to count up in response to the output signal of the anti-game 17 every time information is written into the trace memory 18.

Now, in a computer system, a problem may occur in which, for example, data at a specific address on the memory is destroyed. However, data destruction generally does not immediately lead to abnormal operation, and therefore it is difficult to trace the cause of such malfunctions. The present invention provides an effective tool in such cases. The first above
The configuration shown in the figure shows one embodiment of the present invention, and its operation will be explained below.

First, the memory address where data destruction occurs is set in the address match register 14 in the address match timing trace mechanism 13.

Then, in this state, start the program to be investigated. When memory access is performed in the processing of this activated program, a memory address indicating the memory access destination is held in the memory address register 11. At this time, address match timing trace mechanism 1
Comparator 15 in memory address register 1
1 and the contents of the address match register 14 are compared (
The output of the comparator 15 (the address match detection result) becomes true only when the two contents match (therefore, only when an address match is detected).

The output of the comparator 15 (address match detection result) is supplied to the AND gate 17 together with the memory access signal 1G. The memory access signal 11m becomes true when memory access is performed. Therefore, when the output of the comparator 15 is true during memory access, that is, when the memory access to the memory address indicated by the address match register 14 is performed, the output of the AND gate 17 becomes true. When the output of AND gate I7 becomes true, trace memory 18 becomes writable. As a result, the address of the trace memory 18 specified by the counter 19 is set to the memory address register 11 and the internal register 12-1 at that point in time (that is, at the point in time when an address match is detected).
Each piece of information held in ~l 2-n is stored (traced). The above information includes data at the time of memory access in which an address match was detected, information specifying the issued instruction (program status word, contents of the program counter, contents of the branch trace register, instruction word, etc.). Then, when each of the above information is stored in the trace memory 18, the counter 19 starts counting in response to the transition from true to false in the output of the AND gate 17 (corresponding to the transition from true to false in the memory access signal 16). and specify the next information storage address for the trace memory 18. If the counter 19 specifies the final address of the trace memory 18, the counter I9 specifies the first address of the trace memory 18 by counting up as described above. On the other hand, execution of the program to be investigated continues as is.

The above operations are repeated during the execution period of the program to be investigated. Therefore, if execution of the program to be investigated ends abnormally due to data destruction, by investigating the contents of the trace memory 18, it becomes possible to easily identify the location of the problem.

[Effect of the invention] As detailed above, according to the present invention, the hardware/
For software debugging or troubleshooting, each time an address match is detected by the address match detection mechanism during memory access, various information at the time of the memory access is written to the trace memory, and each time the trace memory is By adopting a configuration that updates addresses, it becomes possible to trace various information to the trace memory regarding address match detections that have occurred multiple times in the past, and by using the information in this trace memory, it is possible to Debugging can be performed efficiently in cases such as when the above data corruption occurs. In addition, information tracing when an address match is detected can be easily realized, and unlike the method of generating an interrupt when an address match occurs, program continuity can be maintained without requiring complicated control, and there is no performance deterioration. It is also effective when troubleshooting.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 11...Memory address register (MAR), 12
-1 to 12-n... Internal register, 13... Address match timing trace mechanism, 14... Address match register (AMR), 15... Comparator (address match detection means), 17... ANDGATE (AN
D), 18...Trace memory, 19...Counter.

Claims (1)

[Claims] A computer system comprising memory address register means for holding a memory address specifying a memory access destination, and in which memory access is performed based on the memory address held in the memory address register means. , an address match in which a match with the target address of memory access is to be detected; an address match register means for holding a memory address to be detected; and an address match in which the contents held by both this address match register means and the memory address register means match. and a trace memory for storing multiple sets of various information at the time of memory access, the storage operation being performed every time an address match is detected by the address match detection means during memory access. 1. An address match timing tracing mechanism comprising: a trace memory in which data is stored; and counter means for specifying an address of the trace memory and updating the address each time a storage operation is performed in the memory.