JPH0362243B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring structure of a matrix type display device using, for example, a liquid crystal or the like, and particularly a so-called thin film transistor (hereinafter abbreviated as TFT) array thereof.

FIG. 1 is a circuit configuration diagram showing a portion of a TFT array used in a matrix type liquid crystal display device. In the figure, 1 is a gate line, 2 is a source line (or drain line), 3 is a TFT made of a MOS transistor, 4 is a display electrode for applying voltage to the liquid crystal, 5 is a storage capacitor, 6 is a liquid crystal, and 7 is a
In the TFT array, 100 indicates a unit display pixel.
The TFT array 7 includes a plurality of gate lines 1 and a plurality of source lines (or drain lines) 2 orthogonal to these gate lines 1, and at each intersection thereof,
A TFT 3 consisting of a MOS transistor, a display electrode 4, a signal storage capacitor 5, etc. are formed.
This constitutes a unit display pixel 100.

FIG. 2 is a partial sectional view showing a matrix type liquid crystal display device using such a TFT array 7. As shown in FIG. In the figure, 8 is a TFT array substrate, 9 is a transparent conductive film, and 10 is a counter substrate having a transparent conductive film 9 facing the TFT array substrate 8. is being held. Reference numeral 11 indicates a matrix type liquid crystal display device, in which a voltage is applied between the display electrode 4 and the transparent conductive film 9 according to a signal from the TFT array 7.
A liquid crystal display is displayed. The conventional TFT array 7 used in such a matrix type liquid crystal display device 11 is formed with the following configuration.

FIG. 3 is a partial plan view showing a unit display pixel of a TFT array in a conventional matrix type liquid crystal display device, and FIG. 4 is a partial sectional view taken along the line - in FIG.

In the figure, 12 is a drain electrode (or source electrode), 13 is a semiconductor layer of TFT, 14 is an intersection of gate line 1 and source line (or drain line) 2,
Reference numeral 15 indicates an interlayer insulating film between the gate line 1 and the source line (or drain line) 2.

The TFT array 7 used in such a conventional matrix type liquid crystal display device 11 includes, for example, a TFT array substrate 8 made of an insulating substrate such as quartz glass, a TFT 3 made of a plurality of MOS transistors, and a storage capacitor. 5 and the display electrode 4, and after forming, for example, aluminum or the like, which will become the source line (or drain line) 2, by a vapor deposition method and patterning, the interlayer insulating film 15 is formed by forming, for example,
Plasma of silicon nitride (SiN) etc.
The gate line 1 is formed by forming and patterning using a CVD method or the like. For example, the TFT array 7 is formed by forming aluminum or the like by a vapor deposition method or the like and patterning it. Further, as another embodiment, the gate line 1 is formed of polycrystalline silicon doped with semiconductor impurities, then the interlayer insulating film 15 is formed, and the source line (or drain line) 2 is formed of aluminum or the like to form a TFT. There are also ways to configure array 7. (Illustration is omitted.) The matrix type liquid crystal display device 11 using the TFT array 7 having such a configuration usually has a unit display pixel 100 shown in FIGS. 1 and 3 because it is used for image display. The size of one side is
The width is limited to about 50 μm to 1 mm, and the number of display pixels usually requires several thousand to several million.
Therefore, the intersection 1 between the source line 1 and the source line (or drain line) 2 formed in the TFT array 7
The number 4 is also formed in the same number as the number of display pixels.
Further, the line widths of the gate line 1 and the source line (or drain line) 2 are limited to about several tens of micrometers due to restrictions such as the aperture ratio of the matrix type liquid crystal display device. Requires a length that corresponds to the size.

However, the conventional matrix type liquid crystal display device 11
As mentioned above, the gate line 1 and source line (or drain line) 2 in the TFT array 7 used for this are made of aluminum or the like.
Although a low-resistance wiring can be obtained, hillocks are likely to occur, and therefore short circuits are likely to occur frequently, particularly at the intersection 14 between the gate line 1 and the source line (or drain line) 2.

Furthermore, as shown in the other example of the conventional TFT array 7 mentioned above, when polycrystalline silicon doped with semiconductor impurities is used for the gate line 1 and aluminum or the like is used for the source line (or drain line) 2, Although a short circuit is less likely to occur at the intersection 14 of both wirings 1 and 2, there is a drawback that the gate line 1 is not made of a metal conductor, resulting in high resistance. As described above, the TFT array used in the conventional matrix type liquid crystal display device has the drawback that it is difficult to obtain wiring with good interlayer insulation between the gate line and the source line (or drain line) and with low resistance.

This invention was made to eliminate the above-mentioned drawbacks, and the gate line and source line (or drain line) are
The wiring connecting the above-mentioned intersections is made of a conductive semiconductor layer mixed with a high concentration of semiconductor impurities, and at least part of it is made of a metal layer, thereby achieving low resistance and interlayer insulation. The purpose is to create a good wiring structure.

An embodiment of the present invention will be described below with reference to the drawings. 5 is a partial plan view showing a unit display pixel of a TFT array according to the present invention, FIG. 6 is a partial sectional view taken along the line - in FIG. 5, and FIG. 7 is a partial sectional view taken along the line - in FIG. FIG. In the figure, 16 is a contact hole, 17 is a second gate line, and 18 is a second source line (or second drain line), which are connected to the source line (or drain line) 2 through the contact hole 16.

The TFT array 7 having such a configuration is first formed by integrating a plurality of semiconductor layers 13 and source lines (or drain lines) 2 on the surface of a TFT array substrate 8 made of an insulating substrate such as quartz glass. Then, an N-type or P-type semiconductor impurity such as phosphorus or boron is added to the drain region (or source region) and the source line (or drain line) of the semiconductor at a surface concentration of, for example, 10 ¹⁸ /
A source line (or drain line) 2 and a drain region (or source region) made of this diffusion layer are formed by selective diffusion to a high concentration of cm ³ or more, and then a gate line 1 and a source line (or drain line) are formed. The interlayer insulating film 15 (line) 2 is formed of SiO ₂ to a thickness of approximately 1000 to 20000 Å by, for example, a silicon thermal oxidation method. Thereafter, as the material for the gate line 1, a polycrystalline silicon/SiO ₂ /semiconductor (Si) system with good compatibility with the semiconductor layer 13, which has a stable and controllable work function, and metals such as aluminum are used. For example, polycrystalline silicon doped with a semiconductor impurity such as phosphorus at a concentration of 10 ¹⁵ to 10 ¹⁶ /cm ² is processed by low-pressure CVD, which allows ohmic contact to be easily obtained and the film formation technique is simple. etc., for example, film thickness 5000
The gate line 1 is formed by forming a film with a thickness of Å. Thereafter, the contact hole 16 of the source line (or drain line) 2 formed from the diffusion layer is patterned by photoetching or the like, and the second source line (or second drain line) 18, second gate line 17 and As the drain electrode (or source electrode) 12, an aluminum alloy such as Al--Si is formed into a film with a thickness of about 7000 Å by, for example, a sputtering method. At this time, the second source line (or second drain line) 18 and second gate line 17 are not formed at the intersection 14 of the gate line 1 and the source line (or drain line) 2, as shown in FIG. First, the gate line 1 and the source line (or drain line) 2 between each intersection 14 are formed so as to be short-circuited.
Use two-layer wiring. TFT formed in this way
Using the array 7, a matrix type liquid crystal display device 11 is obtained in the same manner as in the conventional example.

In the embodiment of the present invention, the second source line (or second drain line) 18 is connected to the source line (or drain line) through two contact holes 16.
2, however, the connection area may be increased to create a more stable and low resistance wiring. 8 and 9 are partial sectional views taken along the line -- in FIG. 5, showing other embodiments of the TFT array according to the present invention.

FIG. 8 shows an example in which the number of contact holes 16 is increased, and FIG. 9 shows an example in which slit-shaped contact holes 16 are formed. Further, in the embodiment of the present invention, the gate line and the source line (or drain line) are shown as two-layer wiring, but the wiring structure of the gate line and the source line (or drain line) is different from that of the gate line 1. Source line (or drain line) 2
The crossing portions 14 may be made of a semiconductor mixed with semiconductor impurities, and the portions between the crossing portions 14 may be made of metal, and may be formed integrally to form a gate line and a source line (or drain line) made of a single layer.

Further, although the embodiments of the present invention have been described using the matrix type liquid crystal display device 11, the present invention can also be applied to a matrix type display device using, for example, an electrochromic element. Further, in the embodiment of the present invention, the gate line 1 is formed by CVD method using polycrystalline silicon doped with semiconductor impurities, but the polycrystalline silicon layer may also be formed by vapor phase epitaxy or impurity mixing method. It may also be mixed in by ion implantation.

As described above, according to the present invention, the gate line and the source line (or drain line) are configured such that the intersection of these lines is made of a conductive semiconductor layer mixed with a high concentration of semiconductor impurities, and the intersection of the gate line and the source line (or drain line) is Since at least a part of the wiring connecting the part and the crossing part is made of a metal layer, it has a wiring structure with low resistance and good interlayer insulation between the gate line and the source line (or drain line). This has the effect of providing a high-grade, high-quality matrix display device free of point defects and linear defects.

[Brief explanation of drawings]

Figure 1 is a circuit configuration diagram showing a portion of a TFT array used in a matrix type liquid crystal display device;
The figure is a partial cross-sectional view showing a matrix-type liquid crystal display device, FIG. 3 is a partial plan view showing a unit display pixel of a TFT array in a conventional matrix-type liquid crystal display device, and FIG. 4 is a portion along the - line in FIG. 3. 5 is a partial plan view showing a unit display pixel of a TFT array according to the present invention, FIG. 6 is a partial sectional view taken along the - line in FIG. 5, and FIG. 7 is a partial plan view taken along the - line in FIG. 8 and 9 are partial sectional views taken along the - line of FIG. 5, respectively, showing other embodiments of the TFT array according to the present invention. In the figure, 1 is a gate line, 2 is a source line (or drain line), 3 is a TFT made of a MOS transistor, 11 is a matrix type display device, 100
14 indicates a unit display pixel, and 14 indicates an intersection of a gate line and a source line (or drain line). In addition,
The same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 Display pixels having MOS transistors are arranged in a matrix, and a plurality of gate lines and a plurality of source lines (or drain lines) connected to these transistors are arranged in a lattice shape through an insulating layer. In the case where the gate line and the source line (or the drain line) are wired, the intersection of these wires is made of 10 ¹⁵ phosphorus or boron.
1. A matrix type display device comprising a silicon layer mixed at a concentration of 1/cm ² or more, and wherein at least a portion of the wiring connecting the crossing portions is comprised of a metal layer. 2. Gate lines and source lines (or drain lines) are made of a silicon layer and a metal layer in which phosphorus or boron is mixed at a concentration of 10 ¹⁵ /cm ² or more, and the wiring that connects the intersections of these wirings. 2. The matrix display device according to claim 1, wherein the matrix display device is constructed of two-layer wiring.