JPH0362536A - Method for interconnecting electrode terminals and manufacturing method for electrical connection structure - Google Patents
Method for interconnecting electrode terminals and manufacturing method for electrical connection structureInfo
- Publication number
- JPH0362536A JPH0362536A JP19695089A JP19695089A JPH0362536A JP H0362536 A JPH0362536 A JP H0362536A JP 19695089 A JP19695089 A JP 19695089A JP 19695089 A JP19695089 A JP 19695089A JP H0362536 A JPH0362536 A JP H0362536A
- Authority
- JP
- Japan
- Prior art keywords
- fine particles
- conductive fine
- wiring board
- potential
- charged
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、他の配線基板等と相対峙する配線基板の電極
端子を導電性微粒子を介して電気的に相互接続するため
に、配線基板上に導電性微粒子を散布する方法に関する
ものである。Detailed Description of the Invention [Industrial Application Field] The present invention provides a wiring board for electrically interconnecting electrode terminals of a wiring board facing another wiring board etc. via conductive fine particles. The present invention relates to a method of dispersing conductive fine particles onto a surface.
[従来の技術]
従来、相対峙する配線基板の電極端子を導電性微粒子を
介して電気的に相互接続するために、配線基板上に導電
性微粒子を散布する方法として、第5図に示すように、
導電性微粒子10aをコロナ放電電極1によって作られ
るコロナ電界中を通過させて帯電させ、帯電した導電性
微粒子10bを配線基板の電極端子4上に電界を集中さ
せた静電界中で散布を行う方法が用いられている。[Prior Art] Conventionally, in order to electrically interconnect electrode terminals of opposing wiring boards via conductive fine particles, a method of dispersing conductive fine particles onto a wiring board is shown in FIG. To,
A method of charging conductive fine particles 10a by passing them through a corona electric field created by a corona discharge electrode 1, and scattering the charged conductive fine particles 10b on an electrode terminal 4 of a wiring board in an electrostatic field where the electric field is concentrated. is used.
[発明が解決しようとする課題]
しかしながら、上記従来例の導電粒子の散布方法では、
配線基板上の導電性微粒子を必要としない部位に付着す
る導電性微粒子10dが相当数在り、配線基板上の配線
間の絶縁抵抗を低下させる場合があった。[Problem to be solved by the invention] However, in the conventional method for dispersing conductive particles,
There were a considerable number of conductive fine particles 10d that adhered to areas on the wiring board where conductive fine particles were not required, and the insulation resistance between the wirings on the wiring board could be lowered.
また、特に、配線基板上に半導体素子をフェースダウン
で接続する場合に半導体素子のダイエツジ部に対応する
部分に導電性微粒子が存在する場合、エツジショートを
生じさせる場合があった。Furthermore, particularly when semiconductor elements are connected face-down on a wiring board, if conductive particles are present in a portion of the semiconductor element corresponding to the die edge portion, edge shorts may occur.
また、相対峙して接続される配線基板において、相対峙
して接続される電極の間隙よりも狭くなる部分に粒子が
存在する場合、相対峙する電極端子を近接させて導電性
微粒子を挟み込むことに支障を来たすことがあった。In addition, in wiring boards that are connected facing each other, if particles are present in a part that is narrower than the gap between the electrodes that are connected facing each other, it is possible to bring the facing electrode terminals closer together and sandwich the conductive fine particles. There were times when it caused problems.
本発明の目的は、このような従来技術の問題点に鑑み、
導電性微粒子の散布方法において、導電性微粒子を配線
基板上の必要な部分にのみ散布できるようにすることに
ある。In view of the problems of the prior art, an object of the present invention is to
In a method for dispersing conductive fine particles, it is an object of the present invention to enable conductive fine particles to be dispersed only to necessary portions on a wiring board.
[課題を解決するための手段]
上記目的を達成するため本発明では、他の配線基板また
は部品の接続部分に対して電気的に接続される配線基板
の電極端子上に、帯電した導電性微粒子をその電極端子
に電界が集中するような静電界中で散布する方法におい
て、配線基板上の導電性微粒子の付着を所望しない部位
に導電性微粒子の帯電電位と同極性の電位をもたせるよ
うにしている。[Means for Solving the Problems] In order to achieve the above object, the present invention provides electrically charged conductive fine particles on electrode terminals of a wiring board that is electrically connected to a connecting portion of another wiring board or a component. In the method of dispersing in an electrostatic field where the electric field concentrates on the electrode terminal, a potential of the same polarity as the charged potential of the conductive fine particles is applied to a portion of the wiring board where the conductive fine particles are not desired to adhere. There is.
ここで、配線基板上で導電性微粒子の付着を所望しない
部位に導電性微粒子の帯電電位と同極性の電位を持たせ
る方法としては、その部位を誘電体からなる絶縁物とし
、コロナ放電等により生じさせたフリーイオンを絶縁体
表面に付着させる方法がある。あるいは、その部位に電
極パターンを設けて電位を与える方法がある。Here, as a method of imparting a potential of the same polarity as the charged potential of the conductive particles to a part on the wiring board where it is not desired that the conductive particles adhere, the part is made of an insulator made of a dielectric material, and by corona discharge etc. There is a method in which the generated free ions are attached to the surface of an insulator. Alternatively, there is a method of providing an electrode pattern at that part and applying a potential.
さらに電極端子には、アース電位、または導電性微粒子
の帯電電位と逆極性の電位を与えるようにしてもよい。Further, the electrode terminal may be applied with a ground potential or a potential with a polarity opposite to the charged potential of the conductive fine particles.
[作用]
この構成において、帯電した導電性微粒子は、電極端子
に電界を集中させた静電界中で散布されるが、配線基板
上で導電性微粒子の付着を所望しない部位に導電性微粒
子の帯電電位と同極性の電位を持たせるようにしたため
、この部位と導電性微粒子との間に静電応力が働き、配
線基板上の導電性微粒子を必要としない部分に導電性微
粒子が付着することが回避される。[Function] In this configuration, the charged conductive fine particles are scattered in an electrostatic field where the electric field is concentrated on the electrode terminal, but the charged conductive fine particles are scattered in areas on the wiring board where the conductive fine particles are not desired to adhere. Because the electrical potential is made to have the same polarity as the potential, electrostatic stress acts between this area and the conductive particles, and the conductive particles may adhere to areas on the wiring board where they are not needed. Avoided.
[実施例] 以下、図面を用いて本発明の詳細な説明する。[Example] Hereinafter, the present invention will be explained in detail using the drawings.
第1図(a)および(b)は本発明の一実施例に係る導
電性粒子の散布方法を示す。FIGS. 1(a) and 1(b) show a method of dispersing conductive particles according to an embodiment of the present invention.
同図において、1はコロナ放電により導電性微粒子10
aを帯電するためのコロナ帯電ピン(コロナ放電電極)
、2はコロナ帯電ピン1に電圧を印加するための高圧電
源、4は配線基板の電極(端子)、6は配線基板のベー
ス基板、7は平板電極(電極板)、13は平板電極7を
アース電位にするためのアース線、9は導電性微粒子を
コロナ帯電ピンに導くための散布ガン、8aは配線基板
の電極端子をアース電位にするためのアース線である。In the same figure, 1 indicates conductive fine particles 10 due to corona discharge.
Corona charging pin (corona discharge electrode) for charging a
, 2 is a high-voltage power supply for applying voltage to the corona charging pin 1, 4 is an electrode (terminal) of the wiring board, 6 is the base board of the wiring board, 7 is a flat plate electrode (electrode plate), and 13 is the flat plate electrode 7. A ground wire 9 is used to bring the conductive particles to the corona charging pin, and 8a is a ground wire used to bring the electrode terminals of the wiring board to the earth potential.
この構成において配線基板上に導電性粒子を散布するた
めには、まず、第1図(a)に示すように、配線基板上
で導電性微粒子の付着を所望しない部位5に誘電物から
なる絶縁物5を設け、配線基板をコロナ放電電極1とア
ース電位に接地された電極板7との間に位置させ、そし
て、コロナ放電電極1から発生したフリーイオン(マイ
ナスイオン)3aを絶縁膜5上に付着させ、絶縁膜5を
帯電させる。In order to scatter conductive particles onto the wiring board in this configuration, first, as shown in FIG. A wiring board is placed between the corona discharge electrode 1 and the electrode plate 7 grounded to earth potential, and free ions (negative ions) 3a generated from the corona discharge electrode 1 are transferred onto the insulating film 5. to charge the insulating film 5.
その後、第1図(b)に示すように、導電性微粒子10
aをコロナ放電電極1により作られるコロナ電界中を通
過させ、帯電させる。これにより、帯電した導電性微粒
子10bは放電電極1とアース電位かもしくは導電性微
粒子の帯電電位と逆極性の電位を与えられた配線基板の
取出し電極4との間に作られた静電電界中で電気力線1
1に沿って導かれ、取出し電極4の接続部に付着する。Thereafter, as shown in FIG. 1(b), conductive fine particles 10
a is passed through a corona electric field created by a corona discharge electrode 1 and charged. As a result, the charged conductive fine particles 10b are placed in an electrostatic electric field created between the discharge electrode 1 and the lead-out electrode 4 of the wiring board, which is given a ground potential or a potential of opposite polarity to the charged potential of the conductive fine particles. electric field lines 1
1 and attached to the connection part of the extraction electrode 4.
このとき絶縁膜5上は、帯電した微粒子10bと同極性
の電位に帯電しているため、帯電微粒子tabは、絶縁
膜5に対して静電応力により反発され、導電性微粒子が
絶縁膜5上に付着することを避けることができる。At this time, since the surface of the insulating film 5 is charged to the same polarity potential as the charged fine particles 10b, the charged fine particles tab are repelled by the electrostatic stress against the insulating film 5, and the conductive fine particles are moved onto the insulating film 5. can be avoided from adhering to.
第2図(a)および(b)は本発明の他の実施例に係る
方法を示す。この方法においては、まず、配線基板上で
導電性微粒子の付着を所望しない部位に導電性微粒子の
帯電電位と同極性の電位を持たせるために、その部位に
電極パターン12を設(す、これを上述と同様にして、
散布される導電性微粒子の帯電電位と同極性に帯電させ
る。FIGS. 2(a) and 2(b) illustrate a method according to another embodiment of the invention. In this method, first, an electrode pattern 12 is provided on the wiring board in order to give a potential of the same polarity as the charged potential of the conductive particles to a region on the wiring board where it is not desired that the conductive particles adhere. in the same way as above,
It is charged to the same polarity as the charged potential of the conductive fine particles to be dispersed.
その後、第2図(b)に示すように、上述と同様にして
導電性微粒子10aを帯電させ、静電界中で散布を行う
。この時、電極パターン12は、導電性微粒子の帯電電
位と同極性に帯電しているため、帯電した導電性微粒子
10bは、電極パターン12により静電応力によって反
発され、導電性微粒子が電極パターン上に付着すること
を避けることができる。Thereafter, as shown in FIG. 2(b), the conductive fine particles 10a are charged and dispersed in an electrostatic field in the same manner as described above. At this time, since the electrode pattern 12 is charged with the same polarity as the charged potential of the conductive fine particles, the charged conductive fine particles 10b are repelled by the electrostatic stress of the electrode pattern 12, and the conductive fine particles are moved onto the electrode pattern. can be avoided from adhering to.
第3図はさらに他の実施例を示す。配線基板上で導電性
微粒子の付着を所望しない部位に導電性微粒子の帯電電
位と同極性の電位を持たせるために、その部位に電極パ
ターン12を設ける点は上述と同様であるが、ここでは
電極パターン12に対し電源14により電位を与え、あ
とは上述と同様にして導電性微粒子を帯電させ、静電界
中で散布する。この時、電極パターン12は、導電性微
粒子10bの帯電電位と同極性の電位を与えられている
ため、帯電した導電性微粒子tabは、電極パターン1
2により静電応力によって反発され、導電性微粒子ta
bが電極パターン12上に付着することを避けることが
できる。FIG. 3 shows yet another embodiment. In order to give a potential of the same polarity as the charged potential of the conductive particles to a region on the wiring board where it is not desired that the conductive particles adhere, the electrode pattern 12 is provided in that region, but here A potential is applied to the electrode pattern 12 by the power source 14, and the conductive fine particles are then charged and dispersed in an electrostatic field in the same manner as described above. At this time, since the electrode pattern 12 is given a potential of the same polarity as the charged potential of the conductive fine particles 10b, the charged conductive fine particles tab are
2, the conductive fine particles ta are repelled by electrostatic stress.
b can be prevented from adhering to the electrode pattern 12.
さらに、第4図に示すように、配線基板上の電極端子4
に導電性微粒子tabの帯電電位と逆極性の電位を電源
8aによって与えるようにしてもよく、これにより、帯
電した導電性微粒子10bと電極端子4との静電引力を
増し、第3図(a)の場合に比し、導電性微粒子を電極
端子上に付着させ易くすることができる。Furthermore, as shown in FIG. 4, electrode terminals 4 on the wiring board
The power supply 8a may apply a potential of opposite polarity to the charged potential of the conductive fine particles tab, thereby increasing the electrostatic attraction between the charged conductive fine particles 10b and the electrode terminal 4, as shown in FIG. 3(a). ) The conductive fine particles can be easily attached onto the electrode terminals.
[発明の効果] 以上述べたように本発明は以下のような効果を有する。[Effect of the invention] As described above, the present invention has the following effects.
すなわち、配線基板上で導電性微粒子の付着を所望しな
い部位に導電性微粒子の帯電電位と同極性の電位を持た
せることによってこの部位と導電性微粒子との間に静電
応力を働かせるようにしたため、配線基板上の導電性微
粒子を必要としない部位に導電性微粒子が付着すること
を回避することができる。That is, by applying a potential of the same polarity as the charged potential of the conductive particles to a portion of the wiring board where it is not desired that the conductive particles adhere, electrostatic stress is exerted between this portion and the conductive particles. , it is possible to avoid adhesion of conductive fine particles to areas on the wiring board that do not require conductive fine particles.
これにより、導電性微粒子が、相対峙して接続される配
線基板の電極端子上以外の場所に付着することを避ける
ことができ、配線間の絶縁抵抗が高く、信頼性の高い配
線基板の電気的相互接続を行うことができる。This prevents conductive particles from adhering to areas other than the electrode terminals of the wiring board that are connected facing each other. physical interconnection.
また、配線基板上に半導体素子をフェースダウンで接続
するために導電性微粒子を用いて電気的接続を行う場合
、配線基板上の半導体素子のダイエツジ部に対応する部
分に導電性微粒子が付着することを避けることができ、
配線基板と半導体素子のエツジショートの発生を防止す
ることができる。Furthermore, when electrical connection is made using conductive particles to connect semiconductor elements face-down on a wiring board, the conductive particles may adhere to the portions of the wiring board that correspond to the die edges of the semiconductor elements. can be avoided,
It is possible to prevent edge shorts between the wiring board and the semiconductor element.
また、導電性微粒子を用いて、相対峙する配線基板を電
気的に相互接続する場合、相対峙して接続される電極端
子の間隙よりも狭くなる部分への導電性微粒子の付着を
避けることができ、したがって、配線基板を圧着して接
続する場合に、相対峙する電極端子の間隙を狭めてなお
かつ導電性微粒子を挟み込むことを支障なく行うことが
できる。Furthermore, when electrically interconnecting wiring boards facing each other using conductive fine particles, it is important to avoid adhesion of the conductive fine particles to areas that are narrower than the gap between electrode terminals that are connected facing each other. Therefore, when connecting wiring boards by crimping, it is possible to narrow the gap between opposing electrode terminals and sandwich the conductive fine particles without any problem.
さらに、配線基板上で導電性微粒子の付着を所望しない
部位の電位を高めることにより、その部位の近辺への導
電性微粒子の付着を避けることができる。Furthermore, by increasing the potential of a portion of the wiring board where the attachment of conductive fine particles is not desired, adhesion of conductive fine particles to the vicinity of that portion can be avoided.
第1図(a)および(b)は、本発明の一実施例に係る
導電性微粒子の散布方法を示す模式図、第2図(a)お
よび(b)は、本発明の他の実施例に係る導電性微粒子
の散布方法を示す模式図、
第3図および第4図はそれぞれ本発明のさらに他の実施
例に係る導電性微粒子の散布方法を示す模式図、そして
第5図は、従来例に係る導電性微粒子の散布方法を示す
模式図である。
1:コロナ;witピン、2:高圧電源、3a:Vイナ
スイオン、3b:フリーイオン、4:配線基板の電極端
子、5:絶縁物、6:配線基板のベース基板、7:平板
電極、13:アース線、9:散布ガン、10a:帯電前
の導電性微粒子、101)=帯電した導電性微粒子、1
0c:N、Fix端子上に付着した導電性微粒子、11
:電気力線、12:電極パターン、3c:フリーイオン
、8a:アース線、13,14:電源、10d:導電性
微粒子。
第
図
第
図
第
図FIGS. 1(a) and (b) are schematic diagrams showing a method of dispersing conductive fine particles according to one embodiment of the present invention, and FIGS. 2(a) and (b) are other embodiments of the present invention. FIG. 3 and FIG. 4 are schematic diagrams showing a method of dispersing conductive fine particles according to still another embodiment of the present invention, and FIG. FIG. 2 is a schematic diagram showing a method of dispersing conductive fine particles according to an example. 1: corona; wit pin, 2: high voltage power supply, 3a: V inus ion, 3b: free ion, 4: electrode terminal of wiring board, 5: insulator, 6: base board of wiring board, 7: flat plate electrode, 13: Earth wire, 9: Spray gun, 10a: Conductive fine particles before charging, 101) = Charged conductive fine particles, 1
0c: N, conductive fine particles attached to the Fix terminal, 11
: electric force lines, 12: electrode pattern, 3c: free ions, 8a: ground wire, 13, 14: power supply, 10d: conductive fine particles. Figure Figure Figure Figure
Claims (3)
的に接続される配線基板の電極端子上に、帯電した導電
性微粒子をその電極端子に電界が集中するような静電界
中で散布する方法において、配線基板上の導電性微粒子
の付着を所望しない部位に導電性微粒子の帯電電位と同
極性の電位をもたせることを特徴とする導電性微粒子の
散布方法。(1) Spray charged conductive fine particles onto the electrode terminal of a wiring board that is electrically connected to the connection part of another wiring board or component in an electrostatic field that concentrates the electric field on the electrode terminal. A method for dispersing conductive fine particles, the method comprising applying a potential of the same polarity as the charged potential of the conductive fine particles to a portion of the wiring board where the conductive fine particles are not desired to adhere.
位に電極パターンを設けるようにした、請求項1記載の
導電性微粒子の散布方法。(2) The method for dispersing conductive fine particles according to claim 1, wherein the electrode pattern is provided at a portion of the wiring board where attachment of the conductive fine particles is not desired.
電電位と逆極性の電位を与える請求項1記載の導電性微
粒子の散布方法。(3) The method for dispersing conductive fine particles according to claim 1, wherein the electrode terminal is given a ground potential or a potential of opposite polarity to the charged potential of the conductive fine particles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1196950A JPH0691129B2 (en) | 1989-07-31 | 1989-07-31 | Method of interconnecting electrode terminals and method of manufacturing electrical connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1196950A JPH0691129B2 (en) | 1989-07-31 | 1989-07-31 | Method of interconnecting electrode terminals and method of manufacturing electrical connection structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0362536A true JPH0362536A (en) | 1991-03-18 |
| JPH0691129B2 JPH0691129B2 (en) | 1994-11-14 |
Family
ID=16366358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1196950A Expired - Fee Related JPH0691129B2 (en) | 1989-07-31 | 1989-07-31 | Method of interconnecting electrode terminals and method of manufacturing electrical connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691129B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0788300A1 (en) * | 1996-02-01 | 1997-08-06 | Motorola, Inc. | Method and apparatus for forming a conductive layer on a printed wiring board terminal |
| JP2007524230A (en) * | 2003-07-09 | 2007-08-23 | フライズ メタルズ インコーポレイテッド | Deposition and patterning methods |
| JP2011171370A (en) * | 2010-02-16 | 2011-09-01 | Renesas Electronics Corp | Method for manufacturing semiconductor device, particle and semiconductor device |
| JP2011222753A (en) * | 2010-04-09 | 2011-11-04 | Toyota Motor Corp | Solder powder supplying device and printing apparatus, and solder powder supplying method and printing method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573962B1 (en) * | 1997-06-13 | 2003-06-03 | Sharp Kabushiki Kaisha | Method of arranging particulates liquid crystal display, and anistropic conductive film |
| US6577373B1 (en) * | 1997-06-13 | 2003-06-10 | Sekisui Chemical Co., Ltd. | Liquid crystal display and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152470A (en) * | 1978-05-22 | 1979-11-30 | Nec Corp | Semiconductor device |
-
1989
- 1989-07-31 JP JP1196950A patent/JPH0691129B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54152470A (en) * | 1978-05-22 | 1979-11-30 | Nec Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0788300A1 (en) * | 1996-02-01 | 1997-08-06 | Motorola, Inc. | Method and apparatus for forming a conductive layer on a printed wiring board terminal |
| JP2007524230A (en) * | 2003-07-09 | 2007-08-23 | フライズ メタルズ インコーポレイテッド | Deposition and patterning methods |
| JP2011171370A (en) * | 2010-02-16 | 2011-09-01 | Renesas Electronics Corp | Method for manufacturing semiconductor device, particle and semiconductor device |
| JP2011222753A (en) * | 2010-04-09 | 2011-11-04 | Toyota Motor Corp | Solder powder supplying device and printing apparatus, and solder powder supplying method and printing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0691129B2 (en) | 1994-11-14 |
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