JPH0362542A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0362542A
JPH0362542A JP1196844A JP19684489A JPH0362542A JP H0362542 A JPH0362542 A JP H0362542A JP 1196844 A JP1196844 A JP 1196844A JP 19684489 A JP19684489 A JP 19684489A JP H0362542 A JPH0362542 A JP H0362542A
Authority
JP
Japan
Prior art keywords
film
semiconductor element
holes
insulating film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1196844A
Other languages
Japanese (ja)
Inventor
Kazunori Sakurai
和徳 桜井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1196844A priority Critical patent/JPH0362542A/en
Publication of JPH0362542A publication Critical patent/JPH0362542A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/701Tape-automated bond [TAB] connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device which is high in strength and the conductivity pattern of which is further minutely formed by sticking a semiconductor element to one side of an insulating film and connecting element of the semiconductor element with the conductivity pattern formed on the other side of the insulating film through holes passed through the film. CONSTITUTION:Resist masks are formed on the surface of a film 1 by applying a photoresist 20 to the surface and removing the photoresist 20 from the parts corresponding to each electrode 7 of a semiconductor element 6 to be stuck to the back surface of the film 1. In addition, a bonding agent 22 is applied to the back surface of the film 1. Then through holes 23 are formed by etching the film 1 at the parts from which the resist 20 is removed and bonding agent 22. Then the element 6 is stuck to the back surface of the film 1, with each electrode 7 of the element 6 being faced to each through hole 23. After the element 6 is stuck, metallic coating films 24 are formed by vapor-depositing, for example, Cr on the surface of the film 1 and inside surface of the holes 23. Then a photoresist 25 is applied to the surface of the film 1 except the component where a conductivity pattern is to be formed and holes 23. After applying the resist 25, the conductive pattern 26 is formed by plating a conductive material, such as gold, etc., to the parts of the back surface where the resist 25 is not applied and the metallic coating films 24 in the holes 23. Finally, the resist 25 is removed from the parts other than the pattern 26.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、絶縁フィルムを用いた半導体装置及びその製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device using an insulating film and a method for manufacturing the same.

[従来の技術] 半導体装置は、一般にリードフレームに設けたダイパッ
ドに半導体素子を取付け、半導体素子の外部電極とリー
ドフレームの端子とをそれぞれワイヤで接続し、これを
エポキシ樹脂の如き熱硬化性樹脂でパッケージしたのち
各端子を切断し、製造している。
[Prior Art] Generally, in a semiconductor device, a semiconductor element is attached to a die pad provided on a lead frame, the external electrodes of the semiconductor element and the terminals of the lead frame are connected with wires, and these are bonded to a thermosetting resin such as epoxy resin. After packaging, each terminal is cut and manufactured.

ところで、最近では電子機器の小形化、薄形化に伴ない
、これに使用する半導体装置も高密度実装するため、薄
くかつ小形の半導体装置の出現が望まれている。このよ
うな要請に答えるべく、ポリイミドフィルムの如き絶縁
フィルムのデバイスホールに半導体素子を配設し、半導
体素子の電極と絶縁フィルムのインナーリードとを接続
し、これに液状の樹脂(例えばエポキシ樹脂)からなる
封止材を印刷あるいはポツティングしてパッケージした
方式の半導体装置が使用されるようになった。
Nowadays, as electronic devices become smaller and thinner, the semiconductor devices used therein are also packaged in higher density, so there is a desire for thinner and smaller semiconductor devices. In order to meet these demands, a semiconductor element is placed in a device hole of an insulating film such as a polyimide film, the electrodes of the semiconductor element are connected to the inner leads of the insulating film, and a liquid resin (for example, epoxy resin) is applied to this. Semiconductor devices that are packaged by printing or potting a sealing material consisting of these materials have come into use.

第2図は絶縁フィルムを用いた従来の半導体装置を説明
するための平面図、第3図はそのA−A拡大断面図であ
る。図において、1は長さ方向に等間隔に、後述の半導
体素子6.8a、8b、・・・の表面積より大きい面積
のデバイスホール2.2a、2b、・・・が設けられた
厚さ75〜125−程度の絶縁フィルム(以下単にフィ
ルムという)である。3はフィルム1に設けられた銅の
如き導電率の高い厚さ15〜40−1幅50〜3001
Jffi程度の金属箔からなる多数の導電パターンで、
その一部はデバイスホール2内に突出してインナーリー
ド3aとなっており、半導体素子6〜6bの電極4と接
続される。5はフィルム1を搬送するためのスプロケッ
ト穴である。
FIG. 2 is a plan view for explaining a conventional semiconductor device using an insulating film, and FIG. 3 is an enlarged sectional view taken along line A-A. In the figure, 1 indicates a thickness 75 in which device holes 2.2a, 2b, . It is an insulating film (hereinafter simply referred to as a film) of about 125-. 3 is a material with high conductivity such as copper provided on the film 1 with a thickness of 15 to 40-1 and a width of 50 to 3001
With a large number of conductive patterns made of metal foil of Jffi level,
A portion thereof protrudes into the device hole 2 to serve as an inner lead 3a, and is connected to the electrodes 4 of the semiconductor elements 6 to 6b. 5 is a sprocket hole for conveying the film 1.

第4図は上記のようなフィルム1に半導体素子を取付け
る装置の一例を示す模式図で、チップ台8上に載置され
た半導体素子6は、位置決めガイド9により所定の位置
に位置決めされる。一方、テープレールIOにガイドさ
れ、スプロケットにより紙面の垂直方向に送られたフィ
ルム1は、そのデバイスホール2が半導体素子6上に達
した位置で停止し、半導体素子6に設けた多数の電極(
図示せず)と、各インナーリード3aとをそれぞれ整合
させる。ついで加熱されたボンディングツール11を下
降させて各インナーリード3aを加圧し、所定の角度に
フォーミングして各インナーリード3aをそれぞれ電極
に融着させ、接続する。次に、フィルム1を移動してそ
れぞれインナーリード3aを切断し、又はスキージ印刷
、ボッティング等により半導体素子6及びインナーリー
ド3aの一部を液状の封止用樹脂で封止して、半導体装
置を製造する。
FIG. 4 is a schematic diagram showing an example of an apparatus for attaching a semiconductor element to the film 1 as described above. The semiconductor element 6 placed on the chip stand 8 is positioned at a predetermined position by a positioning guide 9. On the other hand, the film 1 guided by the tape rail IO and sent in the direction perpendicular to the plane of the paper by the sprocket stops at the position where its device hole 2 reaches above the semiconductor element 6, and the film 1, which is
(not shown) and each inner lead 3a. Next, the heated bonding tool 11 is lowered to apply pressure to each inner lead 3a and form it at a predetermined angle to fuse and connect each inner lead 3a to the electrode. Next, the film 1 is moved to cut each inner lead 3a, or the semiconductor element 6 and a part of the inner lead 3a are sealed with liquid sealing resin by squeegee printing, botting, etc., and the semiconductor device is Manufacture.

[発明が解決しようとする課題] 上記のような半導体装置は、従来の半導体装置に比べて
薄くできる、実装密度を高めることができる等、多くの
特長を有するが、次のような問題がある。
[Problems to be Solved by the Invention] The semiconductor device described above has many features such as being able to be made thinner and having higher packaging density than conventional semiconductor devices, but it also has the following problems. .

(1)第3図に示すように半導体素子6はインナーリー
ド3aに宙吊りになっているので、細密化してインナー
リード3aが増加すると必然的にその幅が細くなり、強
度が低下する。
(1) As shown in FIG. 3, the semiconductor element 6 is suspended from the inner leads 3a, so as the number of inner leads 3a increases due to miniaturization, the width inevitably becomes narrower and the strength decreases.

(2〉半導体素子6の電極4には、インナーリード3a
の先端部とボンディングする際に接続の信頼性を向上し
、また緩衝作用を与えるため金バンブを使用しているの
で、歩留りが悪く、コストアップになる。
(2> The electrode 4 of the semiconductor element 6 has an inner lead 3a
Since gold bumps are used to improve connection reliability and provide a buffering effect when bonding to the tip of the metal, yields are poor and costs increase.

(3)インナーリード3aと半導体素子6の電極4とは
、加熱したボンディングツール11を圧下して融着して
いるので、半導体素子6の能動面に電極が設けられてい
る場合は、ボンディングツール11の圧下によりクラッ
クが発生するおそれがあるため、ボンディングできない
(3) Since the inner lead 3a and the electrode 4 of the semiconductor element 6 are fused by pressing down the heated bonding tool 11, if the electrode is provided on the active surface of the semiconductor element 6, the bonding tool Bonding cannot be performed because cracks may occur due to the reduction of 11.

(4)ボンディング時に半導体素子6に熱的、機械的ス
トレスが加わるため、半導体素子6にクラックが生じ易
く、不良品発生率が高くなる。
(4) Since thermal and mechanical stress is applied to the semiconductor element 6 during bonding, cracks are likely to occur in the semiconductor element 6, increasing the incidence of defective products.

本発明は、上記の課題を解決すべくなされたもので、半
導体素子にストレスを加えることなく絶縁フィルムの導
電パターンと半導体素子の電極とを接続することのでき
る半導体装置及びその製造方法を得ることを目的とする
ものである。
The present invention has been made to solve the above problems, and provides a semiconductor device and a method for manufacturing the same that can connect a conductive pattern of an insulating film and an electrode of a semiconductor element without applying stress to the semiconductor element. The purpose is to

[課題を解決するための手段] 本発明は、半導体素子の各電極に対応して貫通穴が設け
られた絶縁フィルムの一方の面に前記半導体素子の能動
面を接着し、前記絶縁フィルムの他方の面に形成された
導電パターンと前記半導体素子の電極とを前記貫通穴を
介してそれぞれ接続してなる半導体装置。及び、 絶縁フィルムの半導体素子の各電極に対応した位置にそ
れぞれ貫通穴を設けると共に、該絶縁フィルムの一方の
面又は半導体素子の能動面に接着剤を塗布し、前記半導
体素子をその各電極を前記貫通穴にそれぞれ対向させて
前記絶縁フィルムに接着し、ついで前記絶縁フィルムの
他方の面及び前記貫通穴に金属皮膜を形成して前記他方
の面の金属皮膜上に前記各貫通穴の底部に達する導電パ
ターンを形成し、該導電パターンと前記半導体素子の電
極とを接続してなる半導体装置の製造方法を提供するも
のである。
[Means for Solving the Problems] The present invention provides for bonding the active surface of the semiconductor element to one side of an insulating film in which through holes are provided corresponding to each electrode of the semiconductor element, and A semiconductor device in which a conductive pattern formed on a surface of the semiconductor element is connected to an electrode of the semiconductor element through the through hole. and providing through holes in the insulating film at positions corresponding to the respective electrodes of the semiconductor element, applying an adhesive to one surface of the insulating film or the active surface of the semiconductor element, and attaching the semiconductor element to each electrode thereof. Adhere to the insulating film so as to face each of the through holes, and then form a metal film on the other surface of the insulating film and the through holes, and coat the bottom of each of the through holes on the metal film on the other surface. The present invention provides a method for manufacturing a semiconductor device, which comprises forming a conductive pattern that extends to the semiconductor device, and connecting the conductive pattern to an electrode of the semiconductor element.

[実施例] 第1図は本発明に係る半導体装置の製造方法の実施例を
説明するための模式図である。なお、1はポリイミドフ
ィルムの如き絶縁フィルム(以下単にフィルムという)
で、実施例では厚さ25囲のものを使用した。このフィ
ルム1には両側にスプロケット穴5が設けられているが
、第2図の従来例に示したようなデバイスホール2やフ
ィンガー3aは形成されていない。以下、図面により本
発明の製造方法の一例を説明する。
[Example] FIG. 1 is a schematic diagram for explaining an example of the method for manufacturing a semiconductor device according to the present invention. In addition, 1 is an insulating film such as a polyimide film (hereinafter simply referred to as a film)
In the example, a material having a thickness of 25 cm was used. Sprocket holes 5 are provided on both sides of this film 1, but device holes 2 and fingers 3a as shown in the conventional example of FIG. 2 are not formed. Hereinafter, an example of the manufacturing method of the present invention will be explained with reference to the drawings.

(1) (a)図に示すようにフィルム1の表面(第2
図の幅Wの範囲)にフォトレジスト2oを塗布し、下面
に接着する半導体素子6の各電極7に対応した部分(d
図参照)をそれぞれ除去してレジストマスクを形成する
。また、裏面に接着剤22(実施例では厚さ5−)を塗
布する。
(1) (a) As shown in the figure, the surface of film 1 (second
A photoresist 2o is applied to the area (width W in the figure), and the area corresponding to each electrode 7 of the semiconductor element 6 (d
(see figure) are removed to form a resist mask. Further, an adhesive 22 (thickness 5- in the example) is applied to the back surface.

(2〉次に、(b)図に示すようにフォトレジスト2゜
を除去した部分のフィルム1及び接着剤22をエツチン
グして貫通穴23を形成する。
(2) Next, as shown in Figure (b), the film 1 and adhesive 22 are etched in the area where the photoresist 2° has been removed to form a through hole 23.

(3) (c)図に示すように、フィルム1の表面に塗
布したフォトレジスト20を除去する。
(3) (c) As shown in the figure, the photoresist 20 applied to the surface of the film 1 is removed.

(4) (d)図に示すように、半導体素子6の各電極
7を各貫通穴23と対向させてフィルム1の裏面に半導
体素子6を接着する。
(4) (d) As shown in the figure, the semiconductor element 6 is adhered to the back surface of the film 1 with each electrode 7 of the semiconductor element 6 facing each through hole 23.

(5) (e)図に示すように、フィルム1の表面及び
貫通穴23の内表面に例えばクロム(Cr )を蒸着し
て金属皮膜24(実施例では厚さ0.2−)を形成する
。このとき、貫通穴23内においては、半導体素子6の
電極7の表面にも金属皮膜24が形成される。
(5) (e) As shown in the figure, for example, chromium (Cr) is vapor-deposited on the surface of the film 1 and the inner surface of the through hole 23 to form a metal film 24 (thickness 0.2 - in the example). . At this time, a metal film 24 is also formed on the surface of the electrode 7 of the semiconductor element 6 in the through hole 23 .

(8) (f’)図に示すように導電パターンを形成す
る部分及び貫通穴23を除く部分にフォトレジスト25
を塗布しく実施例では厚さl〇−又はそれ以上)、レジ
ストマスクを形成する。
(8) (f') As shown in the figure, photoresist 25 is applied to the part where the conductive pattern is to be formed and the part excluding the through hole 23.
In the embodiment, the resist mask is coated to a thickness of l〇- or more).

(7) (g)図に示すように、フォトレジスト25が
塗布されていない部分及び貫通穴23の金属皮膜24上
に例えば金(Au )の如き導電材料をメツキし、導電
パターン26を形成する。これにより、半導体素子6の
各電極7は金属皮膜23を介してそれぞれ導電パターン
2Bに接続される。
(7) (g) As shown in the figure, a conductive material such as gold (Au) is plated on the parts where the photoresist 25 is not applied and on the metal film 24 of the through hole 23 to form a conductive pattern 26. . Thereby, each electrode 7 of the semiconductor element 6 is connected to the conductive pattern 2B via the metal film 23.

(8)最後に、(h)図に示すように、導電パターン2
6以外の部分のフォトレジスト25及び金属皮膜24を
エツチングにより除去する。
(8) Finally, (h) as shown in the figure, the conductive pattern 2
The photoresist 25 and metal film 24 other than the portions 6 are removed by etching.

上記のようにして半導体素子6が実装されたフィルム1
は、適宜長さの導電パターン28の範囲で切断され、半
導体装置が製造される。
Film 1 on which semiconductor element 6 is mounted as described above
is cut within the range of the conductive pattern 28 having an appropriate length, and a semiconductor device is manufactured.

なお、本発明は、第2図に従来例として示した長尺状の
絶縁フィルムを使用した半導体装置についても適用する
ことができる。
Note that the present invention can also be applied to a semiconductor device using a long insulating film shown as a conventional example in FIG.

以上本発明に係る半導体装置の製造方法の実施例につい
て説明したが、本発明はこれに限定するものではなく、
本発明の要旨を逸脱しない範囲で適宜変更することがで
きる。
Although the embodiments of the method for manufacturing a semiconductor device according to the present invention have been described above, the present invention is not limited thereto.
Appropriate changes can be made without departing from the gist of the invention.

[発明の効果] 以上の説明から明らかなように、本発明はボンディング
ツール等を使用することなく、絶縁フィルムの一方の面
に半導体素子を接着し、絶縁フィルムの他方の面に形成
した導電パターンと半導体素子の電極とを絶縁フィルム
に設けた貫通穴を介して接続するようにしたので、次の
ような顕著な効果を得ることができる。
[Effects of the Invention] As is clear from the above description, the present invention is capable of bonding a semiconductor element to one surface of an insulating film and forming a conductive pattern on the other surface of the insulating film without using a bonding tool or the like. Since the electrodes of the semiconductor element are connected to the electrodes of the semiconductor element through the through holes provided in the insulating film, the following remarkable effects can be obtained.

(1)半導体素子は絶縁フィルムに接着されているので
、従来装置のようにオーバーハング部分が存在しない。
(1) Since the semiconductor element is bonded to the insulating film, there is no overhanging portion unlike in conventional devices.

このため強度が大で導電パターンをさらに細密化するこ
とができる。
Therefore, the strength is high and the conductive pattern can be further made finer.

(2)ボンディングツールを使用しないので、電極が能
動面に設けられている半導体素子でも絶縁フィルムに実
装することができる。
(2) Since no bonding tool is used, even semiconductor elements with electrodes provided on the active surface can be mounted on the insulating film.

(3)実装時に熱的、機械的ストレスが加わらないので
半導体素子にクラックが発生するおそれがなく、歩留り
が大幅に向上する。
(3) Since no thermal or mechanical stress is applied during mounting, there is no risk of cracks occurring in the semiconductor element, and the yield is significantly improved.

(4)ボンディングツールを使用しないので製造設備が
簡単になり、製造も容易である。
(4) Since no bonding tools are used, manufacturing equipment is simple and manufacturing is easy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(h)は本発明に係る製造方法の実施例
を示す説明図、第2図は絶縁フィルムを使用した従来の
半導体装置の製造例を示す平面図、第3図はそのA−A
拡大断面図、第4図はフィンガーと電極とのボンディン
グの一例を示す模式図である。 1:絶縁フィルム、6:半導体素子、7:電極、22: 接着剤、 23: 貫通穴、 24: 金属皮膜、 26: 導 電パターン。
FIGS. 1(a) to (h) are explanatory diagrams showing an example of the manufacturing method according to the present invention, FIG. 2 is a plan view showing an example of manufacturing a conventional semiconductor device using an insulating film, and FIG. Its A-A
The enlarged sectional view and FIG. 4 are schematic diagrams showing an example of bonding between fingers and electrodes. 1: Insulating film, 6: Semiconductor element, 7: Electrode, 22: Adhesive, 23: Through hole, 24: Metal film, 26: Conductive pattern.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体素子の各電極に対応して貫通穴が設けられ
た絶縁フィルムの一方の面に前記半導体素子の能動面を
接着し、前記絶縁フィルムの他方の面に形成された導電
パターンと前記半導体素子の電極とを前記貫通穴を介し
てそれぞれ接続してなる半導体装置。
(1) The active surface of the semiconductor element is adhered to one side of an insulating film in which through holes are provided corresponding to each electrode of the semiconductor element, and the conductive pattern formed on the other side of the insulating film and the A semiconductor device in which electrodes of a semiconductor element are connected to each other through the through holes.
(2)絶縁フィルムの半導体素子の各電極に対応した位
置にそれぞれ貫通穴を設けると共に、該絶縁フィルムの
一方の面又は半導体素子の能動面に接着剤を塗布し、前
記半導体素子をその各電極を前記貫通穴にそれぞれ対向
させて前記絶縁フィルムに接着し、ついで前記絶縁フィ
ルムの他方の面及び前記貫通穴に金属皮膜を形成して前
記他方の面の金属皮膜上に前記各貫通穴の底部に達する
導電パターンを形成し、該導電パターンと前記半導体素
子の電極とを接続してなる半導体装置の製造方法。
(2) Provide through holes in the insulating film at positions corresponding to each electrode of the semiconductor element, apply adhesive to one surface of the insulating film or the active surface of the semiconductor element, and attach the semiconductor element to each electrode of the insulating film. are bonded to the insulating film so as to face each of the through holes, and then a metal coating is formed on the other surface of the insulating film and the through holes, so that the bottom of each of the through holes is coated on the metal coating on the other surface. 1. A method for manufacturing a semiconductor device, comprising forming a conductive pattern reaching up to 100 m, and connecting the conductive pattern to an electrode of the semiconductor element.
JP1196844A 1989-07-31 1989-07-31 Semiconductor device and manufacture thereof Pending JPH0362542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1196844A JPH0362542A (en) 1989-07-31 1989-07-31 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1196844A JPH0362542A (en) 1989-07-31 1989-07-31 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0362542A true JPH0362542A (en) 1991-03-18

Family

ID=16364603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1196844A Pending JPH0362542A (en) 1989-07-31 1989-07-31 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0362542A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298043A (en) * 2000-02-08 2001-10-26 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2003318234A (en) * 2002-02-25 2003-11-07 Sony Corp Electronic component and method of manufacturing electronic component
JP2011526422A (en) * 2008-07-02 2011-10-06 シーメンス アクチエンゲゼルシヤフト Planar power electronic component for use at high temperatures and method of manufacturing the same
JP2012256631A (en) * 2011-06-07 2012-12-27 Toshiba Corp Semiconductor device and manufacturing method of the same
WO2013027718A1 (en) * 2011-08-23 2013-02-28 株式会社フジクラ Component-mounting printed circuit board and manufacturing method for same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298043A (en) * 2000-02-08 2001-10-26 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP2003318234A (en) * 2002-02-25 2003-11-07 Sony Corp Electronic component and method of manufacturing electronic component
JP2011526422A (en) * 2008-07-02 2011-10-06 シーメンス アクチエンゲゼルシヤフト Planar power electronic component for use at high temperatures and method of manufacturing the same
JP2012256631A (en) * 2011-06-07 2012-12-27 Toshiba Corp Semiconductor device and manufacturing method of the same
US8786077B2 (en) 2011-06-07 2014-07-22 Kabushiki Kaisha Toshiba Semiconductor device having a first substrate containing circuit element connected to radiation plate on a cover plate with metal vias
WO2013027718A1 (en) * 2011-08-23 2013-02-28 株式会社フジクラ Component-mounting printed circuit board and manufacturing method for same

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