JPH0362553A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized in a building block type or master slice type semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit in which the layout design of a circuit that handles analog signals is improved.

〔overview〕

The present invention provides a building block type or master slice type semiconductor integrated circuit comprising a plurality of pads and input/output circuit blocks arranged around a chip, and at least one circuit block arranged in an internal area of the chip. , by providing a relay block having electrically equivalent input terminals and output terminals for relaying wiring between the circuit block and the pad or the input/output circuit block, the circuit can be connected during automatic wiring design. This enables wiring between blocks and the relay block, shortens the wiring and prevents overlapping of the wiring of a plurality of circuit blocks, shortens the design and development period, and improves characteristics.

[Conventional technology]

In semiconductor integrated circuits of the building block type or the master slice type, recently, in order to achieve a short development period, the layout and wiring of internal circuits are automatically performed using a computer or the like. Under such circumstances, the wiring between circuit functional blocks and the wiring between blocks and pads for taking out power and signal lines around the semiconductor chip on which those circuits are mounted differ depending on the individual integrated circuit, and are difficult to maintain. This often results in redundant and unreasonable wiring. These redundant wiring places an extra load on the signal line, which causes a delay in the propagation of the signal itself. Although digital circuits affect the delay value of each signal line, this problem can be avoided by taking this into consideration in advance when designing.

On the other hand, in a semiconductor integrated circuit including an analog block, such redundant and unreasonable wiring can be said to be extremely disadvantageous because it causes deterioration of the characteristics of the analog block and crosstalk from digital signals.

For example, as shown in FIG. 5 as a first conventional example, R
Reference voltage input terminal 4 of string type DA converter 3
If the wiring 6 between the pads 8 and 5 and the pads 8 and 9 becomes unnecessarily long, the influence of the wiring resistance will cause deterioration in zero scale error and full scale error.

In addition, if there are multiple circuit blocks and their reference voltage input terminals are connected to a common pad, the sixth
When the wiring is as shown in the second conventional example in the figure, a-b
The wiring between the reference voltage input terminals 4. ．． 4b, 4c, 5. ．． 5. Since the sum of the currents flowing into 5c and 5c flows, the voltage drop becomes extremely large, leading to an increase in zero-scale error and full-scale error.

However, if such wiring is manually changed to the shortest and most optimal wiring, the development period will inevitably increase, and it can be said that this is virtually impossible for semi-custom LSIs such as gate arrays, which have the greatest advantage of short development periods.

[Problem that the invention seeks to solve]

As described above, the conventional layout design of analog blocks in semiconductor integrated circuits using the building block method or the master slice method has problems such as deterioration of characteristics due to redundant and unreasonable wiring caused by automatic placement and wiring.

The purpose of the present invention is to solve the above-mentioned problems.
It is an object of the present invention to provide a semiconductor integrated circuit in which layout design of analog blocks can be performed without redundant wiring and characteristics can be improved.

[Means for solving problems]

The present invention provides a semiconductor integrated circuit including a plurality of pads and input/output circuit blocks arranged around a chip, and at least one circuit block arranged in an internal area of the chip. At least one relay block is provided, which has input terminals and output terminals that are equivalent in terms of input and output terminals, and serves as an intermediate connection point for wiring connecting internal terminals of the circuit block and the pad or the input/output circuit block. shall be.

[Effect]

The relay block is provided between the pad or the input/output circuit block and the circuit block in the internal area, and has electrically equivalent input terminals and output terminals. This results in
During automatic wiring design, an internal terminal of the circuit block is connected to an output terminal of the relay block, and its input terminal is connected to the pad or input/output circuit block. In this case, by appropriately setting the arrangement position of the relay block, the wiring can be made short without any redundant parts. Furthermore, when there are a plurality of circuit blocks, by using the relay block as a single-manpower multi-output terminal, the wiring to each circuit block can be separated and wired without being overlapped.

Therefore, it is possible to automatically design an appropriate wiring without trial and error, shorten the development period, and improve characteristics such as error reduction by shortening the wiring and preventing overlapping wiring.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic layout diagram showing a main part of a first embodiment of the present invention, and FIG. 2 is an explanatory diagram showing an example of a relay block thereof.

In this practical example, a plurality of pads 2 arranged around a chip 1 and serving as external connection terminals, and a DA converter 3 of a J song and n bits are arranged in an internal area of the chip 1.
A semiconductor integrated circuit comprising an input terminal 10 and an output terminal 11, a high level reference voltage input terminal 4 and a low level reference voltage input terminal 5 of the DA converter 3, which is a feature of the present invention. and,
It includes two relay blocks 7 that serve as intermediate connection points for wiring 6 that connects pads 8 and 9, respectively. Here, the input terminal 10 and the output terminal 11 of the relay block 7 are connected by a wiring 6.

Since the relay block 7 has its own input terminal 10 and output terminal 11 that are electrically equivalent, it is electrically no different from a single wire, but this relay block is specified in the circuit connection information. By connecting it to the reference voltage input terminals 4 and 5 of the DA converter 3, it functions extremely effectively at the stage of automatic placement and wiring processing. In other words, this relay block 7 is connected to pads 8 and 9 and the DA converter 3.
Redundant and irrational wiring, which is extremely disadvantageous for analog signal systems, can be eliminated by forcibly placing it near the middle between reference voltage input terminals 4 and 5, or at an optimal position that takes into account the nature of the automatic wiring program. .

Now, assume that the DA converter 3 is an 8-bit DA converter, and the unit resistance value of the RS/IJ ring section is 200Ω. Assuming that the resistance value per 1 mm of the wiring 6 is 40Ω, in a conventional layout that does not use a relay block as shown in the first conventional example in FIG. The wiring lengths between the reference voltage input terminal 9 and the reference voltage input terminal 5 are 2 mm and 2.5+ nm, respectively, resulting in significant characteristic deterioration.

On the other hand, in a layout where redundant wiring is eliminated by using the relay block 7 as shown in FIG.
The respective wiring lengths mentioned above are shortened to 0.5 mm and 1 mm, which makes it possible to significantly suppress characteristic deterioration.

FIG. 3 is a schematic layout diagram showing the main parts of the second embodiment of the present invention, and FIG. 4 is an explanatory diagram showing an example of the relay block 7a.

In the second embodiment, three Rs) IJ type upper bit DA converters 3a, 3b and 3C have respective high level and low level reference voltage input terminals 4a,
4b and 4cs and 5a, 5b and 5C are respectively connected to common pads 8 and 9 (or external output block) via a relay block 7a, which is a feature of the present invention.

Since the input terminals 10 and output terminals 11 of this relay block 7a are all electrically equivalent, it is the same as simple wiring of 3 outputs by one person, but this relay block 7a is connected to the three DA converters in the circuit connection information. 3a13
By connecting it to the high level and low level reference voltage input terminals 4a, 4b, 4c, 5a, 5b and 5c of the terminals b and 3c, it functions extremely effectively at the stage of automatic placement and wiring processing. In other words, this relay block 7a
pads 8 and 9 (or outside person block)
three DA converters 3a by placing them near.

The wiring path between a-b and a'-b' in FIG. 6, through which the sum of the currents flowing through the R-stack 9-f of parts 3b and 3c, can be made extremely short.

Now, assume that the DA converters 3a, 3b, and 3C are 8-bit DA converters, and the unit resistance value of the R string section is 200Ω. And the resistance value of 1 mm of wiring is 40
Ω, in a conventional layout that does not use a relay block as shown in the second conventional example in Fig. 6, the paths through which the total current flows between a and b and between a and b extend redundantly and become 2 mm and 2 mm, respectively. 2.5 mm, the DA converter 3a whose reference voltage input terminals 4a and 5a are closest to points b and 62 has extremely poor characteristics as follows.

On the other hand, in a layout where the path through which the total current flows is sufficiently reduced by using the relay block 7a as in the second embodiment shown in FIG.
, 3b and 3C reference voltage input terminals 4a, 4b
, 4c, 5a, 5b, and 5C, this will cause a change in the characteristics of the long wiring bones, but since the current flowing there is one R string, the influence will be small. Regarding one DA converter 3a, 3b or 3C, its high level and low level reference voltage input terminals 4a, 4b and 4
When the wiring lengths between C, 5a, 5b, and 5C and the relay block are respectively 2 mm and 2.5 mm, it can be seen that even if the wiring lengths are the same as in the case of FIG. 6, the characteristic deterioration is significantly reduced.

Although the above description has mainly focused on the connection between the pad and the circuit block, the same applies to the connection with an external input/output circuit block instead of the pad.

〔Effect of the invention〕

As explained above, the present invention provides a semiconductor integrated circuit of a building block type or a master slice type, which includes an analog circuit block and a relay block that serves as a relay connected to an analog signal system terminal of the analog circuit block. , the wiring between the analog signal system terminal of the analog circuit block and the chip peripheral pad (or external output block) or between other blocks can be made close to ideal even in automatic wiring, and the analog/digital This has the effect of solving the contradictory issues of improving the performance of embedded LSIs and shortening the design period all at once.

[Brief explanation of drawings]

FIG. 1 is a schematic layout diagram showing the main parts of a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing an example of the relay block. FIG. 3 is a schematic layout diagram showing the main parts of a second embodiment of the present invention. FIG. 4 is an explanatory diagram showing an example of the relay block. FIG. 5 is a schematic layout diagram showing the main parts of the first conventional example of the present invention. FIG. 6 is a schematic layout diagram showing the main parts of a second conventional example of the present invention. 1... Chip, 2.8.9... Pad, 3.3a~
3C-DA: 7 inverters, 4.4a to 4c, 5.5
a~5C... Reference voltage input terminal, 6... Wiring, 7.
7a... Relay block, 10... Input terminal, 11.
...Output terminal. ( Hiroshi Nakatsuki) "Rock) Ko, Kaku 52" [Crime example (relay allotsuku) 1: + rough 2.8, 9: No, ad 3, 3a, 3b, 3c: OA converter Ko - conventional example M 5 En, a, 4b. , a, 5b1: 2nd conventional example 6 mouths

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising a plurality of pads and input/output circuit blocks arranged around a chip, and at least one circuit block arranged in an internal area of the chip, comprising: at least one relay block having two electrically equivalent input terminals and output terminals, and serving as an intermediate connection point of wiring connecting the internal terminal of the circuit block and the pad or the input/output circuit block; A semiconductor integrated circuit characterized by: