JPH0362731A - Intermittent operation pll circuit - Google Patents
Intermittent operation pll circuitInfo
- Publication number
- JPH0362731A JPH0362731A JP1198508A JP19850889A JPH0362731A JP H0362731 A JPH0362731 A JP H0362731A JP 1198508 A JP1198508 A JP 1198508A JP 19850889 A JP19850889 A JP 19850889A JP H0362731 A JPH0362731 A JP H0362731A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase difference
- intermittent operation
- switch
- pll circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は低消費電力化を図る為に用いられる間欠動作
P L L (Phase Looked Loop
)Ill路に関するものである〇
〔従来の技術〕
第2図は従来の間欠動作を行なうPL、L回路のブロッ
ク図である。図において、1及び11はPLL回路を動
作させる電源電圧供給端子で、lはPLL回路の基準信
号発振器4.固定分周器5.可変分周器61位相比較器
1に電源電圧を供給する端子、11はループフィルタ8
及びV OO(Voltag@ 0ontrO1led
0scillator電圧制御発振器)に電源電圧を
供給する端子である。2は間欠動作を行なわせる為のス
イッチ回路、3はスイッチのON、 OFFを制御する
スイッチ制御回路、4は基準信号発振器、5は基準信号
発振器乙の基準信号を分周する為の固定分周器、6は9
より発生した発振周波数を分周する為の可変分周器であ
る07は5の固定分周器により分周された信号と6の可
変分周器によう分局された信号の位相を比較する為の位
相比較器である08は7より出力された位相差を電圧に
変換する為のループフィルタである。工Oは8のループ
フィルタの電圧を2の制御スイッチがOFFの時間保持
する為のコンデンサ である。[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to an intermittent operation PLL (Phase Looked Loop) used to reduce power consumption.
)Ill path〇 [Prior art] Fig. 2 is a block diagram of a conventional PL and L circuit that performs intermittent operation. In the figure, 1 and 11 are power supply voltage supply terminals for operating the PLL circuit, and 1 is a reference signal oscillator 4.1 of the PLL circuit. Fixed frequency divider5. Variable frequency divider 61 Terminal for supplying power supply voltage to phase comparator 1, 11 is loop filter 8
and V OO (Voltag@0ontrO1led
This is a terminal that supplies the power supply voltage to the oscillator (voltage controlled oscillator). 2 is a switch circuit for intermittent operation, 3 is a switch control circuit that controls ON/OFF of the switch, 4 is a reference signal oscillator, and 5 is a fixed frequency divider for dividing the reference signal of reference signal oscillator B. vessel, 6 is 9
07, which is a variable frequency divider for dividing the oscillation frequency generated by the oscillation frequency, is used to compare the phase of the signal divided by the fixed frequency divider 5 and the signal divided by the variable frequency divider 6. The phase comparator 08 is a loop filter for converting the phase difference output from 7 into a voltage. The capacitor O is used to hold the voltage of the loop filter 8 while the control switch 2 is OFF.
次に動作について説明する。このPLL回路は9のVO
Oの出力周波数を安定させることを目的としている。4
の基準信号発振器により発生した信号を固定分周器5で
分周し、この分周された信号を基準とし、この基準信号
と6の可変分周器の出力信号が同位相となる様構成され
ている。もしもこの5の出力信号と6の出力信号に位相
差があればその位相差を7の位相比較器に出力し、8の
ループフ、イルタにより位相差が電圧変換され、その変
換された電圧が9のWOOに印加される。この電圧の変
動により9の出力周波数が変わり6の可変分周器へ入力
され、この入力された信号は可変分周器6により分周さ
れ、位相比較器7へ入力される。以下、固定分周器5お
よび位相比較器プのそれぞれの出力信号が同位相となる
までこの動作は繰り返される。Next, the operation will be explained. This PLL circuit has 9 VO
The purpose is to stabilize the output frequency of O. 4
A fixed frequency divider 5 divides the signal generated by the reference signal oscillator 5, and this frequency-divided signal is used as a reference, and the reference signal and the output signal of the variable frequency divider 6 are configured to be in the same phase. ing. If there is a phase difference between the output signal of 5 and the output signal of 6, that phase difference is output to the phase comparator of 7, the phase difference is converted into a voltage by the loop filter and filter of 8, and the converted voltage is converted into a voltage of 9. is applied to WOO. Due to this voltage variation, the output frequency of 9 changes and is input to the variable frequency divider 6, and this input signal is frequency-divided by the variable frequency divider 6 and input to the phase comparator 7. Thereafter, this operation is repeated until the output signals of the fixed frequency divider 5 and the phase comparator P have the same phase.
この従来のPLL回路は以上に述べた様な動作を行なう
と同時に、低消費電力化を図る為間欠動作を行なう回路
も備えていた。この間欠動作とはPLL回路に供給され
る電源電圧をある一定時間0IFFすることによ勺低消
費電力化を図っている0この電源電圧の0N10FF
の制御はスイッチ制御回路3によって行なわれる。ス
イッチ回82がONの時のみ上記のPLL動作が行なわ
れ、OF]7′状態の時PLLは動作しない。This conventional PLL circuit not only operates as described above, but also includes a circuit that performs intermittent operation in order to reduce power consumption. This intermittent operation is intended to reduce power consumption by reducing the power supply voltage supplied to the PLL circuit to 0IFF for a certain period of time.
The control is performed by the switch control circuit 3. The PLL operation described above is performed only when the switch circuit 82 is ON, and the PLL does not operate when the switch circuit 82 is in the ON state.
従来のPLL回路は以上のように構成されていたので、
スイッチ制御回路の制御をある一定時間0IFFにし、
ある一定時間○’FF状態にするといった様にクイナミ
ンクに0N10FF 動作を行々う必要があり、この為
スイッチ回路が0IFFの時にはPLJ、回路が動作せ
ずVOOが非常に不安定な状態になるという問題点があ
った。Since the conventional PLL circuit was configured as above,
Control the switch control circuit to 0IFF for a certain period of time,
It is necessary to perform 0N10FF operation on Quinaminku, such as keeping it in the FF state for a certain period of time, and for this reason, when the switch circuit is 0IFF, the PLJ and circuit do not operate and VOO becomes extremely unstable. There was a problem.
この発明は上記のような問題点を解消する為になされた
もので、位相比較器の出力信号を検出することによりス
イッチ制御@回路を制御することを目的とする。This invention was made to solve the above-mentioned problems, and its object is to control a switch control @ circuit by detecting the output signal of a phase comparator.
この発明に係る間欠動作PLL回路は、固定分周器の出
力信号と可変分周器の出力信号の位相差がある一定の許
容範囲内の差であればスイッチ制御回路はONの佑゛号
を出力する様にしたものである0
〔作用〕
この発明に釦ける間欠動作PLL回路は、VOOの周波
数が安定していれば電源電圧をoIPIFシ、筐たWO
Oの周波数のずれが発生した時点で電源電圧をONにす
るといったフィードバック機能を備えたPLL動作を行
なう。In the intermittent operation PLL circuit according to the present invention, if the phase difference between the output signal of the fixed frequency divider and the output signal of the variable frequency divider is within a certain tolerance range, the switch control circuit turns on the ON signal. [Function] The intermittent operation PLL circuit according to the present invention changes the power supply voltage to the oIPIF and the WO
A PLL operation is performed with a feedback function such as turning on the power supply voltage when a shift in the frequency of O occurs.
以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図はこの発明の一実施例による間欠動作pLb回路
のブロック図を示し、図中、前記従来のものと同一符号
は同一のものを示す。図において、12は位相差検出回
路で、位相比較器7の位相差を検出し、位相差がある一
定の許容範囲内の値であれはスイッチ制御回路3にスイ
ッチ回路2が0IFFとなる様な命令を送る為の信号を
出力し、また逆に、位相比較器7の位相差がある一定の
許容範囲以上であれは、スイッチ制御回路3にスイッチ
回路2がONとZる様な命令を送る為の信号を出力する
。これにより、VOO9の周波数が安定した時に電源電
圧端子lは0IPF状態となり、v009の周波数が基
準信号に対して位相差を生じた時に電源電圧端子lがO
Nするといった位相差によるフィードバック機能を備え
た間欠動作PLL回路を得ることができる。FIG. 1 shows a block diagram of an intermittent operation pLb circuit according to an embodiment of the present invention, and in the figure, the same reference numerals as in the conventional circuit denote the same parts. In the figure, 12 is a phase difference detection circuit that detects the phase difference of the phase comparator 7, and if the phase difference is within a certain tolerance range, the switch control circuit 3 is configured so that the switch circuit 2 becomes 0IFF. It outputs a signal to send a command, and conversely, if the phase difference of the phase comparator 7 is above a certain tolerance range, it sends a command to the switch control circuit 3 to turn the switch circuit 2 ON and Z. Outputs a signal for As a result, when the frequency of VOO9 is stabilized, the power supply voltage terminal l is in the 0IPF state, and when the frequency of v009 has a phase difference with respect to the reference signal, the power supply voltage terminal l is in the 0IPF state.
An intermittent operation PLL circuit having a feedback function based on a phase difference such as N can be obtained.
以上のようにこの発明によれば、位相比較器の位相差を
検出することにより間欠動作を行なわせるといったフィ
ードバック機能を備えたので、より安定した間欠動作P
LL回路を得ることができる0As described above, according to the present invention, since a feedback function is provided to perform intermittent operation by detecting the phase difference of the phase comparator, more stable intermittent operation P
0 which can obtain LL circuit
第1図はこの発明の一実施例による間欠動作PLL回路
を示すブロック図、第2図は従来の間欠動作PLL回路
を示すブロック図である。
図において、1は電源電圧端子、2はスイッチ回路、3
はスイッチ制御回路、4は基準信号発生器、5は固定分
周器、6は可動分周器、7は位相比較器、12は位相差
検出回路を示す。
なお、図中、同一符号は同一 または相当部分を示す○FIG. 1 is a block diagram showing an intermittent operation PLL circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional intermittent operation PLL circuit. In the figure, 1 is a power supply voltage terminal, 2 is a switch circuit, and 3 is a power supply voltage terminal.
4 is a switch control circuit, 4 is a reference signal generator, 5 is a fixed frequency divider, 6 is a movable frequency divider, 7 is a phase comparator, and 12 is a phase difference detection circuit. In addition, in the figures, the same symbols indicate the same or equivalent parts○
Claims (1)
器で構成されるPLL回路において、それぞれの電源電
圧端子とこの電源電圧端子に電源電圧を供給する為の電
源電圧供給端子との間に間欠動作を行なわせるスイッチ
回路と、このスイッチ回路のスイッチのON、OFFを
行なわせるスイッチ制御回路と、このスイッチ制御回路
を位相比較器の出力信号により発生する位相差検出回路
を備えたことを特徴とする間欠動作PLL回路。In a PLL circuit consisting of a reference signal oscillator, fixed frequency divider, phase comparator, and variable frequency divider, between each power supply voltage terminal and the power supply voltage supply terminal for supplying the power supply voltage to this power supply voltage terminal. A switch circuit that performs intermittent operation, a switch control circuit that turns on and off the switch of this switch circuit, and a phase difference detection circuit that generates the switch control circuit using the output signal of a phase comparator. Features an intermittent operation PLL circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1198508A JPH0362731A (en) | 1989-07-31 | 1989-07-31 | Intermittent operation pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1198508A JPH0362731A (en) | 1989-07-31 | 1989-07-31 | Intermittent operation pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0362731A true JPH0362731A (en) | 1991-03-18 |
Family
ID=16392304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1198508A Pending JPH0362731A (en) | 1989-07-31 | 1989-07-31 | Intermittent operation pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0362731A (en) |
-
1989
- 1989-07-31 JP JP1198508A patent/JPH0362731A/en active Pending
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