JPH0362732A - Synchronizing signal level detector and pedestal level detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention detects the synchronization signal level of a video signal, such as a high-definition signal, in a VTR or the like, which has a multi-level waveform synchronization signal with both positive and negative polarities. The present invention relates to a device and a device for detecting the pedestal level of a video signal having a negative polarity synchronization signal such as an NTSC signal, or a video signal having a multi-level waveform synchronization signal of both positive and negative polarity such as a Hi-Vigilon signal. It is something.

2. Description of the Related Art Generally, a synchronizing signal level detecting device and a pedestal level detecting device are constructed using analog circuits.
When digitally processing a video signal, level detection is often performed after the video signal is analog-to-digital converted as shown in FIG.

Problem to be Solved by the Invention However, in the above conventional configuration, the video signal I having a negative polarity synchronization signal as shown in FIG.
When the synchronization signal level is detected by the synchronization signal level detection circuit 25 after analog-to-digital conversion,
As shown in FIG. 10, it is necessary to perform analog-to-digital conversion by including all the negative synchronizing signals, but in this case, it is not possible to obtain a large range in the actual video signal part, and the analog-to-digital conversion circuit 3 There was a problem that the S/N ratio decreased. Therefore, if the negative polarity sync signal is separated and only the negative polarity sync signal is converted from analog to digital to detect the sync signal level, while only the video signal portion is converted from analog to digital, a large dynamic range can be obtained. Since two D converters are required, there is a problem in that the circuit scale becomes large.

Furthermore, in the pedestal level detection circuit 24, it has conventionally been common to detect the pedestal level after analog-to-digital conversion including all negative polarity synchronization signals. In this case, even though it is not necessary to convert all parts of the negative polarity synchronizing signal into analog-to-digital, all parts are converted into analog-to-digital, which causes deterioration of the S/N ratio in the analog-to-digital conversion part.

Means for Solving the Problems In order to solve the above problems, the synchronization signal level detection device of the present invention includes an amplification means for amplifying the gain of a video signal, and an output of the amplification means for converting most of the negative polarity synchronization signal. an A/D conversion circuit that performs analog-to-digital conversion, a synchronization signal separation circuit that separates a synchronization signal from the video signal, and a timing generation circuit that generates one or more pulses from the output of the synchronization signal separation circuit. The synchronizing signal amplitude level detection circuit detects the position of the synchronizing signal by the pulse of the synchronizing signal, and detects the synchronizing signal amplitude level from the output of the A/D conversion circuit.

The bedscale level detection device of the present invention further includes an amplification means for amplifying the gain of the video signal, and an A/D conversion circuit for converting the output of the amplification means into analog and digital data except for most of the negative polarity synchronization signal. , a sync signal separation circuit that separates a sync signal from the video signal, a timing generation circuit that generates one pulse from the output of the sync signal separation circuit, and a pedestal level position detected by the pulse from the timing generation circuit; The device has a configuration including a pedestal level detection circuit that detects a pedestal level from the output of the A/D conversion circuit.

Operation With the above configuration, the input dynamic range of the A/D converter circuit can always be utilized to the maximum during analog-to-digital conversion to perform analog-to-digital conversion of video signals, and S/N
It becomes possible to greatly improve the ratio.

Embodiment Hereinafter, a synchronizing signal level detection device of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the synchronization signal level detection device of the present invention. The video signal 1 is amplified by the amplifying means 2. The output of the amplification means 2 is converted into an analog/digital signal by an A/D conversion circuit 3. At this time, as shown in FIG. 6, analog-to-digital conversion is performed except for most of the negative synchronization signal. The synchronization signal is separated by a synchronization signal separation circuit 4, a timing generation circuit 5 generates timing for detecting the synchronization signal level, and a synchronization signal amplitude level detection circuit 6 detects the amplitude level of the positive polarity synchronization signal. . Based on the detection result, the gain of the amplification means 2 is adjusted and the dynamic range of the input signal to the A/D conversion circuit is expanded by the amount excluding the negative polarity synchronization signal. The N ratio can be greatly improved.

Next, FIG. 2 shows the second synchronous signal level detection device of the present invention.
1 is a block diagram showing the configuration of an automatic gain control device using a synchronizing signal level detection device as an embodiment of the present invention. The amplification signal means 2 shown in FIG. /A conversion circuit 9, low pass filter 10.
It is composed of a control circuit 11. The video signal (2) is amplified by a variable gain amplifier circuit 7. The output of the variable gain amplifier circuit 7 is subjected to analog-to-digital conversion by the A/D conversion circuit 3.

At this time, as shown in FIG. 6, by removing most of the negative polarity synchronization signal and performing analog-to-digital conversion and detecting the amplitude level of the positive polarity synchronization signal, a feedback loop to the variable gain amplifier circuit 7 is established. Configure. The synchronization signal is extracted from the video signal I in the synchronization signal separation circuit 4, the timing generation circuit 5 creates a timing for detecting the synchronization signal amplitude level, and the synchronization signal amplitude level detection circuit 6 extracts the A/D converted video signal. Detect the amplitude level of the synchronization signal from The subtraction circuit 8 calculates the difference between the reference value and the synchronization signal amplitude level, and the output of the subtraction circuit 8 is the D/A
The conversion circuit 9 performs digital-to-analog conversion, and the low-pass filter 10 filters the signal. The control circuit 11 controls the gain of the variable gain amplifier circuit 7 based on the output of the low-pass filter (2)0. In this configuration, by controlling the dynamic range of the input signal to the A/D conversion circuit 3 to be maximized, the S/N ratio can be greatly improved in the A/D conversion circuit 3 portion.

Next, a bedscale level detection device according to the present invention will be explained with reference to the drawings.

FIG. 3 shows an embodiment of the bedscale level detection device of the present invention. The video signal 1 is amplified by the amplifying means 2. The output of the amplification means 2 is converted into an analog/digital signal by an A/D conversion circuit 3. At this time, as shown in Figure 6,
Analog-to-digital conversion is performed except for most of the negative polarity synchronization signal. The synchronization signal is extracted by the synchronization signal separation circuit 4, the timing generation circuit 12 generates a timing for detecting the pedestal level, and the pedestal level detection circuit (3) detects the pedestal level. Based on the detection result, the gain of the amplifying means 2 is adjusted, and the dynamic range of the input signal to the A/D converter circuit 3 is expanded by the amount excluding the negative polarity synchronizing signal, so that the A/D converter circuit 3 section can: The S/10-N ratio can be greatly improved.

FIG. 4 is a block diagram of a clamping device using a pedestal level detecting device as a second embodiment of the pedestal level detecting device, and the amplifying means 2 shown in FIG. , a D/A conversion circuit 16, a low-pass filter 17, a control circuit 18, and an amplifier circuit 26. The video signal 1 is amplified by an amplifier circuit 26. The output of the amplifier circuit 26 passes through the DC level shift circuit 14 and is converted into an analog/digital signal by the A/D conversion circuit 3. At this time, as shown in Fig. 6, most of the negative polarity synchronization signal is removed and analog-digital conversion is performed.
By detecting the pedestal level, a feedback loop to the DC level shift circuit 14 is configured.

The synchronization signal is extracted from the video signal 1 in the synchronization signal separation circuit 4, the timing generation circuit I2 creates timing for detecting the pedestal level, and the pedestal level detection circuit 13 extracts the A/D converted video signal. Detect the pedestal level from. The subtraction circuit 1511- calculates the difference between the reference value and the pedestal level, and the output of the subtraction circuit 15 is digital-to-analog converted by the D/A conversion circuit 16 and filtered by the low-pass filter 17. The control circuit 18 uses the output of the low-pass filter 17 to
Controls the DC Ray Igle shift circuit 14. the result,
The pedestal level of the output of the DC level shift circuit 14 is kept constant. In this configuration, most of the negative polarity synchronization signal is removed and analog-to-digital conversion is performed, so the gain in the preceding stage amplifier circuit 26 can be increased by the amount by which the negative polarity synchronization signal is removed, and the A/D conversion circuit 3 The dynamic range of the input signal can be expanded, and the A/D conversion circuit section can expand the dynamic range of the input signal to the
The S/N ratio can be greatly improved.

Next, an automatic gain control device and a clamp device will be described with reference to the drawings as an embodiment in which the synchronization signal level detection device and pedestal level detection device of the present invention are combined.

FIG. 5 is a lock diagram showing the configuration of an automatic gain control device and a clamp device according to an embodiment of the present invention. The video signal 1 is amplified by a variable gain amplifier circuit 7. The output of the variable gain amplifier circuit 7 passes through a DC level shift circuit 14 and is then converted into an analog-to-digital signal by an A/D conversion circuit 3. At this time, as shown in FIG. 6, analog-to-digital conversion is performed only on a portion excluding most of the negative polarity synchronizing signal.

The synchronization signal is extracted from the video signal as in the previous embodiment, and the timing generation circuit 19 generates the synchronization signal as shown in FIG.
A pulse indicating the position of the synchronization signal and the pedestal level is generated, the synchronization signal level detection circuit 20 and the pedestal level detection circuit 13 detect the synchronization signal level and the pedestal level, and the subtraction circuit 21 calculates the difference between the two. Then, a feedback loop to the variable gain amplifier circuit 7 is constructed in the same manner as in FIG. Further, the output of the pedestal level detection circuit 13 constitutes a feedback loop to the DC level shift circuit 14 as in FIG. 4. With this configuration, the amplitude level of the synchronizing signal can be detected accurately, and the dynamic range can be expanded to the maximum while keeping the pedestal level of the input signal to the A/D converter circuit 3 at a constant value. The S/N ratio can be greatly improved in this area. At the same time, by sharing a portion of the circuit, it is possible to reduce the circuit scale.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention eliminates the need for analog-to-digital conversion of a negative synchronization signal when converting a video signal from analog to digital, and also extracts the synchronization signal and converts it to a reference position before analog-to-digital conversion. Therefore, the position of the positive polarity synchronization signal and pedestal level can be accurately known.

The amplitude of the positive polarity synchronization signal can be detected accurately, and by adjusting the gain of the amplification means placed in the previous stage, the
The dynamic range of the input signal to the /D conversion circuit can be expanded.

Furthermore, in the pedestal level detection device, since most of the negative polarity synchronization signal is removed and A/D converted, the dynamic range can be expanded by the amount by which the negative polarity synchronization signal is removed by adjusting the gain of the front stage amplification means. Even in this manner, the pedestal level can be detected as a positive electrode. According to the present invention, it is possible to perform analog-to-digital conversion by always making maximum use of the input dynamic range of the A/D conversion circuit during analog-to-digital conversion, and it has become possible to greatly improve the -ff/N ratio.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the synchronization signal level detection device of the present invention, and FIG. 2 is a block diagram showing the configuration of an automatic gain control device which is a second embodiment of the synchronization signal level detection device. Fig. 3 is a block diagram showing an embodiment of the pedestal level detection device, Fig. 4 is a block diagram showing the configuration of a clamp device which is a second embodiment of the pedestal level detection device, and Fig. 5 is a synchronization signal level. 6 is a block diagram showing the configuration of an automatic gain control device and a clamp device, which are embodiments using a detection device and a pedestal level detection device.
10 and 10 are waveform diagrams showing the depression of analog-to-digital conversion, FIG. 7 is a waveform diagram showing the output of the timing generation circuit, and FIG. 8 is a conventional synchronization signal level detection device and pedestal level detection device 5-1. FIG. 9 is a waveform diagram showing an example of a video signal having synchronization signals of both positive and negative polarities. 1... Video signal, 2... Amplifying means, 3...
・A/D conversion circuit, 4... synchronous signal separation circuit,
5.12...Timing generation circuit, 6...Synchronizing signal amplitude level detection circuit, 7...Variable gain amplifier circuit, 8.15...Subtraction circuit, 9.16・D
/A conversion [, 10°17...low pass filter,
11... Control circuit, 13... Pedestal level detection circuit τ 14... DC level shift circuit, 26.
...Amplification circuit.

Claims (5)

[Claims] (1) an amplification means for amplifying the gain of the video signal; an A/D conversion circuit for converting the output of the amplification means into analog-to-digital data except for most of the negative polarity synchronization signal; and separating the synchronization signal from the video signal. a synchronization signal separation circuit; a timing generation circuit that generates one or more pulses from the output of the synchronization signal separation circuit; and a timing generation circuit that detects the position of the synchronization signal using the pulse from the timing generation circuit and performs the A/D conversion. 1. A synchronization signal level detection device comprising: a synchronization signal amplitude level detection circuit that detects a synchronization signal amplitude level from an output of the circuit. (2) The amplification means of the synchronization signal level detection device according to claim 1 includes: a variable gain amplifier circuit that controls the gain of the video signal input to the A/D conversion circuit; and the output and reference of the synchronization signal amplitude level detection circuit. a subtraction circuit that calculates the difference between the two values, and a D/A that converts the output of the subtraction circuit into digital and analog.
An automatic gain control device comprising: an A conversion circuit; a low-pass filter that filters the output of the D/A conversion circuit; and a control circuit that controls the gain of the variable gain amplifier circuit based on the output of the low-pass filter. (3) The timing generation circuit generates one pulse each indicating the position of the synchronization signal and the position of the pedestal level, and the synchronization signal amplitude level detection circuit detects the position of the synchronization signal and the pedestal level using the pulses from the timing generation circuit. The synchronizing signal level according to claim 1, characterized in that the amplitude level of the synchronizing signal is detected by detecting the position of the synchronizing signal, detecting the synchronizing signal level and the pedestal level, and calculating the difference between the synchronizing signal level and the pedestal level. Detection device. (4) an amplification means for amplifying the gain of the video signal; an A/D conversion circuit for converting the output of the amplification means into an analog-to-digital form except for most of the negative synchronization signal; and a synchronization circuit for separating the synchronization signal from the video signal. a signal separation circuit; a timing generation circuit that generates one pulse from the output of the synchronization signal separation circuit; and a timing generation circuit that detects the position of the pedestal level using the pulse from the timing generation circuit, and detects the pedestal level from the output of the A/D conversion circuit. A pedestal level detection device comprising a pedestal level detection circuit for detecting. (5) The pedestal level detection circuit according to claim 4 includes, as an amplification means, a DC level shift circuit for adjusting the DC level of the video signal input to the A/D conversion circuit, and an output of the pedestal level detection circuit and a reference value. a subtraction circuit that calculates the difference between
A clamp device comprising: an A conversion circuit; a low-pass filter that filters the output of the D/A conversion circuit; and a control circuit that controls the DC level shift circuit using the output of the low-pass filter.