JPH0362965A - Photo sensor with memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for writing/writing together with a photosensor on the same substrate.
The present invention relates to a photosensor with a memory function provided with an erasable memory.

[Prior Art] Conventionally, in electronic still cameras, video camera devices, etc., FET type amorphous St (silicon) photosensors are used as photoelectric conversion elements, and optical signals given through an optical system are converted into electricity by the photosensors. The pixel signal is converted into a typical pixel signal, stored in a capacitor, and read out using the sense amplifier of the drive circuit.

[Problem to be solved by the invention] However, this kind of conventional FET type amorphous S
Electronic still cameras and other devices using i-photo sensors cannot perform high-speed continuous shooting due to the low mobility of each pixel of the photosensor and the slow speed of the drive circuit that takes out each pixel signal in sequential scanning. The problem was that I couldn't do it. In addition, the pixel signal converted into an electrical signal by the photo sensor is stored in a capacitor and read out using the sense amplifier of the drive circuit, so when shooting, peripheral circuits after the sense amplifier, display device, or storage device was necessary.

The present invention has been made in view of the above-mentioned circumstances.
To provide a photosensor with a memory function that is capable of continuous photographing and does not require a sense amplifier or a storage device after the sense amplifier during photographing.

[Means for Solving the Problems] The present invention provides a photosensor array configured using thin film transistors and a plurality of frame memories configured using thin film transistors for memory, and the image information output from the photosensor array is transmitted to the plurality of frames. The data is selectively stored in the frame memory of the frame memory.

[Function] In the photosensor with a memory function configured as described above, each time a photograph is taken by operating the shutter, the frame memories are sequentially switched, and the image information output from the photosensor array is stored in multiple frame memories. are stored sequentially. Therefore, it is possible to continue photographing without waiting for the readout of the photographed image information, and high-speed photographing and continuous photographing are possible.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual diagram of the present invention. In FIG. 1, reference numeral 11 denotes a photosensor array in which a number of photosensors corresponding to one frame are arranged in an array, and an optical image is provided as incident light from an optical system (not shown). This photosensor array 11 converts incident light (optical image) into an electrical signal.
That is, it is converted into a pixel signal and output to the changeover switch 12.

This changeover switch 12 switches the frame memories 131, 132°, 131, 132°, 1
3n sequentially to select the pixel signal output from the photosensor array '11.
Output to □, ..., 13n.

These frame memories 13+, 132 . ...13n
When selected by the changeover switch 12, stores the pixel signals sent from the photosensor array 11 for one frame, that is, the image information for one photograph.

The image information stored in the frame memories 13 to 13n is selected by the changeover switch 14 and sequentially read out by the readout circuit 15 in the readout mode after the photographing is completed.
sent to. From the photosensor array 11 to the changeover switch 14, or from the photosensor array 11 to the sequential readout circuit 15, are arranged on one substrate using, for example, an FET.
It consists of thin film transistors (TPT).

The sequential reading circuit 15 has a changeover switch 1.
1 of frame memories 13+ to 13n selected by 4
The stored information is sequentially read out from the beginning and output to the signal amplification circuit 16. The image information amplified by this signal amplification circuit 16 is sent to an image memory 17 having a storage capacity for one frame and displayed on a display unit 18, and is also displayed on a large capacity external storage device such as a floppy disk. 19 and stored.

In the above configuration, when a shutter operation is performed in the photographing mode, a photographed optical image is converted into electrical image information by the photosensor array 11 and stored in one of the frame memories 131 to 13n selected by the changeover switch 12. be done. Also, each time the shutter operation is performed, the frame memories 131 to 13 are switched by the changeover switch 12.
n is sequentially switched, and the photographed image information is stored in the frame memory 13. ~13n are sequentially stored. The image information stored in the frame memories 131 to 13n does not need to be read out every time the shutter is operated, thus enabling high-speed photography and continuous photography.

Then, the frame memory 13. The image information stored in 13n to 13n is sequentially selected by the changeover switch 14 by designating the readout mode after photographing is completed, and sequentially read out via the sequential readout circuit 15. The image information read from the frame memories 13+ to 13n is stored in the image memory 17 and displayed on the display section 18. Therefore, the photographed images stored in the frame memories 13□ to 13n1 can be stored in the large-capacity external storage device 19 while being checked on the display section 18.

FIG. 2 is an equivalent circuit at the time of photographing, showing one pixel cell portion in the circuit from the photosensor array 11 to the frame memories 131 to 13n. A predetermined pulse signal is applied to the drain electrode and gate electrode G of the phototransistor FT in the photosensor array 11 during photographing (shutter operation). The source electrode S of the phototransistor FT is grounded via a pull-down resistor Ra.

Then, by applying a pulse signal to the gate electrode G and drain electrode of the phototransistor FT in synchronization with the shutter operation, a pulse signal corresponding to the amount of light is generated at the connection point A between the source electrode S and the resistor Ra. . A signal generated at this point A is transmitted to memory thin film transistors MTII, MT21 . -MT
It is input to the gate electrode of nL. The thin film transistors MTII to MTnl have drain electrodes and source electrodes connected together and are grounded via resistors R1 to Rn, and are connected to changeover switches SWI, SW2, .
...Connected to terminal 21 via SWn. A pulse signal of an inverted potential synchronized with the signal generated at the point A is applied to one end of the changeover switches SWI, SW2, .

In the configuration shown in FIG. 2, when a shutter operation is performed, a pulse signal is applied to the gate electrode G and drain electrode of the phototransistor FT in synchronization with the shutter operation, and the connection between the source electrode S and the resistor Ra is A pulse signal corresponding to the amount of light is generated at point A. On the other hand, a pulse signal of an inverted potential is applied to the common connection point B of the changeover switches SWt to SWn in synchronization with the signal generated at the point A. Therefore, now the frame memory 13. If memory thin film transistor MTII is selected, a large potential difference will occur between the gate and source/drain of this thin film transistor MTII depending on the amount of light, which will shift the Vt (gate voltage at which drain current begins to flow) of thin film transistor MTII. By doing so, pixel signals are written. For other memories #Jii) Transistors MT 21 to MT, nl are changeover switches SW
Since 2 to SWn are off, the source and drain are at the ground level by the pull-down resistors R2 to Rn, and only a smaller potential difference than that of the selected thin film transistor MTII occurs between the gate and the source and drain.

In this case, memory thin film transistors MTII to MTn
By setting the characteristic of 1 such that stored data does not change at this potential difference level, no data is written.

In addition, in the frame memory 131 selected at this time, data is written in the same way for other pixels, but since the amount of incident light differs for each pixel, different data (shift amount of Vt) is written accordingly. :Remembered.

FIG. 3 is an equivalent circuit showing one pixel cell portion extracted from the frame memories 131 to 13n at the time of reading. As shown in the figure, address lines A and data lines D are arranged in a matrix, and a memory thin film transistor MT and a selection thin film transistor S are located at the intersections of the address lines A and data lines D.
T is provided. The memory thin film transistor MT has a drain electrode applied with a read pulse signal Vd, a gate electrode grounded, a source electrode grounded via a pull-down resistor R, and a selection thin film transistor S.
Connected to the drain electrode of T. The selection thin film transistor ST has a gate electrode connected to an address line A, and a source electrode connected to a data line D.

In the above configuration, when reading data, a read pulse signal is applied to the source electrode of the memory thin film transistor MT, and a pulse signal specifying the selection thin film transistor ST is applied to the address line A. The pulse signal applied to the address line A turns on the selection thin film transistor ST. Then, a signal of a potential corresponding to the channel resistance between the drain and source is read out from the memory thin film transistor MT by the read pulse signal, and is output to the data line D via the selection thin film transistor ST. The value of the channel resistance between the drain and source of the memory thin film transistor MT is stored and set according to the level of the pixel signal when writing the data described above, so by applying a read pulse of a constant potential, the memory thin film transistor MT A signal with a potential corresponding to the storage pixel signal is read out from.

The circuits shown in Figures 2 and 3 above are equivalent circuits for each operation mode during writing/reading, so in actual circuits, both of these circuits are switched. However, this switching circuit is not included. A schematic diagram of each cell is shown in FIG. As shown in the figure, the phototransistor FT has a drain electrode supplied with an operating voltage 1/2Vp, and a source electrode S connected to a write/read changeover switch 31 and a pull-down resistor Ra.
grounded via. The write/read changeover switch 31 is controlled on/off by a changeover signal from a write/read changeover circuit 33.

Then, the write/read changeover switch 31 and the resistor R
A pulse signal corresponding to the amount of light generated at the connection point A with a is input to the gate electrodes of the one-dot thin film transistors MTII to MTnl in each frame memory 131 to 13n. This thin film transistor M T 11= M T n
The drain and source electrodes of 1 are connected to a frame memory selection decoder 32. This frame memory selection decoder 32 uses the changeover switch 1 during data writing.
2, the thin film transistor M T ll = M
Tnl is selected, and when reading data, thin film transistors MTII to MTn are selected according to the operation of the changeover switch 14.
The selected thin film memory element MT is connected to the write/read switching circuit 3 through the selection line 34, and the unselected thin film transistor MT is connected through the unselected line 35.
Connect to 3. This write/read switching circuit 33 consists of a selection system 33a and a non-selection system 33b.
r-1/2 to the Hi and Lo terminals for writing, respectively.
A voltage of VpJ is supplied, a drain voltage Vd is supplied to the read Hi terminal, and data read from the Lo terminal is input to the drain electrode of the selection thin film transistor ST.

The selection thin film transistor ST has a gate electrode connected to the address line A, and a source electrode connected to the data line D.
connected to. Moreover, in the non-selective system 33b,
Ground both Hi and LO terminals for writing, and Hi terminal for reading.
and Lo terminals are both held open.

In the above configuration, at the time of photographing, that is, in the data write mode, the write/read l;/ll open circuit 3
An on command is sent to the write/read changeover switch 31, and this changeover switch 31 is held in the on state. When the shutter is operated in this state, the drain electrode of the phototransistor FT is
A pulse signal of 2 Vp is applied, and a read pulse is input to the gate electrode to operate the phototransistor FT, and a pulse signal corresponding to the amount of light is generated at point A.

Further, in synchronization with the shutter operation, a pulse signal of r-1/2VpJ is manually applied to the writing Hi terminal and Lo terminal of the selection system 33a in the writing/reading switching circuit 33. Therefore, the write voltage r-1/2VpJ is sent from the write/read switching circuit 33 to the frame memory selection decoder 32 via the selection line 34, and the ground potential is sent as the write voltage via the non-selection line 35. It will be done. The frame memory selection decoder 32 switches the write voltage from the write/read switching circuit 33 to the switch 1.
Thin film transistors M T 11 to M according to the specifications of 2.
Output to T nl. For example, if the thin film transistor MTII is specified by the changeover switch 12,
The frame memory selection decoder 32 applies a write voltage r-1/2VpJ to the drain electrode and source electrode of the selected thin film transistor MTll, and applies a ground potential to the drain electrode and source electrode of the other unselected thin film transistors MT21 to MTnl. . Therefore, a large potential difference occurs between the gate and source drain of the selected thin film transistor MTII, and the thin film transistor M
A pixel signal is written to TII. Since the ground potential Lp is applied to the drain and source electrodes of the other unselected thin film transistors MT21 to MTnl, the potential difference between the gate and the source/drain is small, and the stored data does not change.

The thin film transistor M'rt selected as described above
A pixel signal is written to t.

On the other hand, when the read mode is designated, an off signal is sent from the write/read changeover circuit 33 to the write/read changeover switch 31. As a result, the changeover switch 31 is turned off, and the phototransistor FT is switched to the thin film transistor MTII.
- separated from MTnl. In the read mode, the write/read switching circuit 33 switches and connects the reading Hi terminal and Lo terminal of the selection system 33a to the selection line 34, and unselects the reading Hi terminal and Lo terminal of the non-selection system 33b. Switch connection to line 35.

As a result, the selection system 33 in the write/read switching circuit 33
The read pulse signal V given to the read Hi terminal of a
d is sent to the frame memory selection decoder 32 via the selection line 34, while the non-selection line 35 is kept open. The frame memory selection decoder 32 applies a read pulse Vd to the drain electrode of the thin film transistor MT selected by the changeover switch 14.
The drain and source electrodes of unselected thin film transistors MT are kept in an oven state. For example, when the thin film transistor MTII is selected and designated by the changeover switch 14, the read pulse Vd is applied to the drain electrode of this thin film transistor MTII, and the drain electrodes and source electrodes of the other unselected thin film transistors MT21 to MTnl are kept in an oven state. be done. By applying the read pulse Vd to the drain electrode of the selected thin film transistor MTII, a signal with a potential corresponding to the channel resistance between the drain and source is read out, and is transmitted from the frame memory selection decoder 32 via the selection line 34 to the write/write signal. The signal is sent to the readout switching circuit 33. This write/continue output switching circuit 33 is a thin film transistor M for memory.
The data read from T is read out by the selection system 33a.
It is output from the terminal to the selection thin film transistor ST. At this time, a pulse signal is applied from the address line A to the gate of the selection thin film transistor ST, and the read data is outputted to the drain line D. On the other hand, the drain electrodes and source electrodes of the unselected thin film transistors MT21 to MTnl are kept in an oven state, so that no data is read out.

In the above embodiment, ordinary FET type ones were used as the phototransistor FT and the memory element.
A thin film transistor having a structure with two gates as shown in FIG. 6 and FIG. 6 may also be used.

FIG. 5 shows the configuration of a phototransistor FT having a structure including two gates, and here, a structure using an inverted staggered thin film transistor is shown. In the figure, 41 is an insulating substrate made of glass or the like, Gl is a lower gate electrode formed on this insulating substrate 41, and 42 is a lower gate electrode formed over almost the entire surface of the substrate 41 on the lower gate electrode Gl. It is a gate insulating film, and is made of, for example, an SiN film in which the composition ratio St/N of silicon atoms Si and nitrogen atoms N is set to approximately the same value as the stoichiometric ratio (Si/N-0,75). There is. Further, 43 is a semiconductor layer made of l-type a-3i (amorphous silicon) formed on the lower gate insulating film 42 to face the lower gate electrode Gl, and S and D are semiconductor layers on this semiconductor layer 43. sauce formed into.

This is the drain electrode. Further, an upper gate insulating film 44 is formed over almost the entire surface of the substrate 41 on the semiconductor layer 43 and the source and drain electrodes S and D connected thereto. On top,
An upper transparent electrode (upper gate electrode) GA facing the semiconductor layer 43 is formed. The upper gate insulating film 4
4 is, for example, the composition ratio SL/N17) of silicon atoms St and nitrogen atoms N as the stoichiometric ratio (Si/N-0,75).
It is made of a SiN film with approximately the same value as .

In the phototransistor FT configured as described above, when an operating voltage is supplied to the lower gate electrode GL and the drain electrode, the channel resistance changes according to the incident light to the upper transparent electrode GA, and the channel resistance changes according to this channel resistance. A signal is output from the source electrode S.

FIG. 6 shows the structure of a memory thin film transistor MT having a structure with two gates, similar to FIG. 5. In the memory thin film transistor MT having this two-gate structure, in the phototransistor FT shown in FIG. The value of the composition ratio S i /N of rS i /N-0,85~
1.1'' to provide a hysteresis characteristic, and an upper gate electrode G2 is provided in place of the upper transparent electrode GA, but the other configuration is the same as that shown in FIG.

The memory thin film transistor MT having the structure with two gates configured as described above has gate electrodes Gl and G2.
Among them, the lower gate electrode Gl, which faces the semiconductor layer 43 via the lower gate insulating film 42 having a charge storage function, is used as a write/erase electrode, and is connected to the semiconductor layer 43 via the upper gate insulating film 44, which does not have a charge storage function. The upper gate electrode G2 facing the layer 43 is used as a reading electrode.

That is, when using the memory thin film transistor MT having the above two gate structure, writing of data is performed using the lower gate electrode Gl, and reading of stored data is performed using the upper gate electrode G2. . Therefore,
A readout circuit using a memory thin film transistor MT having such a structure is constructed without using a selection thin film transistor, as shown in FIG. That is, as shown in the figure, in the memory thin film transistor MT, the upper gate electrode G2 is connected to the address line A, the source electrode is connected to the data line D, and the lower gate electrode Gl and drain electrode are grounded. By applying a selection pulse signal to the address line A and a read pulse signal to the data line A, a signal corresponding to the channel resistance of the memory thin film transistor MT can be extracted via the data line D.

[Effects of the Invention] As detailed above, according to the present invention, a photosensor array configured using thin film transistors and a plurality of frame memories configured using memory thin film transistors are provided, and images output from the photosensor array are provided. Since the information is sequentially and selectively stored in the plurality of frame memories, the next photograph can be taken without waiting for the readout of the photographed image information, and high-speed photographing and continuous photographing become possible. Moreover, since the image information taken is stored in a plurality of frame memories, a sense amplifier for reading out the image information and subsequent peripheral circuits, etc. are not required when taking images.

[Brief explanation of drawings]

1 to 7 show embodiments of the present invention; FIG. 1 is a block diagram showing the overall schematic configuration; FIG. 2 is an equivalent circuit diagram showing one pixel cell portion taken out at the time of photographing; FIG. 3 is an equivalent circuit diagram showing the pixel l cell portion taken out during readout, FIG. 4 is a schematic configuration diagram per cell including a switching circuit for switching the circuit during imaging and the circuit during readout, and FIG. 6 is a cross-sectional view showing an example of a phototransistor configured using a thin film transistor having a structure with two gates. FIG. FIG. 7 is an equivalent circuit diagram per pixel cell when the memory transistor shown in FIG. 6 is used. 11... Photo sensor array, 12.14... Changeover switch, 13. ~13n...Frame memory, 1
5... Sequential reading circuit, 16... Signal multiplication circuit, 1
7... Image memory, 18... Display unit, 1... External storage device, 21... Terminal, 31... Write/read changeover switch, 32... Frame memory selection decoder, 33... ...Write/read switching circuit, 33a...
Selection system, 33b...Non-selection system, 34...Selection line, 35...Non-selection line, 41...Substrate, G1...
- Lower gate electrode, 42... Lower gate insulating film, 43
... Semiconductor layer, 44... Upper gate insulating film, GA.
・Top transparent electrode, G2 ・Top gate electrode, FT・
...Phototransistor, MT...Thin film transistor for memory, ST...Thin film transistor for selection, GA...
...Top transparent electrode.

Claims (1)

[Claims] A photosensor array formed by arranging a plurality of phototransistors formed of thin film transistors in an array; and a plurality of frame memories formed of thin film transistors for memory and storing image information in units of frames output from the photosensor array. , and memory switching means for selectively switching and connecting the plurality of frame memories to the photosensor array.