JPH0363097B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention provides a method for detecting errors in data in a large-capacity storage unit, etc., in a storage unit control device even when the data is not accessed for a relatively long time and an error occurs. The present invention relates to an error correction method for storage data that can be corrected.

(2) Background of the Technology In information processing systems that have a large-capacity buffer memory separate from the main memory, data often resides in the buffer memory, so the number of accesses to the main memory is small. In systems with such buffer memory, if an error occurs in the data due to the influence of alpha rays on the storage device, the error will not be corrected for a long time, and the error will not be corrected for a long time.
As a result, uncorrectable errors often occur.

(3) Prior art and problems Generally, data in a storage device is attached with a check bit using the SEC-DED (1-bit error correction-2-bit error detection) method, so it is difficult to check the data each time it is accessed. If there is an error, it is corrected using a known 1-bit error correction circuit.

However, when there are few access opportunities, such as in the case of the main memory described above, an error that has occurred once is deferred, and furthermore, an error may occur again in the same data block.

In that case, it becomes impossible to correct the error using the 1-bit error correction circuit.

Furthermore, if this is done by a program or the like, the central processing unit must perform special command decoding and control operations for data checking in addition to its original operations.

(4) Purpose of the Invention The purpose of the present invention is to improve the above-mentioned drawbacks, provide a storage section access generation circuit, a data error correction circuit, a buffer memory, etc. in a storage section control device,
When a burst error occurs in a storage section, the area is switched to a spare area via a buffer memory, thereby providing a system that can correct data errors within a storage section control device. The present invention is designed to perform operations with a simple configuration, although it is necessary to guarantee the data in the switched area when a burst error occurs and the data is switched to the spare area. be.

(5) Structure of the Invention In order to achieve the above object, the present invention includes a storage unit, a storage unit control device that controls the storage unit, and a correction system that corrects the error when a bit error is detected in data in the storage unit. an information processing device comprising: a patrol access generation circuit; a circuit for checking data accessed from a storage unit by the patrol access; and a buffer memory; the patrol access generation circuit performs access; If the data at the address to be accessed is not stored in the buffer memory, the data from the storage section is written to the buffer memory through a data check circuit and a correction circuit, and if the buffer memory has data at the address, the data is stored in the buffer memory. The data read out by accessing the buffer memory is checked by a data check circuit, and written to the buffer memory through a correction circuit, and the data read from the buffer memory is written to the storage part. Thus, the data check circuit detects error locations within a word of data, and when multiple errors are detected within a predetermined memory replacement unit, replaces the memory;
Thereafter, by accessing the patrol access generation circuit, data in the memory replaced via the buffer memory is guaranteed.

(6) Embodiments of the invention Hereinafter, embodiments of the invention shown in the drawings will be described. In the overall system diagram shown in FIG. 1, the storage controller MCU includes an access generation circuit ACG for the storage MSU, a data check circuit DCH from the storage MSU, a circuit PRT for determining access priority, and a circuit PRT for determining access priority. Equipped with a correction circuit CRT. The priority order determination circuit PRT determines the priority order by adding the accesses from the access generation circuit ACG to the accesses from the central processing unit CPU and the channel CHP. In addition, FIG. 1 is equipped with a buffer memory MCUBM201, which is also an intermediate buffer and GSU (global).
It is also called a storage unit) and is a buffer located between the main storage device and the cache memory in the CPU. ing).

Access generation circuit ACG, data check circuit
A detailed diagram of the configuration of the DCH etc. is shown in FIG. 2, and a partial state transition diagram thereof is shown in FIG.

In FIG. 2, PTL 212 indicates a patrol control circuit, which is mainly composed of an access generation circuit ACG as described later, but is initially reset and in an idle state IDL, and no access is generated.

Next, when activated in response to an instruction from the service processor SVP, the DTC shifts from the idle state to the data check state, and "0" is set in the patrol address contained in the port PAT. The priority determination circuit PRT220 selects access from the patrol control circuit and
When PAT is selected, data pipeline T1~
Injected into T6.

Buffer memory of data for address
Regardless of whether it exists on the MCUBM201, this access is to the access control port to the storage MSU.
Input from pipeline T3 to MP0, storage section
MSU is accessed. Also, in accordance with the timing when data is sent from the storage unit MSU, it is inputted into the pipeline again through port LB, and the subsequent operation is controlled.

The above-mentioned patrol access is performed as follows. If there is no data at the address in the buffer memory MCUBM of the storage controller, the data from the storage unit MSU is input to the port DR, and the data check circuit DCH20
6. Write to buffer memory MCBM through data correction circuit CRT218. buffer memory
If the MCUBM has the address, in addition to the above operations, it inputs the data in the buffer memory to the port DR204 via the selector SEL202,
Next, it passes through a data check circuit DCH206 and a data correction circuit CRT208, and is written into the storage section as error-free data. buffer memory
If there is data in MCUBM201, the storage section
The purpose of writing data to the MSU is to reflect the correct data.

If no error is detected in the data from the storage unit MSU, in the state diagram shown in Figure 3, | |
Therefore, the data check DTC state is entered again. In this case, an example of address setting in the storage unit MSU is shown in FIG. 4, and the order in which addresses are checked is shown in FIG. When no error is detected, the order is as shown in FIG. 5A.

If an error is detected in the data from the storage unit MSU, its location information is set in the register EBL208 in FIG.
Reports the detected error to the patrol control circuit PTL. From now on, the patrol control circuit
The state of PTL moves to burst check state BST (step 2) in FIG.

In the burst check state BST (step 2), the storage unit MSU is accessed in the same manner as in the data check state DTC (step 1). When an error is detected in the data from the storage unit, the location information of the error is compared with the contents of the register EBL 208,
When the match circuit CIN210 determines a match, the burst detection bit BST·DRT="1" is stored in the patrol control circuit PTL212.

When the above check of one address is completed, the address is added in the direction shown as 64B direction address in FIG. 4, and the burst check state in FIG.
Input to BST (Step 2). In the burst check state, the entire 4MB address area is checked, but the patrol control circuit PTL 212 counts the number of accesses, and depending on this value, it is controlled whether or not to end the burst check state and move to another state. . Now, referring to FIG. 4, each circled number represents one memory cell. In the memory configuration of FIG. 4, the symbol indicates data in the depth direction (72 bits) of the drawing. 8 bits out of 72 bits are used for ECC code, and the data is 64 bits (8 bytes). The central processing unit CPU assigns one address to one byte. However, the actual memory read unit is 8 bytes. 8.
There is an address difference of 64 bytes (bytes x 8), and the direction of twist is called the 64B direction. Furthermore, the thick line in the figure indicates a 64k bit configuration with one chip of memory, and there is a difference of 64 bytes x 64k = 4 Mbytes, so the direction in which it twists is called the 4MB direction. In Figure 4,
Each memory cell is 64B when viewed in the direction shown as 64B direction.
(bytes) apart, so when accessing in the initial burst check state, after setting the address in the initial memory cell, by sequentially adding the same number of addresses in the 64B direction, All memory cells in one direction can be easily accessed. Furthermore, the address relationship for each memory cell viewed in the 4MB direction is the same as in the 64B direction. One address consists of 72 bits of data. One bit of each address in the vertical direction of the drawing corresponds to one memory element. As mentioned above, this is the part indicated by the thick line in the figure.

The address when the termination condition END occurs is
This is the same address used when an error is detected in the data check state DTC. Even if an error is detected again at this address, it will be ignored. When the end condition END occurs and the last access in that state occurs
If BST/DET="0", add the address in the 4MB direction and move to data check state DTC.
The address order at this time is shown in FIG. 5B. If BST・DET="1", the address
Add in direction 64B and move to waiting state WT. In the waiting state, the patrol control circuit PTL reports to the service processor SVP that multiple errors have been detected within the 4MB address area. When the service processor receives this signal, it analyzes the information in register EBL208, etc.
It knows at which location in which storage unit MSU the error was detected, and instructs which chip in that storage unit MSU should be switched to the spare area.

In addition, the storage unit control unit MCU
Instructs the MSU to rewrite and correct errors. When the patrol control circuit PTL receives this instruction, it transmits a release go signal RLSGO, and shifts from the waiting state WT (step 3 in FIG. 3) to the release 1 state RLS1 (step 4).

In release 1 state RLS1 (step 4),
Data check status The memory section operates in the same way as DTC.
Access the MSU and make data corrections as well.
Write to buffer memory MCUBM201 and storage unit MSU. In this case, the address is 64B in Figure 5.
Always added in the direction. Release 1 state RLS1
to Lily 2 state RLS2. At this time as well, the address is added in the 64B direction.

In the Release 1 and Release 2 states, the aforementioned patrol access is performed. As mentioned above, in patrol access, if there is no data at the address in the buffer memory MCUBM201 of the storage unit controller, the data from the storage unit MSU is input to the port DR, and the data check circuit DCH2
06. Write to buffer memory MCUBM201 through data correction circuit CRT218. If the buffer memory MCUBM201 has data at the address, in addition to the above operations, the data in the buffer memory is input to the port DR204 via the selector SEL202, and then passed through the data check circuit DCH206 and the data correction circuit CRT218 to correct the error. Write to the storage unit as missing data. Therefore, patrol access is performed twice in Release 1 and Release 2. The first patrol access in the state of Release 1 mainly involves correcting data in the storage unit MSU and updating the buffer memory.
An operation of writing to the MCUBM 201 is performed. In Release 2 state RLS2, Release 1 state RLS
Since the same patrol access as in 1 is performed, the contents of the buffer memory MCUBM are mainly stored in the storage section.
Write to MSU.

In the release 2 state RLS2, as in the burst check state BST, a termination condition is created based on the number of accesses and the state is changed. When the termination condition occurs, the address is incremented in the 4BM direction, the state moves to a data check state, and the storage MSU data is checked again. The above address order is shown in FIG. 5C.

The above operation will be explained by comparing FIGS. 4 and 5.

Address, , etc., and perform the above patrol access.

When an error is detected, the direction of address addition changes according to the detected address, accesses in the direction of..., and checks whether there is an error at the same bit position as the position where the error was detected.
Detected.

(The detailed explanation of this operation is as described above. The bit position is determined by the error bit location circuit.
Since it is stored in EBL208, the matching circuit
Matching of bit positions is detected by CUN210. ) A burst error occurs when an error occurs at the same location.

When a burst error is detected, the element (the element is
(any one element of the bits) is replaced by the service processor SVP.

Next, release RLS1 and RLS2 operations, which are the characteristic feature of the present invention, are performed.

This simply makes patrol access twice in the direction of the above addresses, . . . . The operation of patrol access is as described above.

If, at the time of release RLS1, the data at the specified address is not stored in the buffer MCUBM 201, as defined above, "the buffer memory MCUBM of the storage controller
If there is no data at the address, the memory
Input data from MSU to port DR, data check circuit DCH206, data correction circuit CRT2
18 to the buffer memory MCUBM. Therefore, the error-corrected data will be added to the buffer.

Next, this data is accessed as described above in the patrol access at the time of release RLS2. If the buffer memory MCUBM has data at the address, in addition to the above operation, the data in the buffer memory is input to the port DR204 via the selector SEL202. Then, the data is written into the storage section as error-free data via the data check circuit DCH206 and the data correction circuit CRT218. Therefore, if patrol access is performed twice, the correct data will be reflected after the memory is replaced. Therefore, the present invention has the advantage that data guarantee after detecting a burst error and replacing the memory can be easily performed by performing the same access twice as in the patrol access. Further, since similar accesses are performed, separate access control and routes would be required for separate accesses, but this is not necessary in the present invention.

Note that the replacement of a memory chip (one element) is performed for one bit. Burst error check is performed to identify the error bit position.
It means at which bit of 64 bits/address (72 bits in the figure includes 8 bits of ECC code) an error occurs. For example, if an error occurs in the 10th bit of multiple addresses,
The memory chip that makes up the 10th bit is defective, so it will be replaced with another chip.

FIG. 6 shows the internal configuration of the patrol control circuit PTL of FIG. 2, which consists of an access generation circuit ACG, two timing circuits, and the like. The timing circuit consists of two counters, U-CTR and L-CTR.
C-UP0 and CRY0 indicate the count-up signal and carry signal of the counter U-CTR, respectively, and C-UP1 and CRY1 indicate the count-up signal and carry signal of the counter L-CTR. In addition, PAT-RQ is a signal that instructs the access generation circuit ACG to output an access to port PAT in Figure 2, and PATC-INC is a signal for burst check BST, release 1RLS1, release 2RLS.
This is a signal instructing a count up of 2.

In the data check state DTC, this access is reduced and the central processing unit CPU and channel
Although we would like to reduce the impact on accesses from CHP, it is not possible to make the access interval very large, and it is difficult to determine an appropriate value in advance. Therefore, by setting an arbitrary value as the initial value for the counter U-CTR, an arbitrary access interval can be set. Since the count up signal C-UP1 is set to “1”,
The counter L-CTR is counted up every clock, and the carry CRY1 becomes "1" at regular intervals. In data check state DCT, counter U-
CTR count-up signal C-UP0 is cancelled.
CRY1 is selected, and the counter U-CTR is counted up by the carry CR1. Carrier CRY0 is selected for the access instruction signal PAT-RQ, and when carrier 0 is "1", PAT-RQ
becomes “1”. At that time, access generation circuit ACG
outputs the access and also outputs the counter U-
Let CTR set the initial value. Therefore PAT−
RQ becomes “1” at regular intervals determined by the initial value,
Since it will be accessed, you can obtain any access interval by changing the initial value. Next, in the burst check state, release 1, and release 2 state, it is necessary to quickly process the detected error, so the selector is switched so that the access instruction signal PAT-RQ is generated by the carry CRY1. As a result, the access interval becomes shorter and error correction is performed in a shorter time. At this time, counter U-
Since CTR is not used, this counter is used to calculate the number of accesses. Burst check status
When entering BST, the counter U-CTR is set to "0", and when it is determined that an access has flown from the signal from the pipeline T5, the count-up instruction signal PAT-INC is set to "1" and the count-up starts. . Since the end condition END is when the carry CRY0 occurs, it is used as a movement condition signal for each state.

The embodiments of the present invention have been described above, assuming that the buffer memory MCUBM in this embodiment is a store-in (swap) type buffer.

By performing Release 1, (a) correct values are returned to the storage unit MSU for data originally grown in the buffer, and (b) correct values are written to the buffer for data that was not present in the buffer.

Even if this is the case, the data in the latter (b) is a swap-type buffer and will be moved out to the storage unit MSU later, so it seems that there is no need to perform release 2, but in the present invention, (a), Regardless of (b), perform Release 2.

In case (b), if the data is patrolled again before it is moved out from the buffer MCUBM to the storage MSU, an error will be detected again and burst check, chip replacement, etc. This is because the action will be performed. Furthermore, the data in case (b) will be left in a 1-bit error state on the storage unit MSU, and there is a possibility that a 2-bit error will occur, so release 2 is performed.

(7) Effects of the invention As explained in detail above, according to the present invention,
By repeating access similar to patrol access, data can be easily corrected when replacing the chip when an error is detected.

[Brief explanation of drawings]

Fig. 1 is an overall system diagram showing an embodiment of the present invention, Fig. 2 is a detailed explanatory diagram of a portion of Fig. 1, Fig. 3 is an operational state diagram of Fig. 2, and Fig. 4 is an address setting of the storage unit. 5 is an access explanatory diagram, and FIG. 6 is a patrol control circuit in FIG. 2.

Claims (1)

[Scope of Claims] 1. In an information processing device having a storage unit, a storage unit control device that controls the storage unit, and a correction circuit that corrects an error when a bit error is detected in data in the storage unit, a patrol access generation circuit is provided. , a check circuit for data accessed from the storage unit by the patrol access, and a buffer memory, wherein the patrol access generation circuit performs an access and checks whether the data at the address to be accessed is not in the buffer memory. In this case, the data from the storage section is written to the buffer memory through a data check circuit and a correction circuit, and if the buffer memory has data at the address, the storage section is accessed and the read data is data checked. The data check circuit performs access by checking the data in the data word by the access operation by the patrol access generation circuit, and writes the data into the buffer memory through the correction circuit and writes the data read from the buffer memory into the storage unit. detecting the error position of the memory, and when a plurality of errors are detected within a predetermined memory replacement unit, replacing the memory, and then accessing the patrol access generation circuit; 1. An error correction method for storage data, characterized by guaranteeing data in a memory that is replaced via a buffer memory.