JPH0363210B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE RELATED APPLICATIONS The method of the present invention is, in some respects, a self-aligned minimum mask method for manufacturing insulated gate semiconductor devices with integrated shorts. U.S. Patent Application No. 406,731 to Victor A.K. Temple and entitled ``Insulated Gate Semiconductor Devices with Integrated Shorts Fabricated by Dual Etching and Use of a Diffusion-Selective Oxidation Barrier. 396,172 to Victor A. K. Temple, entitled "Self-Aligned Minimum Mask Method for Reconciling Masks". The contents of these patent application specifications are incorporated herein by reference. U.S. Patent Application No.
No. 406,731 is also significant in that it discloses various sub-processes useful in practicing the present invention. Examples include various sub-processes that may be used to provide windows for source contacts (eg, based on selective oxidation techniques) and various sub-processes that may be used to form source and base regions.

BACKGROUND OF THE INVENTION The present invention relates to insulated gate type power semiconductor devices such as MOSFETs as well as other more complex devices including MOSFET-like structures such as insulated gate rectifiers (IGRs), MOS gated thyristors and other MOS type The present invention relates to a method of manufacturing a transistor or MOS thyristor composite element. More particularly, the present invention relates to a method of forming the top electrode region and base region of the above-described device without a masking step requiring precise alignment, thereby reducing the minimum cell size.

Known power MOSFETs generally consist of a large number (sometimes thousands to tens of thousands) of unit cells formed on a single silicon semiconductor wafer. Such unit cells have dimensions on the order of 300 mils (0.3 inches) and are electrically connected in parallel.
Each unit cell typically has a width of about 25 microns. Various geometric configurations are possible for such unit cells, including elongated strips.

One of the known techniques for manufacturing power MOSFETs is the double diffusion technique. According to it,
First, a common drain region of, for example, N type semiconductor material is formed on an N ⁺ type substrate. after that,
- A base region is formed inside the drain region by a first diffusion step for introducing impurities of a conductivity type, and then a base region is formed by a second diffusion step for introducing impurities of an opposite conductivity type. A source region is formed inside. If the drain region is N-type, a P-type base region is formed by performing a first diffusion step with an acceptor impurity, followed by a second diffusion step with a donor impurity. An N ⁺ type source region is formed. At the surface of the drain region,
A base region will exist as a band between the source and drain regions.

An insulated gate electrode structure is defined on the surface by forming a conductive gate electrode over the strip of the base region while being separated by a gate insulating layer. Typically, the gate electrode is made of highly doped polysilicon. In operation, applying a voltage of appropriate polarity to the gate electrode causes an electric field to extend through the gate insulating layer into the base region, thereby inducing a conductive channel just below the surface.
As a result, current flows horizontally between the source and drain regions through a conductive channel.

To form such an insulated gate electrode structure, a uniform gate insulating oxide layer and a uniform doped polyurethane are deposited during an initial wafer preparation step prior to the introduction of impurities to form the base and source regions. A silicon layer is placed over the drain region. Spaced apart insulated gate electrode structures are then formed along the drain region by etching trenches into the polysilicon layer and the gate insulating oxide layer.

In the case of power MOSFETs, the source, base, and drain regions correspond to the emitter, base, and collector, respectively, of a parasitic bipolar transistor. As is known, when such a parasitic bipolar transistor is turned on during operation of a power MOSFET, the blocking voltage and dv/dt characteristics of the power MOSFET are substantially reduced. Therefore, in order to prevent the parasitic bipolar transistor from being turned on during operation of the power MOSFET, it is common to short-circuit the layers constituting the source and base regions using ohmic connection means.

This same general MOSFET structure may also be included in other more complex devices. For example, a P ⁺ type substrate can be used instead of an N ⁺ type substrate. Such a P ⁺ type substrate constitutes the anode region of a MOS gated thyristor or an insulated gate rectifier (IGR), depending on the density of the short circuits.
In this case, an N-type drain region is formed as described above, but here more generally the "first
area. On the other hand, the P ⁺ type anode region is referred to as a "second region." A P ⁺ shaped base region is formed in the first region as described above,
An N ⁺ shaped region is then formed within the base region.
In the case of an IGR, such an N ⁺ type region is not called the source region as in the previous case, but is called the rectifier cathode region or more generally the top electrode region.

As another example, a lower main electrode region of a MOS gate type thyristor is formed by placing an N ⁺ type third region below a second region doped with a medium concentration of P type impurity. You can also do that.

It will be appreciated that in each of these cases, the MOS gate structure is essentially the same, with the only substantial changes in the overall device structure being with respect to the layers below the first region. . In any case, it is desirable to provide a short between the upper electrode region and the base region (whether in the source region of a MOSFET, the cathode region of an IGR or the main electrode region of a MOS gated thyristor). Also, in any case,
A metal terminal is connected to the upper electrode region and gate electrode of the element.

In this specification, for convenience, the present invention mainly refers to
Explained in relation to MOSFETs. However, based on the above explanation, it goes without saying that the present invention is equally applicable to various other types of insulated gate type semiconductor devices.

Based on the structures of known power MOSFETs currently manufactured, five to seven masking steps are typically required, and several masks are placed at high relative levels to obtain a properly working device. Must be aligned with precision. In particular, when forming the source-to-base short between the first and second diffusion steps, a diffusion barrier covering a portion of the base diffusion surface area is installed by selective masking, thereby providing selective Source diffusion into the base region is prevented within the target masked area. As a result, a shorting extension of the base region extends to the surface. after that,
The selective mask is removed and metallization for the source terminals is installed. A portion of such source terminal metallization also makes ohmic contact with the previously masked area of the base region.

Conventional methods include multiple masking steps and require alignment, resulting in low yields. Furthermore, the need to provide tolerances for misalignment requires unit cell dimensions to be unnecessarily large, which undesirably increases the spreading resistance effect. Furthermore, conventional methods typically form encapsulated gate electrode structures with remote gate contacts, which also result in increased gate input impedance. The aforementioned patent application Ser. No. 406,731 discloses various methods for manufacturing power MOSFETs and similar devices. These methods are characterized in that they include a minimum number of photolithographic masking steps and are fail-safe in several respects. Polysilicon gate molding according to the method disclosed in U.S. Patent Application No. 406,731, supra.
In manufacturing a MOSFET, a semiconductor wafer is first prepared that includes a drain region, a gate insulating layer uniformly formed on its surface, and a conductive polysilicon gate layer. A subsequent masking and etching step etches a trench through the polysilicon gate layer and gate insulating layer to the drain region. In general, the method of U.S. Patent Application No. 406,731 uses a single undercut etch step, resulting in an overhang layer on the polysilicon gate electrode.
is left behind. The remaining portions of the polysilicon gate layer will define spaced apart polysilicon gate electrode structures along the drain region. Using such a polysilicon gate electrode structure as a mask, impurities are introduced into the drain region from the surface between the polysilicon gate electrodes and then properly positioned by moving them through thermal diffusion. A base region and a source region are formed. In that case, the source region is located inside the base region in both the horizontal and vertical directions. According to the various methods disclosed therein, impurities for the base and source regions are introduced by ion implantation, diffusion of a gaseous impurity source, or a combination thereof. In the case of ion implantation, impurities are introduced through the gate insulating layer in some variations. Several variations are also disclosed for forming shorting extensions of the base region that extend through the source region to part of its surface.
Many of these variants use an overhang layer formed by undercut etching as a mask to form an extension of the base region up to the surface of the source region, and are thus self-masking. It is. U.S. Patent Application No.
According to the method disclosed in No. 406731, 2
A seed general MOSFET structure is formed. One structure has metallized finger gate terminals, which are formed according to the -mask method. The other structure has a finger gate encapsulated in an insulating oxide and connected to a remote gate contact, and is formed according to a three-mask method. For either structure, the preferred method requires selective oxidation of the polysilicon gate electrode material, and various means for achieving such selective oxidation have therefore been described.

On the other hand, the aforementioned U.S. Patent Application Ser. Various variants have been disclosed that allow the formation of . (However, in order to automatically separate the metal film into source and gate terminals,
Advantageously, an overhanging layer of electrically conductive, refractory material is present. In summary, a variation of U.S. Patent Application No. 396,172 forms a source-to-base short according to the following procedure. (1) Following the initial wafer preparation step, narrow trenches are formed by narrow etching in the drain region.
(2) An initial base region is formed and a nitride mask is installed, using the sidewalls of such narrow trenches as masks. (3) Separate the nitride mask from the gate by widening the trench with a lateral etch. (4) Using a nitride mask, the source and base regions are formed by diffusion and the sidewalls of the gate are selectively oxidized.

The present invention now seeks to provide another two-stage etching method for forming source-base shorts.

SUMMARY OF THE INVENTION One object of the present invention is to provide a self-aligned manufacturing method for insulated gate semiconductor devices, particularly in the case of MOSFETs. The goal is to provide a method for

It is also an object of the present invention to provide such a method which is suitable for the manufacture of devices with direct metallized finger gate contacts or remote gate electrode contacts.

A self-aligned manufacturing method for an insulated gate semiconductor device according to an embodiment of the present invention will be briefly described as follows.
First, one conductivity type (e.g. N
A semiconductor wafer (eg, a silicon wafer) including a first region (eg, a drain region of a MOSFET) of a shape) is prepared. As an initial preparation step for such a wafer, a gate insulating layer of, for example, silicon dioxide and a conductive gate electrode layer of, for example, heavily doped polysilicon of the N ⁺ type are successively formed. If the power MOSFET to be manufactured has a finger gate encapsulated in an insulating oxide and connected to a remote gate contact, the polysilicon gate electrode layer may be immediately masked. can. However, when fabricating power MOSFETs with metallized finger gate terminals, it is preferred to provide a top mask layer (eg, of silicon nitride) that is resistant to high temperature processing over the polysilicon gate electrode layer.

A corrosion-resistant mask, typically with an opening defining the final location of the source region, is then placed over the wafer. Since the first method for manufacturing power MOSFETs with encapsulated gate electrodes is a three-mask method, the corrosion-resistant mask described above is the first mask used in such a method. However, power MOSFETs with metal-coated finger gate terminals
Since the second method for manufacturing is the -mask method, the corrosion-resistant mask described above is the only mask used in such a method.

A two-stage etching operation is used in the present invention. The next step is the first stage of etching. Relatively narrow trenches are formed by etching the polysilicon gate electrode layer at least down to the gate insulating layer according to a suitable etching method.

Suitable impurities are then introduced into the drain region, for example by ion implantation, to form a shorting region of the opposite conductivity type (for example P type). In that case, ion implantation may be performed substantially vertically. During this step, the remaining portion of the polysilicon gate electrode layer serves as a mask. According to a preferred embodiment, the ion implantation of the shorting region impurity is performed prior to the removal of the gate insulating layer, such that the ion implantation is performed through the gate insulating layer. At any point during the method of the invention,
That is, immediately after ion implantation or during the diffusion or heating process described below, the impurity for the short circuit region is moved at least vertically to a desired depth by thermal diffusion, so that the short circuit region extends from the main surface to the desired depth. You will get it.

A second lateral etch is then performed on the remaining portions of the polysilicon gate electrode layer to form polysilicon insulated gate electrode structures extending upwardly from and spaced apart along the major surface. Ru. At this point, the corrosion-resistant mask may be removed.

Suitable impurities are then introduced into the drain region to form a base region of the opposite conductivity type (e.g. P type) and of one conductivity type (e.g. N ⁺ type).
Suitable impurities are introduced into the base region to form a source region. By thermally diffusing the impurities thus introduced, appropriate positions and shapes are given to the base and source regions.
As a result, in the main plane, the base region exists as a strip of opposite conductivity type between the source region and the drain region, and the active portion of the base region strip is below at least a portion of the insulated gate electrode structure. It will be located in In order to ensure that the source-base short circuit is completed in a subsequent metallization step, the base region and the corresponding short circuit region form a continuous region of opposite conductivity type below the main surface.

Impurities for the source and base regions are preferably introduced by ion implantation through the gate insulating layer. However, diffusion of gaseous impurity sources can also be used, as long as the gate insulating layer is removed first. Importantly, unlike the various methods described in U.S. Patent Application Ser. The advantage lies in the fact that a perpendicular implantation direction can be used in the case of ion implantation.

At some point during the method, at least the sidewalls of the polysilicon gate electrode are oxidized. In this case, the metallization can be brought into contact with the source region without the need for a separate masking step to provide a window for the source contact.
It is preferable to perform selective oxidation, such as oxidizing the sidewalls of the polysilicon gate electrode without oxidizing the surface of the source region. As described in more detail in the aforementioned US patent application Ser. No. 406,731, two general methods can be used to accomplish such selective oxidation.

According to the first method, a silicon nitride layer is included in the gate insulating layer. Selective oxidation of the polysilicon gate electrode is accomplished by heating in the presence of oxygen prior to removing the gate insulating layer over the source region. In this case, oxidation of the source region is prevented by the presence of the silicon nitride layer.

According to a second method for achieving selective oxidation, no silicon nitride layer is included in the gate insulating layer. This is beneficial in terms of the performance of the finished device. This is because unstable charges may exist in the nitride/oxide sandwich structure. Instead, a silicon nitride oxide mask layer is later formed over the source region. Such an oxidation mask layer can be formed, for example, by ion implantation or low pressure vacuum deposition.

Furthermore, the silicon nitride oxide masking layer over the source region may be eliminated and the surface of the source region oxidized, at the expense of requiring an additional masking step. In this case, an oxide etch is performed using a mask to provide a window for the source contact. Although an additional masking step is required, the source-to-base short is still formed without the need for a masking step.

If the gate insulating layer has not already been removed, it is removed at this point. As a result, silicon is exposed in the source region.

The remaining step in the method of the invention is the metallization step. In the case of a mask method for forming metallized finger gate terminals, metal (for example aluminum) is deposited on the wafer surface.
Such metal automatically separates into an upper gate contact and a lower source contact. In the case of the three-mask method for forming the encapsulated gate electrode, windows for the gate contact are provided in portions of the wafer other than the source region through the use of additional masking and etching steps. Further, by performing pattern formation using a third masking step, the metal film is separated into a source terminal portion and a gate terminal portion.

One of the advantages of the present invention is that many of the methods described are fail-safe.
That is, even if individual unit cells are not completely formed, there is no problem with the device as a whole. As a result, high yields are achieved.
One such example is a photoresist error in the initial masking step (ie, photoresist is present where it should not be present or is absent where it is supposed to be present). Even in such a case, although the unit cell may not operate, the device as a whole operates correctly. Another case is when a source-base short is not formed in a certain area of the device.

There are relatively few possible catastrophic failure modes. One example is a metallization error where the source and gate terminals touch and short the device.

DETAILED DESCRIPTION OF THE INVENTION The novel features of the invention are pointed out in the appended claims. However, the structure and content of the present invention, as well as other objects and features, may be better understood from the following detailed description, taken in conjunction with the accompanying drawings.

In this specification, for convenience, mainly N ⁺ type source region, P type base or channel region and
It should be noted in advance that the device and manufacturing method of the present invention will be described in connection with a MOSFET having an N ^- type drain region. More generally, the method of the invention will be described in relation to an insulated gate semiconductor device having an N ⁺ type top electrode region, a P type base region and an N type first region. However, it goes without saying that the present invention is equally applicable to various devices in which the active regions formed have opposite conductivity types.

A first general form of the device is characterized by having a gate electrode encapsulated in an insulating oxide and then surrounded by a metallization in the upper electrode region. In this case, remote gate contacts are used. Only one conductive layer may be present in the gate electrode, but a second layer may be used to reduce gate input resistance. Devices of this type are manufactured according to the three-mask method described in detail in connection with FIGS. 1-12.

The present invention can also be applied to devices that are generally capable of high frequency operation by having finger-shaped gate terminals that are metallized to reduce gate input resistance. Elements of this type are manufactured according to the mask method described herein in connection with FIGS. 13-18.

However, it should be noted that the three-mask method for forming encapsulated gate electrodes has several advantages. First, the source region,
The base region and the shorting region can all be formed. Second, there is no need to provide a protective layer that can withstand high temperature processing on the top surface of the polysilicon gate electrode. This is because neither masking layer is required to survive several high temperature processing steps.

Furthermore, it should be noted that the methods described in detail below are specific embodiments that are presently preferred. It should be noted that such methods and variations may be used in different combinations than those described below, and that the various steps may be performed in a different order than those described below. Needless to say, it is.

<Encapsulated Gate Electrode Element> Turning first to FIG. 1, a partial cross-sectional view of the active portion of a power MOSFET 50 is shown. In this case, one unit cell 52 is fully illustrated, while the adjacent unit cells are only partially illustrated. As is well known, a power MOSFET consists of a large number of unit cells formed on a single semiconductor wafer 54, and these unit cells are electrically connected in parallel. The unit cell 52 has a common drain region 5 made of N ^- type silicon semiconductor material.
6, and a common metal terminal 58 is in ohmic contact with the drain region 56 via an N ⁺ type substrate 60 doped with impurities at a high concentration. The currently preferred semiconductor material is silicon, although other semiconductor materials (eg, gallium arsenide) can also be used.

Unit cell 52 also has an N ⁺ source region 62 and a P-type base region 64 formed within drain region 56 . At the surface 66 of wafer 54, each base region 64 exists as a band 68 of P-type semiconductor material between N-type source region 62 and drain region 56.
In order to prevent turn-on of the parasitic bipolar transistor formed by the N ⁺ type source region 62 , P type base region 64 and N ^- type drain region 56 , the P ⁺ type shorting region 69 or the source region 62 is penetrated. A source-to-base short is provided consisting of an extension of the base region 64 extending to the surface thereof. Such a short circuit is completed by a portion of the metallization for the source terminal.

surface 6 to induce enhancement type channels useful for operation of field effect transistors.
A gate insulating layer 72 and a conductive gate electrode 70 are disposed on the base region 64 so as to at least cover the strip 68 of P-type semiconductor material constituting the base region 64 . As a result, a trench is defined between the gate electrodes 70, and the source region 62 (and shorting region 69) is located at the bottom of the trench.

According to one embodiment, gate insulating layer 72 has a sandwich structure. For reasons detailed below, the gate insulating layer in such a structure includes a first oxide layer 74 of silicon dioxide, a nitride layer 76 of silicon nitride, and (if desired)
A second oxide layer 7 also consisting of silicon dioxide
8.

A polysilicon gate electrode 70 is completely encapsulated in a protective oxide layer 79, including the sidewalls and top surface. The entire active part of the wafer, including the encapsulated gate electrode 70, is covered by a metallization 88 for the source terminal. Therefore, remote gate contacts are required, resulting in high gate input resistance. (However, the 10th
It will be appreciated that low gate input resistance is obtained in accordance with the embodiments described below in connection with FIGS. ) As can be seen in FIG. 1, the metal coating 88 for the source electrode is in ohmic contact with both the source region 62 and the shorting region 69, thereby achieving ohmic contact between the source region 62 and the base region 64. There is.

Base region 64, source region 62 and shorting region 69 of FIG. 1 are moved to their final positions by a thermal diffusion process as described below. The approximate locations of these regions are shown in FIG. 1, and as can be seen, the surface portion of the base region, or strip 68, is located completely below the conductive gate electrode 70, and thus An overlap portion 90 exists between source region 62 and conductive gate electrode 70 . In carrying out the thermal diffusion process, it is necessary to control the width of the overlapping portion 90 to be at least 0 or more, in other words, so that the overlapping portion 90 always exists.

Regarding operation, each unit cell is normally in a non-conducting state and has a relatively high withstand voltage. When a positive voltage is applied to the gate electrode 70, it penetrates the gate insulating layer 72 and forms the base region 6.
An electric field is generated that extends up to 4. As a result, electrons are attracted from the P-type base region 64.
A thin N-type channel is induced directly beneath the surface 66 located below the gate electrode 70 and gate insulating layer 72. As is known, the higher the gate voltage, the more conductive the channel and therefore the more operating current will flow. The current flows through the source region 6
2 and drain region 56 in a horizontal direction near surface 66 and then in the remaining drain region 5
6 and flows vertically through substrate 60 to reach drain terminal 58 .

<Other insulated gate type devices> As outlined above, the general MOSFET structure shown in FIG. 1 is representative of all insulated gate type semiconductor devices to which the method of the present invention is applied. .

For example, to obtain an insulated gate rectifier (IGR), substrate 60 in FIG. 1 may be of the P ⁺ type, thereby forming the rectifier anode region. N ^- type region 56 is more generally referred to herein as a first region, and substrate 60 is more generally referred to herein as a second region. Although source region 62 constitutes the rectifier cathode region, it is more generally referred to herein as the top electrode region.

Similarly, although not clearly shown in the drawings, by forming an N ⁺ type third region (not shown) below the second region 60 doped with a medium concentration of P-type impurities. It is also possible to obtain a MOS gate type thyristor. In this case, the third region will constitute the main terminal region of the thyristor.

In a normal device manufacturing method, as is obvious, the lower layer (i.e., the third region in the case of a MOS gate thyristor) is formed first;
The upper layer is then formed one after the other, for example by epitaxial growth techniques.

In the following description, for convenience, the method of the invention will be described in detail with respect to MOSFETs. However, it goes without saying that the method of the present invention is equally applicable to the above and other insulated gate type semiconductor devices in general.

<Three-mask method for forming encapsulated gate electrodes in FIGS. 2-9> In connection with FIG. 2, first, a silicon semiconductor wafer 54 including an N ^- type drain region 56 is prepared. To do this, first a suitable wafer substrate 60 of low resistivity is provided, for example 10 mils thick and
Any N ⁺ type substrate with a resistance of 0.001Ω・cm will suffice.
Then, by epitaxial growth, for example, 2
A drain region 56 having a mil thickness and a resistivity of 25 Ω·cm is formed on the wafer 60. This is a typical 500V structure.

Gate insulating layer 72 is then formed on surface 66 of drain region 56 by successively forming a first oxide layer 74, a nitride layer 76, and a second oxide layer 78. Oxide layers 74 and 7
8 may be produced by thermal oxidation and chemical vapor deposition, respectively. Additionally, nitride layer 76 may be formed by chemical vapor deposition. Since the nitride layer 76 is included to facilitate selective oxidation of the sidewalls of the polysilicon gate electrode 70, a modified method or source contact in which a nitride oxidation mask is formed in a subsequent intermediate step is included. It may also be omitted in variations where an additional masking step is used to provide the partial window. The use of second oxide layer 78 is also optional and is included to facilitate selective oxidation of the polysilicon gate electrode material while protecting nitride layer 76. This is because many polysilicon etchants attack silicon nitride, whereas silicon dioxide resists them well. This oxide layer 78 also serves to reduce mechanical stress in the gate insulating layer 72 and at the interface between the gate insulating layer 72 and the gate electrode layer 91.

Next, the thickness of the final gate electrode 70 (for example,
A high conductivity gate electrode layer 91 having a thickness suitable for 1.0μ) is formed on the gate insulating layer 72. The gate electrode layer 91 is made of highly concentrated N ⁺ type or
It is preferably made of polysilicon doped with P ⁺ type impurities (N ⁺ type impurities in the illustrated case). However, other materials (eg, metal silicides) can also be used for the conductive gate electrode layer 91. The general requirements for any material used are (1) that it can be oxidized in a controlled manner; (2) that it can be etched by etching methods or etchants that do not attack the oxide; 3) have good electrical conductivity; and (4) have a coefficient of thermal expansion reasonably matched to silicon.

Following the initial wafer preparation steps, a first corrosion resistant mask 92 is formed by photolithography with openings 94 defining the final locations of the source and short regions. The first mask will be explained in more detail later in connection with FIG. 9.

Next, an initial etching step is performed, as seen in sections 3A and 3B. This initial etching step is performed to open the opening 94 of the first corrosion-resistant mask 92.
The process is performed until the gate electrode layer 91 is penetrated in the area defined by the gate insulating layer 72. Figure 3A shows the results of a preferred selective etch, and Figure 3B shows the results of a usable isotropic etch.

The selective etching of FIG. 3A is suitable for encapsulated gate electrode type devices because it allows the unit cell dimensions to be reduced. In the case of metallized gate electrode type devices manufactured according to the -mask method as described below in connection with FIGS. 16 to 18, the metallization is automatically separated into source and gate terminals. , directional etching giving vertical sidewalls can be considered essential. To etch substantially perpendicular to the polysilicon, several known methods using electric fields to achieve directionality can be used, commonly known as dry etching methods. One example of a dry etching method suitable for use in the practice of the present invention is reactive ion etching.

The presence of second oxide layer 78 facilitates the etching process by protecting nitride layer 76 from the polysilicon etchant. for example,
Many plasma etching methods attack polysilicon well and attack silicon nitride fairly well, but are blocked by silicon dioxide.

Following the initial etch step shown in FIGS. 3A and 3B, impurities are introduced into drain region 56 by ion implantation through gate insulating layer 72 to form shorting region 69. As shown in FIGS. 4A and 4B, the shorting region impurity implantation is performed substantially vertically, with the first corrosion-resistant mask 92 and the remaining portion of the gate electrode layer 91 serving as a mask. It turns out. Such shorting region impurity implantation is performed relatively shallowly and/or using a P-type impurity (eg, indium) having a relatively slow diffusion rate. This is because, at the end of the method, the depth of the shorting region 69 must not be significantly greater than the depth of the source region 62.

Known ion implantation methods can be used.
An example of this is the paper by G.F. Gibbons published in Proc. IEEE Vol. ``Theory and Experiment'' and the same magazine, Vol. 60, No. 9 (September 1972), 1062~
Examples include those described in G.F. Gibbons' article "Ion implantation in semiconductors - Part: Damage generation and annealing" published on page 1096.

Next, referring to FIGS. 5A and 5B,
Following the step of introducing short-circuit region impurities, the remaining portion of gate electrode layer 91 is laterally etched. That is, by providing an undercut below the first corrosion-resistant mask 92, the final dimensions of the gate electrode 70 are defined.
First corrosion-resistant mask 92 is then removed.

Turning now to FIG. 6, as an intermediate step following the lateral etching step of FIGS. 5A and 5B, appropriate impurities are added into the drain region between gate electrodes 70 to form base region 64 and source region 62. be introduced. These regions may be formed by diffusion or by ion implantation as shown in FIG. It should be noted that since there is no overhang layer on the gate electrode 70, the ion implantation can be performed vertically.

A nitride layer (not shown) formed by chemical vapor deposition may be included under the first corrosion-resistant mask 92 to prevent the formation of a PN junction in the gate electrode 70. Such nitride layer is removed after ion implantation.

The top surface and sidewalls of gate electrode 70 are then selectively oxidized to form an encapsulating oxide layer 79, resulting in the structure of FIG.

As a means of significantly facilitating such selective oxidation, the ion implantation described above to form shorting region 69, base region 64, and source region 62 is performed through gate insulating layer 72, so that gate insulating layer 72 is substantially left unharmed. At an appropriate point after ion implantation, the impurities forming base region 64 and source region 62 are moved to the proper location by thermal diffusion.
Such heat diffusion may be performed all at once, or
Alternatively, the process may be performed in multiple steps.
(For convenience, FIGS. 6 and 7 show the positions after thermal diffusion and therefore do not accurately show the positions immediately after ion implantation.) Impurities to form base region 64 and source region 62 Preferably, the thermal diffusion step for moving the material to its final position is carried out simultaneously with the selective oxidation step shown in FIG. According to the most efficient method, all ion implantations are performed at the same time, and all impurities are transferred at the same time during the selective oxidation step.

In more detail with reference to FIG. 7, the intermediate step of selectively oxidizing the top surface and sidewalls of gate electrode 70 to form oxide layer 79 is accomplished by heating in the presence of oxygen. . The oxide layer 79 thus obtained is the first layer in the gate insulating layer 72.
The oxide layer 74 is considerably thicker than the oxide layer 74. Gate electrode 7
The oxidation of the source region 62 between the gate insulating layer 7
This is prevented by the presence of nitride layer 76 in 2.
Note that, prior to selective oxidation of the upper surface and sidewalls of gate electrode 70, it is preferable to remove second oxide layer 78 located in the source region by selective etching to expose nitride layer 76. For more information on selective oxidation techniques, please visit
IEEE Electron Device Letters No.
EDL-Volume 2, No. 10 (October 1981), pp. 244-247, by Jie Hui, Tei Wai Chiu, S. Wong, and D.B. "Selective Oxidation Techniques".

The device at this point is ready for any required final processing. That is, the completed device is obtained by exposing source region 62 and shorting region 69 for metallization, providing a window for the gate contact, applying metallization, and then patterning the metallization. It is.

More specifically, with reference to FIG. 8, selective etching using a suitable etchant (e.g., buffered hydrofluoric acid for oxides and hot phosphoric acid for nitrides) removes the etchants located between gate electrodes 70. The first oxide layer 74, the nitride layer 76, and the second oxide layer 78 (if still present) in the gate insulating layer 72 are removed, thereby forming a layer on the surface of the source region 62. Silicon is exposed. Etching of oxide layers 74 and 78 in gate insulating layer 72 is easily accomplished without removing gate encapsulating oxide layer 79 (formed as shown in FIG. 7); This is because the oxide layer 79 for encapsulating the gate is much thicker. Although it undergoes some erosion, the oxide layer 79 for gate encapsulation
is never completely removed.

A gate contact window is then provided through the gate encapsulation oxide layer 79 in a remote portion of the device 50 that is different from the active portion. As is known, this is accomplished using a second mask 98, the outline of which is shown in FIG.

Thereafter, a metal coating 88 is deposited over the entire device, as shown in FIG. Then, by patterning using the third mask 100 (FIG. 9), the metal film 88 is separated into a source terminal and a gate terminal.

<Method for forming encapsulated gate with high conductivity (first method)
0-12) > To reduce the gate input resistance in an encapsulated gate electrode structure with remote gate contacts, the gate electrode 70 includes a refractory metal silicide (e.g., molybdenum silicide) on a gate electrode layer 91 of polysilicon. layers. Molybdenum silicide has higher conductivity than polysilicon doped with a high concentration of impurities, and can be encapsulated in the gate electrode 70 by oxidizing its surface.

With reference to FIG. 10, the initial wafer preparation process is essentially as described above with respect to FIGS. 2 and 3A. However, in this case, a molybdenum silicide layer 102 is disposed between the gate electrode layer 91 and the first corrosion-resistant mask 92. Shorting region 69 is formed by ion implantation of P type impurities at a concentration sufficient to create a P ⁺ type region, as described above.

Next, as shown in FIG. 11, undercut etching is performed. Unlike the method described above in connection with Figures 2-9,
As can be seen, selective oxidation is performed prior to the introduction of impurities for the source and base regions.
These impurities are introduced by diffusion of a gaseous impurity source, as described below in connection with FIG.

As shown in FIG. 11, oxide layer 79 is formed not only on the surface of polysilicon portion 91 of gate electrode 70 but also on the surface of molybdenum silicide portion 102.

Next, as shown in FIG. 12, the gate insulating layer 70 located between the gate electrodes 70 is removed,
Base region 64 and source region 62 are then formed by introducing impurities from a gaseous impurity source. These 62 and 64 are moved to their final positions by thermal diffusion in a non-oxidizing atmosphere.

At this point, further processing is performed as described above in connection with FIGS. 8 and 9 to form the remote gate contact.

As can be seen by comparing the method of FIGS. 2-9 with the method of FIGS. 10-12, the order in which the steps are performed can be varied in various ways. In particular, the timing of selective oxidation can be varied.

<Modified method in which the silicon nitride layer is omitted in the gate insulating layer> In the methods described above, silicon nitride is added in the gate insulating layer 72 in order to facilitate selective oxidation of the sidewalls of the gate electrode 70. A layer 76 is included. Inevitably, a conductive gate electrode 7
0 and a surface 68 of the base region 64 in the active portion of the gate insulating layer 7 .
6 remains, but does not serve any purpose after selective oxidation of the sidewalls of gate electrode 70.

By the way, it has been found that the sandwich structure of silicon dioxide/silicon nitride may contain diffuse or unstable charges that are thought to exist mainly at the nitride-oxide interface. Such charge is sufficient to cause problems in the MOS structure containing it, for example by making reversal of the conductive channel difficult.

Therefore, according to this variant, no nitride layer is included in the gate insulating layer formed in the initial wafer preparation step, and a silicon nitride oxide mask layer is formed in a later intermediate step. It is. Such variations are described in more detail in the aforementioned US patent application Ser. No. 406,731. However, for convenience, we will summarize them below.

Briefly, first, the drain region 5
A silicon semiconductor wafer containing 6 is prepared.
However, in this case, instead of the gate insulator 72 having a sandwich structure as shown in FIG. is formed. The remaining initial wafer preparation steps are performed as described above, with the only difference being that no silicon nitride layer is included in the gate insulating layer.

At an appropriate point during the method, the gate electrode 70
A silicon nitride oxide mask layer (not shown) is formed over the shorting region 69 and source region 62 located between the gate electrodes 70 to facilitate selective oxidation of the sidewalls of the gate electrodes 70 . Such an oxidation mask layer (not shown) can be formed by a variety of methods, as described in the Huy et al. article "Selective Oxidation Techniques for High Density MOS" cited above. In one example, the oxide mask layer is formed by ion implantation. However, although such ion implantation may be performed at a certain tilt angle if necessary to treat the entire source region between the gate electrodes 70, ion implantation into the sidewalls of the gate electrodes 70 themselves must be avoided. According to the ion implantation method, nitrogen is directly implanted into silicon. Note that if oxide layer 74 is not removed, nitrogen is implanted into both the silicon dioxide and silicon.

Alternatively, the oxide mask layer can be formed by low pressure chemical vapor deposition. Yet another example is sputtering. Note that in order to avoid the formation of a nitride layer on the sidewalls of the gate electrode 70, selective growth techniques or tilted deposition techniques should be used.

<Modified method that does not use a silicon nitride oxide mask layer> As also described in the above-mentioned U.S. Patent Application No. 406,731, the second method does not require an additional masking step. Not only may silicon nitride layer 76 not be included in the gate insulating layer as described above in connection with FIGS. There is no need to form.
In this case, the surface of the source region 62 is oxidized at the same time as the gate encapsulation oxide layer 79 is formed, and the source contact layer is later removed by removing the source region oxide. A window will be provided. In providing such source contact windows, it is customary to use conventionally precisely aligned masks. Also, methods such as collimated beam reactive ion etching or ion milling, which have a high selectivity for silicon dioxide as compared to silicon, can be used.

In any case, by following the method of the present invention, conventional masking steps that require precise alignment for the formation of source-to-base shorts are avoided.

<For forming metal-coated gate electrodes in Figs. 13 to 18-
Mask Method> Next, a two-step etching method for manufacturing an insulated gate type semiconductor device having a metal-coated gate electrode will be described. It is assumed that the final element structure is represented by MOSFET 104 shown in FIG.

In more detail with respect to FIG. 13, the initial wafer preparation process is substantially the same as described above with respect to FIG. However, in this case, for example, a layer 106 of a heat-resistant metal silicide (for example, molybdenum silicide) protected by a silicon nitride layer 108 is formed by photolithography with a gate electrode layer 91 made of polysilicon. and the corrosion-resistant mask 92.

Since a portion of conductive molybdenum silicide layer 106 remains in the completed device of FIG. 18, this molybdenum silicide layer 106 can be referred to as a second conductive gate electrode layer. On the other hand, the polysilicon layer 91 constitutes the first conductive gate electrode layer, and the metal coating 110 for gate terminal (the 18th
Figure) constitutes the third conductive gate electrode layer. As described in more detail in the aforementioned U.S. Patent Application No. 406,731, the second conductive gate electrode layer 106 can take a variety of forms.
Note that a preferred form is as shown in FIG.
A molybdenum silicide layer 106 protected by a silicon nitride layer 108.

It should be noted that while the presence of the second conductive gate electrode layer 106 has several advantages, it is not essential to the invention.
The first advantage is that the finished device has a low input impedance. As can be seen from FIG. 18, the second advantage is that the second conductive gate electrode layer 10 remains in the completed device.
6 is that it extends above the gate electrode structure 70. As a result, it is substantially easier to automatically separate the metallization into gate terminal portion 110 and source terminal portion 112.

Alternatively, the second conductive gate electrode layer 10
6 could be omitted, in which case the protective silicon nitride layer 108 would be placed directly on the polysilicon layer 91. In such a case, the silicon nitride layer 108 is useful for preventing oxidation of the upper surface of the polysilicon layer 91, so the metal coating 11 for the gate terminal is formed on the upper surface of the polysilicon layer 91.
0 can be set directly. However, in such a case, since there is no overhang layer,
The reliability of automatic separation of metal coatings is reduced. Therefore, a convenient metal etching process is required. Such methods are described, for example, in the aforementioned U.S. Patent Application No.
It is described in the specification of No. 396172.

-Returning to the explanation of the mask method, FIG. 14 shows the initial etching step. That is, etching is performed substantially vertically through silicon nitride layer 108, molybdenum silicide layer 106, and polysilicon layer 91 until gate insulating layer 72 is reached. In addition, FIG. 14 shows the 3A as described above.
This is similar to the figure, the only difference being that layers 106 and 108 have been added in the former.

Next, with reference to FIG. 15, a P ⁺ type short is created by performing a vertical ion implantation through the gate insulating layer 72 as described above with respect to FIG. 4A or FIG. A region 69 is formed.

Next, referring to FIG. 16, insulated gate electrode structure 70 is formed by laterally etching the remaining portions of polysilicon layer 91 as described above with respect to FIG. 5A. is formed. As a result, undercuts occur beneath molybdenum silicide layer 106 and silicon nitride layer 108. Gate electrode structure 7 thus obtained
By using 0 as a mask, base region 62 and source region 64 are formed.

Following the method of FIGS. 13-18, as in the variant described above in connection with FIG. 12, source region 62 and base region 64 are formed by diffusion of a gaseous impurity source. Therefore, in order to utilize the nitride layer 76 included in the gate insulating layer 72 as a selective oxidation mask, in FIG. gate sidewall oxide layer 11 by selectively oxidizing the sidewalls of gate electrode structure 70 prior to diffusion of
4 is generated. Thereafter, as shown in FIG. 17, the gate insulating layer 72 located between the gate electrode structures 70 is removed.

However, it is of course possible to form the source and base regions by ion implantation, as described above in connection with FIG. Since such ion implantation can be performed through the gate insulating layer 72, it is also possible to perform the ion implantation before forming the gate sidewall oxide layer 114 by selective oxidation. However, in this case, because the molybdenum silicide layer 106 extends, the drain region 56 located between the gate electrode structures 70
In order to treat the entire surface of the substrate, the ion implantation for forming the source region 62 and base region 64 must be performed at a constant tilt angle. More detailed explanation in this regard can be found in the aforementioned US patent application Ser. No. 406,731.

To remove the first oxide layer 74, nitride layer 76, and second oxide layer 78 (if still present) in the gate insulating layer 72 located between the gate electrode structures 70. , as previously described, selective etching techniques are used. For example, a suitable etchant for oxides is buffered hydrofluoric acid, and a suitable etchant for nitrides is hot phosphoric acid. Etching of oxide layers 74 and 78 in gate insulating layer 72 removes gate sidewall oxide layer 11.
This is easily achieved without removing the gate sidewall oxide layer 114, since the gate sidewall oxide layer 114 is much thicker. Although some erosion occurs, the gate sidewall oxide layer 114 is not completely removed.

Finally, the molybdenum silicide layer 106, if not removed by previous etching steps.
All overlying masks and protective coatings are removed. The silicon nitride layer 108 or other protective coating on the molybdenum silicide layer 106 is preferably thicker than the nitride layer 76 in the gate insulating layer 72, but may include an oxide layer that is thicker than the first oxide layer 74. Must not be. As a result, the source area 62
The silicon on the surface of (and short circuit region 69) is exposed, and the top of molybdenum silicide 106 is also exposed.

At this point, metal (e.g. aluminum) is placed on the wafer to obtain the finished device shown in FIG.
is deposited by vapor deposition or the like. Thereby, a source terminal 112 made of a metal film in ohmic contact with the source region 62 and the short circuit region 69 and a gate terminal 110 made of a metal film in ohmic contact with the gate electrode structure 70 are formed.

As previously discussed, such metallization automatically separates into an upper portion 110 that constitutes the gate terminal and a lower portion 112 that covers the source region 62. During metallization, the sidewalls of gate electrode structure 70 are partially covered, but this is not a problem due to the presence of gate sidewall oxide layer 114.

Furthermore, a metal coating 58 for the drain terminal is deposited on the substrate 60 at an appropriate time to obtain a completed device.

Although not shown, the completed element of FIG. 18 preferably has a comb-shaped structure when viewed in plan. In this case, source terminal 112 is a recessed comb-shaped structure, with each finger connected at one end to a common source connection pad. On the other hand, the gate terminal 110 is a raised comb structure, with each finger connected at one end to a common gate electrode. These two comb-shaped structures are arranged in an interlocking manner facing each other.

Although the invention has been described in connection with specific embodiments, it will be obvious to those skilled in the art that various modifications and changes may be made. It is, therefore, to be understood that the appended claims are intended to cover all such changes and modifications as do not depart from the spirit and scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the active portion of an encapsulated gate MOSFET manufactured according to a three-mask method according to an embodiment of the present invention, and FIG. 2 is a typical cross-sectional view for manufacturing the device of FIG. 1. FIGS. 3A and 3B are cross-sectional views illustrating initial preparation steps in the method and a selective etching step (providing substantially vertical sidewalls) for etching the wafer of FIG. 2 while minimizing undercuts; 4A and 4B are cross-sectional views illustrating the isotropic etching process, respectively; FIGS. 4A and 4B are cross-sectional views illustrating the vertical ion implantation process for forming shorting regions in the wafers of FIGS. 3A and 3B, respectively; and FIGS. 4A and 4B, respectively; FIG. 6 is a cross-sectional view of the wafer of FIG. 2 after removing the photoresist and implanting the base and source regions;
FIG. 7 is a cross-sectional view showing selective oxidation of the top surface and sidewalls of a polysilicon gate electrode, and FIG. 8 is a cross-sectional view showing the selective oxidation of the top surface and sidewalls of a polysilicon gate electrode. FIG. 9 is a cross-sectional view showing the wafer of FIG. 2 after the regions have been exposed; FIG. 11 is a cross-sectional view of a modified three-mask method for forming an encapsulated gate type device having a molybdenum silicide layer on a polysilicon gate electrode; FIG. 10 is after undercut etching and selective oxidation of the gate electrode; 12 is a cross-sectional view of the wafer of FIG. 10 after removal of the gate insulating layer over the source region and formation of the base and source regions by diffusion of a gaseous impurity source; FIG. FIG. 13 is a cross-sectional view illustrating the initial preparation steps in one mask method for forming a metallized gate electrode in accordance with the present invention;
FIG. 14 is a cross-sectional view showing a first etch step applied to the wafer of FIG. 13 while minimizing undercuts; FIG. 15 is a cross-sectional view showing a vertical implant step to form short regions; FIG. 16 is a cross-sectional view showing the subsequent lateral etching process;
18 is a cross-sectional view showing the step of forming the source and base regions, and FIG. 18 is a cross-sectional view showing the metallization step to form the final metallized gate-type device. In the figure, 50 is a power MOSFET, 52 is a unit cell, 54 is a semiconductor wafer, 56 is a drain region, 58 is a drain terminal, 60 is a substrate, 62 is a source region, 64 is a base region, 66 is a surface, 68
69 is a short circuit region, 70 is a gate electrode,
72 is a gate insulating layer, 74 is a first oxide layer, 7
6 is a nitride layer, 78 is a second oxide layer, 79 is a protective oxide layer, 88 is a metal coating, 91 is a gate electrode layer, 92 is a first corrosion-resistant mask, 98 is a second mask, 100 is a 3rd mask, 102 is a molybdenum silicide layer, 106 is a molybdenum silicide layer, 108
is a silicon nitride layer, 110 is a gate terminal, 112
represents the source terminal, and 114 represents the gate sidewall oxide layer.

Claims (1)

[Claims] 1. (A) After preparing a semiconductor wafer including a first region of one conductivity type having a main surface, a gate insulating layer is formed on the main surface, and a gate insulating layer is formed on the gate insulating layer. preparing the wafer by forming a conductive gate electrode layer; (B) forming an erodible mask having an opening defining the final location of the upper electrode region; (C) performing initial etching on the gate electrode layer in the area defined by the etching mask while minimizing undercuts below the etching mask until at least the gate insulating layer is reached; (D) laterally etching the remaining portion of the gate electrode layer, using the remaining portion of the gate electrode layer as a mask, introducing suitable impurities into the first region to form a shorting region of the opposite conductivity type; (E) forming a gate electrode extending upward from the gate insulating layer and spaced apart along the main surface of the gate insulating layer and the first region; (E) using the gate electrode as a mask; Introducing an impurity suitable for forming the base region of the opposite conductivity type and the upper electrode region of the one conductivity type into the first region located between the gate electrodes, and then diffusing the introduced impurity. By giving proper positions and shapes to the base region and the upper electrode region, the base region has the opposite conductivity type between the upper electrode region and the first region within the main surface. (F) the active portion of the strip is located below at least a portion of at least one gate electrode while being separated by the gate insulating layer; oxidizing and then (G) forming a top electrode region terminal comprising a metal film in ohmic contact with the top electrode region and the short circuit region and a gate terminal comprising a metal film in ohmic contact with the gate region; A self-aligned manufacturing method of an insulated gate semiconductor device including an integrated short circuit, characterized in that 2. The method of claim 1, wherein said step of introducing into said first region an impurity suitable for forming a shorting region comprises ion implantation. 3. The method of claim 2, wherein said ion implantation is performed prior to removal of said gate insulating layer, so that said ion implantation is performed through said gate insulating layer. 4. The method of claim 1, wherein said step of introducing suitable impurities to form the base region and the top electrode region comprises ion implantation. 5. The method of claim 4, wherein said ion implantation is performed prior to removal of said gate insulating layer, so that said ion implantation is performed through said gate insulating layer. 6. The method of claim 4, wherein said step of introducing impurities suitable for forming at least the base region comprises diffusion of a gaseous impurity source. 7. The method of claim 1, wherein said step of introducing impurities suitable to form the base region and the top electrode region comprises diffusion of a gaseous impurity source. 8. In the step of preparing the wafer,
Following the formation of the conductive gate electrode layer, a heat-resistant metal silicide layer forming part of the final gate electrode is formed on the gate electrode layer, and during the step of oxidizing at least the sidewalls of the gate electrode, 2. The method of claim 1, wherein at least the exposed sides of the heat-resistant metal silicide portion of the gate electrode are oxidized. 9. The method of claim 8, wherein said step of introducing suitable impurities to form the base region and the top electrode region comprises ion implantation. 10. The method of claim 8, wherein said ion implantation is performed prior to removal of said gate insulating layer, such that said ion implantation is performed through said gate insulating layer. 11. The method of claim 8, wherein said step of introducing impurities suitable for forming at least the base region comprises diffusion of a gaseous impurity source. 12. The method of claim 8, wherein said step of introducing impurities suitable to form the base region and the top electrode region comprises diffusion of a gaseous impurity source.