JPH0363219B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor device.

Conventionally, as shown in Figure 1, so-called SOS uses sapphire for the substrate to achieve dielectric separation between the substrate and the element.
A semiconductor device with a (Silcon on Sapphire) structure is used. As shown in the figure, for example, in the case of a complementary MOS transistor, this semiconductor device
An N-type semiconductor layer 2 is formed in a predetermined area on the sapphire substrate 1.
, a source 3 and a drain 4 are formed thereon, and a P-channel transistor 7 is formed with an extraction electrode 5 and a gate electrode 6 connected to each other, and a P-type semiconductor layer 8 is formed on the sapphire substrate 1 and a source 9 is formed. and an extraction electrode 1 which forms a drain 10 and is connected to each other.
1 and an N-channel transistor 13 on which a gate electrode 12 is formed. P channel transistor 7 and N channel transistor 13 are isolated by an oxide film 14. Further, a protective film 14 made of phosphosilicate glass (PSG) is formed on the surface thereof. In addition, 6a, 1 in the figure
2a is a gate oxide film, and 6b and 12b are gates. The semiconductor device 15 having such an SOS structure has the following drawbacks. Sapphire substrate 1
The price is higher because of the use of Aluminum, which is a component of the sapphire substrate 1, has an 800~
Due to the high-temperature heat treatment at 1200° C., impurity diffuses into the semiconductor layers 2 and 8 on the sapphire substrate 1, making it extremely difficult to control the impurity concentration within the semiconductor layers 2 and 8. As a result, desired electrical characteristics may not be obtained.

The present invention has been made in view of the above problems, and provides a semiconductor device that can achieve high-speed operation with low power consumption and is capable of reducing manufacturing costs.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2F is a cross-sectional view of one embodiment of the present invention. In the figure, 20 is a P conductivity type semiconductor substrate.
A P conductivity type element region 21 and an N conductivity type element region 22 are formed in a predetermined region of the semiconductor substrate 20 . Each of the element regions 21 and 22 is separated by a dielectric region 23 formed to surround the periphery and the region immediately below. Thin oxide film 23c (500
The second dielectric region 23a surrounding the device regions 21 and 22 via the dielectric layer 23c (23c) is formed of a dielectric material made of a compound of boron, phosphorus, and silicon, for example. The first dielectric region 23b directly below the element regions 21 and 22 is formed of an oxide layer made of silicon dioxide, for example, and is continuous directly below the dielectric and the element regions 21 and 22. This dielectric region 23 is connected to each element region 21, 22.
is completely dielectrically separated from the semiconductor substrate 20. The dielectric region 23 may be any material that can be formed, such as the aforementioned dielectric or oxide layer, as long as it exhibits such a complete dielectric isolation effect. The depth and shape of the second dielectric region 23a made of a dielectric and the depth of the first dielectric region 23b made of an oxide layer can be set as appropriate according to the specifications of the elements to be formed in the element regions 21 and 22. is desirable.

A source 24 and a drain 25 of N conductivity type are formed in the element region 21 of P conductivity type. A gate 27a and a gate lead electrode 27 are formed on the element region 21 between the source 24 and the drain 25 with a gate oxide film 26 interposed therebetween. On the source 24 and drain 25, there are extraction electrodes 2 connected to each other.
8 is formed.

A source 29 and a drain 30 of P conductivity type are formed in the element region 22 of N conductivity type. A gate 32a and a gate lead electrode 32 are formed on the element region 22 between the source 29 and the drain 30 with a gate oxide film 31 interposed therebetween. source 2
9. An extraction electrode 33 is formed on the drain 30.

An N-channel transistor 34 formed in a P-conductivity type device region 21 and an N-conductivity type device region 22
The P-channel transistor 35 formed in the dielectric region 23 and the oxide film 36 formed thereon
The elements are separated by each transistor 3
A protective film 37 made of phosphorus silicate glass is formed on the oxide film 36 and the oxide film 36 .

In the semiconductor device 38 configured in this manner, each of the element regions 21 and 22 includes a second dielectric region 23a made of a dielectric with an oxide film 23c interposed therebetween, and a first dielectric region 23a made of an oxide layer formed in series immediately below the second dielectric region 23a. Since it is completely dielectrically isolated from the semiconductor substrate 20 by the dielectric region 23b, parasitic capacitance can be made extremely small. As a result, high-speed operation can be achieved, and power consumption during operation can be drastically reduced. Furthermore, by forming the element regions 21 and 22 in a structure in which they are separated by a second dielectric region 23a made of a dielectric material, the shape precision of the element regions 21 and 22 can be increased. The area required for this can be reduced and the degree of integration can be significantly improved. Furthermore, since a sapphire substrate is not used for the semiconductor substrate 20, manufacturing costs can be reduced.

Next, a method for manufacturing this semiconductor device 38 will be explained with reference to FIGS. 2A to 2F.

First, as shown in FIG. 2A, a photoresist film 39, for example, is formed to a thickness of 1 to 2 μm in a predetermined region of a semiconductor substrate 20 made of single crystal silicon. Then,
An opening 40 is formed in the photoresist film 39 by photolithography so that a portion of the semiconductor substrate 20 corresponding to the intended element formation region 21a remains. Next, using this photoresist film 39 as a mask, the semiconductor substrate 20 is subjected to anisotropic etching such as reactive, ion, etching (RIEReactive ion etching), etc., to form the element region 2.
1 and 22 are formed.

Next, as shown in FIG.
After removing the oxide film 42, an oxide film 42 having a thickness of about 300 Å is formed on the entire exposed surface of the semiconductor substrate 20 by thermal oxidation. Next, a protective film 43 made of silicon oxide film is formed on the surface of this oxide film 42 by CVD.
(Chemical Vapor Deposition) method, the thickness is approx.
Forms 2500Å.

Next, as shown in FIG. 4C, a resist film is left on the regions 21a and 22a where the elements are to be formed by photolithography, and the bottom 41a of the groove 41 is etched by anisotropic etching.
The protective film 43 and the oxide film 42 are removed from the portion corresponding to the bottom portion 41a to expose the bottom portion 41a. Here, the bottom portion 41a is exposed in the next step.
This is to form a first dielectric region 23b that is continuous and integral with the region 21a and 22a directly below the region 21a and 22a where the elements are to be formed. Therefore, only the protective film 43 may be removed and the oxide film 42 may remain.

Next, as shown in Figure D, this is subjected to thermal oxidation. The regions 21a and 22a where the elements are to be formed are covered with the protective film 4.
Since only the bottom portion 41a of the groove 41 is exposed, oxidation proceeds from the bottom portion 41a toward the region below the bottom portion 41a. Further, it progresses laterally and upward in a concentric circle (in the cross-sectional view) centered around the bottom periphery 41b. As a result, the bottom 4 of the groove 41
Immediately below 1a and planned element formation regions 21a and 22a
A first dielectric region 23b made of an integrally continuous oxide layer can be formed in a region immediately below the oxide layer.

Next, after removing the protective film 43,
A thin oxide film 23c is formed, and as shown in FIG.
For example, phosphorus (P) is selectively introduced as an impurity into the desired element formation region 22a to form an N conductivity type element formation region 22a.

After that, as shown in FIG.
A gate 27a, a gate lead-out electrode 27, etc. are formed to form an N-channel transistor 34, and a P-conductivity type source 29, a P-conductivity type source 29,
A drain 30, a gate 32a, a gate lead-out electrode 32, etc. are formed to form a P channel transistor 35, and a semiconductor device 38 is obtained.

In the embodiment, a so-called MOS type semiconductor device 38 in which an N-channel transistor 34 and a P-channel transistor 35 are formed in the element regions 21 and 22 has been described, but the present invention is also applicable to other devices as shown in FIG. An N-type base 51 in the element region 50;
A so-called bipolar semiconductor device 54 has a P-type emitter 52 and a collector 53, or as shown in FIG. It goes without saying that the present invention can also be applied to a bipolar type semiconductor device 65 or the like in which a type emitter 63 and a collector 64 are formed. Note that the same parts as those in the example are given the same numbers.

As explained above, in the semiconductor device according to the present invention, the element region is almost completely dielectrically isolated from the semiconductor substrate by the first and second dielectric regions, and a sapphire substrate is not used. This has remarkable effects such as being able to achieve high-speed operation with low power consumption and reducing manufacturing costs.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device, FIGS. 2A to 2F are explanatory diagrams showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps, and FIGS. 3 and 4 FIG. 2 is a cross-sectional view of another embodiment of the present invention. 20...Semiconductor substrate, 21, 22, 50, 61
...Element region, 23...Dielectric region, 23a...
Second dielectric region, 23b...first dielectric region, 2
3c... Oxide film, 24, 29... Source, 25,
30...Drain, 26, 31... Gate oxide film, 27, 32... Gate extraction electrode, 27a, 3
2a... Gate, 28, 33... Extraction electrode, 34
... N channel transistor, 35 ... Channel transistor, 36 ... Oxide film, 37 ... Protective film, 38 , 54 , 65 ... Semiconductor device, 51, 6
2...Base, 52, 63...Emitsuta, 53,
64...Collector.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of one conductivity type, a groove formed in a predetermined region of the semiconductor substrate to have vertical side surfaces, an element region surrounded by the groove, and the element region and the groove. a first dielectric region made of an oxide layer integrally formed directly under the bottom of the groove, a second dielectric region made of boron, phosphorus, and silicon oxide filled in the groove, and the element region. A semiconductor device comprising: an oxide film interposed between the second dielectric region and the element region; and an element formed on the element region. 2. Claim 1, wherein the element is a bipolar transistor or a MOS transistor.
1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1, wherein the element is a diode or a resistor.