JPH0363759B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an automatic performance device that corrects the progress of an automatic performance in response to the timing of operating keys or the like. Conventional devices of this type have a system that compares the timing at which keys should be pressed during automatic performance (performance timing) with the timing at which keys are pressed by the performer, for the purpose of key pressing practice for beginners and performance improvement for experts. When the key press timing is earlier than the performance timing, the automatic performance is advanced rapidly or instantaneously, and when the key press timing is later than the performance timing, the automatic performance is paused until the key press timing is reached. There is also a system that attempts to match the progress of the performance by key depression and the automatic performance. However, although such conventional devices compare the performance timing and the key press timing and correct the progress of automatic performance each time, the deviation of the key press timing from the performance timing is originally minute; This is a case where it is meaningless to correct the progress of automatic performance by measuring such a deviation (the performer is expecting a slight deviation in tempo, and the deviation itself is not what the performer intended, i.e. (In some cases, the tempo was not intended to be fast or slow.) This actually made the device more complicated. This invention was made in view of the above circumstances.
To provide a simple automatic performance device that follows and controls the progress of an automatic performance by considering only whether the operation timing is early or late with respect to the performance timing. According to this invention, the performance timing and the operation timing are compared, it is detected whether the operation timing is earlier or later than the performance timing, and the tempo of automatic performance is controlled based on the number of times the operation timing is early or late. , the progress of automatic performance follows the operation timing. Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings. FIG. 1 shows a magnetic tape 1a formed on a musical score 1.
The data reading device 2 reads recorded data, and the accompaniment keyboard 4 has an automatic melody sound performance function that automatically plays melody sounds based on this read data, and an automatic obbligato sound performance function that automatically plays obbligato sounds. Accompaniment tone automatic performance function that forms accompaniment tones such as automatic chord tones and automatic bass tones based on key presses and automatically plays these accompaniment tones, and automatically plays rhythm tones corresponding to the rhythm specified by appropriate means. This figure shows an embodiment in which the present invention is applied to an electronic musical instrument equipped with an automatic rhythm tone performance function. This electronic musical instrument also has a key display function that displays the next key to be pressed on the melody keyboard 3 based on the data read by the data reading device 2 for melody performance practice. The data reading device 2 reads obligado and melody data corresponding to the obbligado performance and melody performance from the magnetic tape 1a of the musical score 1, and transfers the read data to the oblicard data memory 5 and melody data memory 6, respectively. Note that when reading data, the data write/read control circuits 7 and 8 each enter a write mode, designate the write address of each memory 5 and 6, and write obligate data and melody data to each memory 5 and 6. Here, Table 1 shows an example of the data format corresponding to the obligate data and the melody data.

[Table] That is, each data Di (i = 1...n) consists of pitch data TL1 and note length data TL2, and pitch data TL1 includes, for example, a 4-bit note code NC indicating a note and a 3-bit note code indicating an octave. The octave code OC is composed of a total of 7 bits of data, and the code length data is composed of, for example, 8 bits of data. An example of note length data is shown in Table 2.

[Table] Also, for rests, all bits of pitch data are set to “0”.
End data Dn indicating the end of data is represented by setting all bits of pitch data TL1 and note length data TL2 to "1". Reading of each data from obbrigade data memory 5 and melody data memory 6 is performed by data write/read control circuits 7 and 8, respectively. First, to start automatic performance, turn on the start switch 9 and turn on the standby flip-flop.
At the same time as setting FF1, the performance flip-flop FF2 is reset. When standby flip-flop FF1 is set, its output terminal Q
A signal "1" is applied to the differentiating circuit 10 and the delay flip-flop DF1. As a result, the differentiating circuit 10 outputs a preset signal ΔPR (one pulse), and the delay flip-flop DF1
After delaying this signal "1" for a predetermined time, it is added to the AND circuit A1 to enable the AND circuit A1. The preset signal .DELTA.PR is applied to the data write/read control circuits 7 and 8, puts each circuit 7 and 8 into the read mode, and sets the internal address counter to the initial address. As a result, the first stored data is read out from the obligate data memory 5 and the melody data memory 6. At this time, the preset signal ΔPR
is connected to each load terminal of latch circuits L1, L2 and L3, L4 via OR circuits OR1 and OR2.
Since the data is added to the LD, the latch circuit L1 latches the first obli-card data, and the latch circuit L3 latches the first melody data. On the other hand, since the performance flip-flop FF2 has been reset by turning on the start switch 9, it does not output the play signal PL ("1") but outputs the signal "0".
Add to inverter IN1. Inverter IN1 applies a signal ("1") obtained by inverting signal "0" to reset terminal R of note length counter 11 via OR circuit OR3, and also to reset terminal R of note length counter 11 via OR circuit OR4. , is added to the reset terminal R of the counter 13 and the address counter 14, and is also applied to the flip-flops FF3 and FF3 via the OR circuits OR5 and OR6.
It is added to the reset terminal R of FF4. Therefore, when performance flip-flop FF2 is reset, note length counters 11 and 12, counter 13, address counter 14, and flip-flops FF3 and FF4 are all reset. Also, pitch data TL1 of the melody data latched by the latch circuit L3 is applied to the key display device 15 and the comparator 16, and the key display device 1
5 displays the key of the first note of the melody performance (the key to be pressed first) by lighting up the display lamp disposed on that key. In this state, when the performer presses a key on the melody keyboard 3 whose display lamp is lit, a key code KC (4-bit note code) indicating the pressed key is generated.
NC and 3-bit octave code OC) is output. This key code KC is added to the melody tone forming circuit 17 to form a musical tone signal corresponding to the melody tone indicated by this key code KC, which is sent to the speaker 19 via the amplifier 18.
In addition to this, it is also pronounced as a melody sound. Further, the key code KC output from the melody keyboard 3 is applied to the B inputs of the comparators 20 and 16, respectively. The pitch data TL1 of the data latched in the latch circuit L3 is applied to the A input of the comparator 16 as described above, and this A
Pitch data TL1 added to the input (indicating the note to be pressed) and key code KC added to the B input
(indicates the pressed note) matches the matching terminal EQ
Outputs a match signal from. This coincidence signal is applied to AND circuit A2. The other input of AND circuit A2 is any key-on signal AKON (signal that becomes "1" when any key is pressed) output from OR circuit OR7 which takes the OR condition of key code KC output from melody keyboard 3. ) to differentiator circuit 2
A signal differentiated by 1 is applied, and under the condition that a key whose display lamp is lit is pressed, this AND circuit A2 outputs a pulse (key press coincidence signal) KEQ synchronized with the key press. This key press coincidence signal KEQ is sent to the OR circuit 8 and the select switch 2.
2 to AND circuits A3 and A4, and also to AND circuit A1 and OR circuit OR.
9 to the reset terminal R of the standby flip-flop FF1. AND circuit A1 is a delay flip-flop
Since it is enabled to operate by DF1, it outputs a pulse signal ΔPL upon input of the foot key coincidence signal KEQ, and also applies this pulse signal ΔRL to the set terminal S of the performance flip-flop FF2. The performance flip-flop FF2 uses this pulse signal ΔPL.
is set by PL, and outputs the play signal PL.
On the other hand, the standby flip-flop FF1 is reset and the AND circuit A1 is made inactive thereafter. Note that since flip-flops FF3 and FF4 have both been reset, AND circuits A3 and A4 are both inoperable. The pulse signal ΔPL output from AND circuit A1 is OR circuit OR10 and OR11, respectively.
The data write/read control circuits 7 and 8 are connected to the data write/read control circuits 7 and 8, and their internal address counters are advanced by one step. As a result, the obliger data memory 5
Then, the second data is read out from the melody data memory 6. In addition, the pulse signal ΔPL is passed through the OR circuits OR10 and OR1 to the latch circuit L.
1 and L2, the latch circuit L1 latches the second read obbligor data, and the latch circuit L2 latches the first obbrigade data latched by the latch circuit L1. Similarly, the pulse signal ΔPL is applied to the load terminals LD of latch circuits L3 and L4 via OR circuits OR11 and OR2, so latch circuit L3 latches the second read melody data, and latch circuit L4 latches the second read melody data. Latch the first melody data latched at L3. The obligated data latched by the latch circuit L2 is applied to the end detection circuit 23, and
Of the obbligard data, pitch data TL1 is applied to the obbligado tone forming circuit 24, and note length data TL2 is applied to the A input of the comparator 25. The end detection circuit 23 detects the end of the data when all bits of the obbligard data (pitch data TL1 + note length data TL2) are "1", and outputs an end signal.
Output FIN. This end signal FIN is applied to the reset terminals R of the standby flip-flop FF1 and performance flip-flop FF2 via OR circuits OR9 and OR12, respectively, and resets the standby flip-flop FF1 and performance flip-flop FF2. This ends the automatic performance. The obbligado sound forming circuit 24 forms a musical sound signal corresponding to the obbligado sound indicated by the input pitch data TL1, and applies this to the speaker 19 via the amplifier 18 to generate the obbligado sound. Of the second melody data latched by the latch circuit L3, the pitch data TL1 is the key display device 1.
5 and comparator 16, key display device 15
lights up the key of the second tone of the melody device. Note that this lighting display is performed in the same manner as in the case described above. Also, of the first melody data latched by the latch circuit L4, pitch data TL1 is added to the A input of the melody tone forming circuit 26 and comparator 20, respectively, and note length data TL2 is added to the A input of the comparator 27. It will be done. The melody sound forming circuit 26 forms a musical sound signal corresponding to the melody sound indicated by the input pitch data TL1, and applies this signal to the speaker 19 via the amplifier 18 to generate an automatic melody sound. Note that the key code KC is added to the melody sound forming circuit 17 based on the key pressed on the melody keyboard 3, and the latch circuit L is added to the melody sound forming circuit 17 based on the pressed key.
Of course, this is the same data as the pitch data TL1 which is latched at step 4 and applied to the melody tone forming circuit 26. Therefore, either make the manual melody sound and the automatic melody sound different tones, or
It is preferable to reduce the volume of the automatic melody sound. In addition, the play signal PL generated from the performance flip-flop FF2 is applied to the inverter IN1, and the inverted signal becomes "0".
The note length counters 11 and 12, the counter 13, and the address counter 14 become capable of counting. A tempo oscillator 28 is connected to the clock terminal CK of the note length counters 11 and 12 and the address counter 14.
A tempo clock TCL has been added since. In the initial state, the tempo oscillator 28 outputs a tempo clock TCL with a frequency preset by the tempo setter 29, and then outputs a tempo clock TCL with a frequency preset by the tempo setting device 29.
The tempo of automatic performance in this embodiment is determined by correcting the frequency of the tempo clock TCL using a correction signal outputted from (dotted chain line). Note that details will be explained later. The address counter 14 is connected to the tempo clock.
Count TCL and store the counted value in pattern memory 3
Pattern memory 3 as address signal for 1
Add to 1. The pattern memory 31 stores a plurality of bass patterns, chord patterns, and rhythm patterns for each rhythm. In this pattern memory 31, the above patterns to be read are set in advance in correspondence with the rhythm selected by a rhythm selection switch (not shown), and the base pattern signal BP and base pattern signal Read out the sound generation timing signal BT, chord tone generation timing signal CT, and rhythm pattern signal RP.
Here, the bass pattern signal PR is information indicating the pitch relationship to the root note of the automatic bass note to be produced (this root note is specified in relation to the keys pressed on the accompaniment keyboard 4), and timing signal
BT is a signal indicating the generation timing of the automatic bass tone, and the chord tone generation timing signal CT indicates the generation timing of the automatic chord tone (this chord tone is specified in relation to the foot keys on the accompaniment keyboard 4). The rhythm pattern signal RP is information indicating the type of rhythm sound to be generated and the timing of its generation. The accompaniment sound forming circuit 32 adds the key code representing the root note of the automatic bass sound output from the accompaniment keyboard 4 and the bass pattern signal BP to form a key code representing the automatic bass sound, and adds this key code to the base pattern signal BP. to automatically form a musical tone signal corresponding to the bass tone,
This musical tone signal is used as the bass tone generation timing signal.
Open/close envelope control and output according to BT,
Also, a musical tone signal corresponding to the automatic chord tone is formed from the key code indicating the automatic chord tone outputted from the accompaniment keyboard 4, and this musical tone signal is outputted after being subjected to opening/closing envelope control according to the chord tone generation timing signal CT. . Musical tone signals indicating these automatic accompaniment tones are applied to a speaker 19 via an amplifier 18, and are emitted as automatic accompaniment tones. Further, the rhythm pattern signal RP output from the pattern memory 31 is applied to the rhythm sound source circuit 33. The rhythm sound source circuit 33 generates rhythm sound signals representing various rhythm instrument sounds in accordance with the input rhythm pattern signal PR, and applies the signals to the speaker 19 via the amplifier 18 to generate automatic rhythm sounds. On the other hand, note length counters 11 and 12 count the tempo clock TCL output from tempo oscillator 28, and add the counted values to the B inputs of comparators 25 and 27, respectively, as note length data. In the comparator 25, the code length data of the obligate data latched by the latch circuit L2 is applied to the A input of the comparator 25. In this case, the note length data TL2 applied to the A input of the comparator 25 is note length data regarding the first note of the obbligato note, as is clear from the above explanation. The comparator 25 compares the note length data TL2 applied to the A input with the counted value of the note length counter 11 which started counting from the timing of the first key press, and when both data match, a signal "1" is sent to the line l1. Outputs a pulse signal. This pulse signal is applied to the data write/read control circuit 7 via the OR circuit OR10, and advances the internal address counter by one step. As a result, the third data is read out from the obligate memory 5.
In addition, this pulse signal is OR circuit OR10, OR
1 to the load terminals LD of latch circuits L1 and L2, the latch circuit L1 latches the third read obbliged data, and the latch circuit L2 latches the 2nd data latched by the latch circuit L1.
Latch the th obbligard data. Also,
This pulse signal is applied to the reset terminal R of the note length counter 11 via the OR circuit OR3, and resets the note length counter 11. In this way, the obligate data is read out sequentially, and automatic obbligado performance is performed. Furthermore, the reading of melody data is basically performed in the same manner as the reading of the obligate data. That is, the comparator 27 is connected to the latch circuit L4.
The note length data TL2 of the melody data latched and added to the A input is compared with the counted value of the note length counter 12, and a pulse signal of signal "1" is sent to line l2 where both data match and A=B. Output.
This pulse signal is applied to the data write/read control circuit 8 via the OR circuit OR11, and advances the internal address counter by one step. This results in
The third data is read from the melody data memory 6. Also, this pulse signal is an OR circuit.
Since it is applied to the load terminals LD of latch circuits L3 and L4 via OR11 and OR2, latch circuit L3 latches the third melody data read out, and latch circuit L4 latches the third melody data read out by latch circuit L3. Latch the melody data.
Further, this pulse signal is applied to the reset terminal R of the note length counter 12 via the OR circuit OR4, and resets the note length counter 12. In this way, the melody data is sequentially read out, and the melody is automatically played and the key to be pressed is displayed. Further, the pulse signals outputted from the comparator 27 via the line 12 are each output from an OR circuit OR5.
through the reset terminal R of flip-flop FF3 and the set terminal S of flip-flop FF4.
added to. Further, the comparator 27 compares the note length data TL2 of the melody data and the note length data corresponding to the sixteenth note of the difference (A-B) between the count values of the note length counter 12, and determines whether the difference (A-B) is If it becomes smaller than the note length data corresponding to a 16th note, line l3
The note length counter 12 outputs the signal "1" to the set terminal S of the flip-flop FF3 via It is output to the reset terminal R of the flip-flop FF4 through the reset terminal R of the flip-flop FF4. The operations of flip-flops FF3 and FF4 will now be explained with reference to the timing chart shown in FIG. Flip-flop FF3 is shown in Figure 2d.
As shown in FIG.
2 (FIG. 2a). Further, flip-flop FF4 is set by the pulse signal generated on line 12 as shown in FIG. 2e, and reset by the rising edge of the signal generated on line 14 (FIG. 2c). Note that flip-flop FF3 is set before the timing at which the key should be pressed (Fig. 2a),
Flip-flop FF4 is set after the key depression timing, and the set times T1 and T2 correspond to the length of a 16th note. Therefore, AND circuits A3 and A4 are enabled only while flip-flops FF3 and FF4 are set, respectively. On the other hand, with the first key depression on the melody keyboard 3, the pitch data TL1 of the first melody data is added to the A input of the comparator 20, and the pitch data TL1 of the first melody data is added to the A input of the comparator 20.
Pitch data TL1 of the second melody data is added to the A input. Note that, like the comparator 16, the comparator 20 is configured so that the key code KC output from the melody keyboard 3 is added to its B input, and the pitch data added to the A input.
When the key code KC applied to the TL1 and B inputs match (A=B), a match signal is applied to the AND circuit A5. The AND circuit A5 is configured such that the signal output from the differentiation circuit 21 is added to other inputs every time a key is pressed on the melody keyboard 3, and a pulse (key press coincidence signal) KEQ synchronized with the press of a key is added to the other input. is outputted via the OR circuit OR8 and the select switch 22. Here, the case where a key is pressed for the second time on the melody keyboard will be explained. (1) When the key press timing is earlier than the key press timing. In this case, the comparator 27 still outputs line l2.
A pulse signal is not outputted to , and the address counter of the data write/read control circuit 8 is not advanced. Therefore, the pitch data TL1 of the first melody data is applied to the A input of the comparator 20, and the pitch data TL1 of the second melody data is applied to the A input of the comparator 16. At this time, when a second key is pressed on the melody keyboard 3, a match signal is output from the comparator 16, and at this key press timing, a key press match signal KEQ is sent from the AND circuit A2 via the OR circuit OR8 and the select switch 22. and output to AND circuits A3 and A4. Furthermore, if the key press timing is earlier than the key press timing (within 16th note length from the key press timing), flip-flop FF3 is set, as is clear from Figure 2 (d). , AND circuit A3
Since only the key depression key is enabled, the key press coincidence signal KEQ is outputted via the AND circuit A3. (2) When the key press timing is later than the key press timing: In this case, the comparator 27 has already detected the line l2.
A pulse signal is output to , and the address counter of the data write/read control circuit 8 is advanced by one step. Therefore, the pitch data TL1 of the second melody data is input to the A input of the comparator 20.
is added, and pitch data TL1 of the third melody data is added to the A input of the comparator 16. At this time, when a second key is pressed on the melody keyboard 3, a match signal is output from the comparator 20, and at this key press timing, a key press match signal KEQ is sent from the AND circuit A5 via the OR circuit OR8 and the select switch 22. and output to AND circuits A3 and A4. Furthermore, if the key press timing is later than the key press timing (at the latest, within the length of a 16th note from the key press timing), flip-flop FF4 is set, as is clear from Figure 2 e. Since only the AND circuit A4 is enabled, the key press coincidence signal KEQ is outputted via the AND circuit A4. In this way, when the key press timing is earlier than the key press timing, the AND circuit A3 outputs the key press coincidence signal KEQ, and when the key press timing is later than the key press timing, the AND circuit A4 outputs the key press coincidence signal KEQ. A key press coincidence signal KEQ is output from the key press key matching signal KEQ.
Note that the key press coincidence signal KEQ other than the length of the 16th note before and after the key press timing is not output to the subsequent tempo control circuit 30 because AND circuits A3 and A4 are both inoperative. That is, such a key press coincidence signal KEQ is regarded as a mistouch, and is excluded from the tempo control in the tempo control circuit 30. The tempo control circuit 30 outputs correction data for correcting the oscillation frequency of the tempo clock TCL output from the tempo oscillator 28, and uses this correction data to control the tempo of automatic performance according to the present invention. The counter 13 has its count value reset to "0" until the first key is pressed on the melody keyboard, and a signal "0" is output from the carry output terminal C. . This signal "0" is applied to the A input select terminal SA of the selector 34 and the inverter IN6. This results in
Selector 34 selects B input and inverter IN
6 inverts this signal "0" and adds AND circuit A6 to enable AND circuit A6. Correction data “0” is added to the B input of the selector 34 from the 0 value generator 35, and the selector 3
4 outputs this correction data "0" to the tempo oscillator 28. Therefore, the tempo oscillator 28 does not correct the oscillation frequency of the tempo clock TCL using the correction data applied from the selector 34, but instead generates the tempo clock TCL at the frequency previously set by the tempo setter 29. Here, if the timing of the second or subsequent key depression on the melody keyboard 3 is earlier than the timing at which the key should be depressed, a signal "1" is output from the AND circuit A3. This signal "1" is applied to the input terminal IN of the n-stage, 1-bit shift register 36, and is also applied to the shift terminal of the shift register 36 and the AND circuit A6 via the OR circuit OR13. As a result, the shift register 36 outputs a signal "1".
Enter to shift by one step. Also, AND circuit A
6 is made operable by the inverter A6, so the signal "1" is sent to the clock terminal CK of the counter 13, causing the counter 13 to count up. Further, if the timing of the second or subsequent key depression on the melody keyboard 3 is later than the timing at which the key should be depressed, a signal "1" is output from the AND circuit A4. This signal "1" is applied to the shift terminal of the shift register 36 and the AND circuit A6 via the OR circuit OR13. This allows the shift register 36
inputs the signal "0" from the AND circuit A3 and shifts by one stage. Also, the AND circuit A6 outputs the signal "1" to the clock terminal CK of the counter 13 in the same manner as described above.
and causes the counter 13 to count up. When the counter 13 counts the number of stages n of the shift register 35 as described above, the counter 1
3 applies a signal "1" from the carry output terminal C to the A input select terminal SA of the selector 34 and the inverter IN6. This causes the selector 34 to
The input is selected, and the inverter IN6 inverts the signal "1" and applies it to the AND circuit A6, disabling the AND circuit A6. At this time, the shift register 35 inputs the signal "1" or "0" to all stages, and the signal "1" is output to the quick key press number detection circuit 37.
The signal “0” is output to the delayed key press count detection circuit 38. The early key press frequency detection circuit 37 detects the number of times the key press timing is earlier than the key press timing by counting the signal "1" in the n stage, and adds this counted value to the A input of the subtracter 39. Similarly, the late key count detection circuit 38 detects the number of times the key press timing is later than the key press timing by counting the signal "0" through n stages, and inputs this counted value to B of the subtractor 39. Add to. The subtracter 39 subtracts the count value of the B input from the count value of the A input, and applies this subtracted value (AB) to the tempo oscillator 28 via the A input of the selector 34 as tempo correction data. The tempo oscillator 28 consists of a variable frequency divider that divides the frequency of a high-speed clock pulse (not shown), and generates a tempo clock TCL of an appropriate frequency based on the division ratio data input from the tempo setter 29 and the correction data input from the selector 34. Output. That is, the tempo oscillator 28 includes a subtracter that subtracts correction data from the frequency division ratio data, and uses this subtracted value as new frequency division ratio data to divide the high speed clock pulse and output the tempo clock TCL. Therefore, when the correction data is "positive" (the number of fast key presses is greater than the number of slow key presses), the new frequency division ratio data is higher than the frequency division ratio data output from the tempo setter 29 in advance. becomes smaller, and the tempo clock
TCL oscillation frequency increases. If the correction data is "negative", the new frequency division ratio data will be larger than the frequency division ratio data previously output from the tempo setter 29, and the oscillation frequency of the tempo clock TCL will become lower. As described above, the oscillation frequency of the tempo clock is corrected in accordance with the key press timing, so that the progress of the automatic performance automatically follows the key press timing. Note that the number of stages n of the shift register 36 is 5.
20th place is appropriate. In addition, by switching the select switch 22 to the opposite position from the state shown in the figure, automatic performance as described above can be performed even when there is no key depression coincidence (match between the pitch data TL1 and the key code KC output from the melody keyboard 3). Progress control is possible. FIG. 3 shows another embodiment of an electronic musical instrument to which the present invention is applied. This electronic musical instrument has each of the functions of the electronic musical instrument shown in FIG. If the key press timing is too early, the oscillation frequency of the tempo clock TCL will be increased by 25%, and if the key press timing is later than the key press timing, the tempo clock TCL oscillation will be stopped until the key press is made, in other words, automatic performance will be stopped. It is equipped with Note that common parts in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Hereinafter, operations will be described when the key press timing for the second tone is earlier than the key press timing, when they match, and when the key press timing is later than the key press timing. (1) When the key press timing is earlier than the key press timing When the key press timing is earlier than the note length data TL2 latched in the latch circuit L4,
The count value of the note length counter 120 is the note length data mentioned above.
The key press coincidence signal KEQ is generated before reaching TL2. Therefore, at the timing when the key press coincidence signal KEQ is generated, a signal "1" is generated from the comparator 270 on line l6 (signal "1" is generated when the B input is smaller than the A input). ,
The AND condition of the key press coincidence signal KEQ, the signal on line l6, and the signal obtained by inverting the rest detection signal RD from the rest detection circuit 40 by the inverter IN7 (in this case, the rest detection signal RD is set to "0") is The output of the AND circuit A7 becomes "1".
The output signal "1" of the AND circuit A7 is applied to the set terminal S of the flip-flop FF30 and the fast key input terminal F of the tempo control circuit 30.
As a result, flip-flop FF30 is set, and fast forward signal FF is output from output terminal Q. This fast forward signal FF is the tempo oscillator 2
80, the oscillation frequency of the tempo clock TCL output from the oscillator 280 is increased by 25%, and the automatic performance proceeds rapidly. Further, the tempo control circuit 30 has a circuit configuration similar to that shown in FIG.
A tempo clock output from the tempo oscillation base 280 based on the difference between the number of times a signal is applied to the fast key press input terminal F (the number of fast key presses) and the number of times that the signal is applied to the slow key input terminal S (the number of slow key presses). It corrects the oscillation frequency of the tempo clock TCL, and outputs correction data to the tempo oscillator 280 in order to increase the oscillation frequency of the tempo clock TCL. Further, the output of flip-flop FF30 is applied to AND circuit A8 via delay flip-flop DF2. The AND circuit A8 has the other input the line l5 output from the comparator 270.
A note length matching signal obtained by differentiating the signal of
LEQ has been added. Therefore, when A=B is established in the comparator 270 and the code length match signal LEQ is generated, the AND condition is established in the AND circuit A8, and the signal "1" (pulse signal) is satisfied.
Output. This signal is transmitted to the data write/read control circuit 8 and the OR circuit via the OR circuit OR14.
Latch circuit L3, L via OR14, OR2
4 and performs the next read. In addition, flip-flop FF3 outputs the fast-forward signal FF.
0 reset terminal R has the output of AND circuit 8 and
The output of the OR circuit OR15 which takes the OR condition for the PL signal is added, and in this case, the AND circuit A
The flip-flop FF30 is reset by the output of 8, and the fast forward signal FF becomes "0". In other words, the key press timing is determined by the latch circuit L4.
If the note length data TL2 is earlier than the latched note length data TL2, the automatic performance is rapidly advanced until the count value of the note length counter 120 matches the note length data TL2, and the fast key input terminal F of the tempo control circuit 30 is A signal "1" is input to the tempo oscillator, and correction data is generated to speed up the automatic performance and added to the tempo oscillator. (2) When the key press timing matches the key press timing When the key press timing matches the note length data TL2 latched in the latch circuit L4,
At the same time as the key press coincidence signal KEQ, A=B is established in the comparator 270, and a signal "1" is sent to the line l5.
occurs. In this case, "1" is differentiated by the differentiating circuit 41 and added to the AND circuit A9 as the code length matching signal LEQ. AND circuit A9 has an inverter IN which inverts the rest detection signal RD to the other input.
9 outputs and key press matching KEQ are added. Therefore, the AND condition of the AND circuit A9 is satisfied, and a signal "1" (pulse signal) is outputted via the OR circuit OR14. This signal “1”
Then, the next melody data is read out. In other words, the key press timing is determined by the latch circuit L4.
If it matches the note length data TL2 latched in the tempo clock TCL, no control is performed on the tempo clock TCL. (3) When the key press timing is later than the key press timing When the key press timing is later than the note length data TL2 latched in the latch circuit L4,
Alternatively, if the correct key press is delayed due to a mistouch, the count value of the note length counter 120 is changed to the note length data TL2 before the key press coincidence signal KEQ is generated.
The comparator 270 establishes A=B, and the differentiating circuit 41 generates a code length match signal LEQ. This code length match signal LEQ is applied to AND circuit A10. The AND circuit A10 has the output signal of the inverter IN10 and the signal inverted by the inverter IN11 of the output of the AND circuit A9 added to other inputs, and in this case, the rest detection signal
RD is “0”, output of AND circuit A9 is “0”
Therefore, the AND condition of the AND circuit A10 is satisfied and a signal "1" is output. The output of this AND circuit A10 is connected to the other input by a flip-flop.
The inverted output (in this case, "1") of FF30 is applied to the set terminal S of the flip-flop FF40 via the AND circuit A11, which has become operational, and is also applied to the slow key input terminal S of the tempo control circuit 30. join. As a result, flip-flop FF30 is set and outputs a stop signal ST from output terminal Q. This stop signal ST is inverted by an inverter IN12 and applied to an AND circuit A12, thereby disabling the AND circuit A12 and temporarily stopping the progress of the automatic performance.
The tempo control circuit 30 also includes a tempo oscillator 2.
Correction data is output to lower the oscillation frequency of the tempo clock TCL output from 80. Also, the stop signal ST output from flip-flop FF40 is output from delay flip-flop FF40.
It is added to the AND circuit A13 via DF3. AND circuit A13 sends a key press coincidence signal to other inputs.
KEQ can now be added. Therefore, the AND circuit A13 outputs the key press coincidence signal KEQ.
The AND condition is satisfied at the timing , and a signal "1" (pulse signal) is outputted via the OR circuit OR14. This signal "1" causes the next melody data to be read. In addition, flip-flop FF40 outputs the stop signal ST.
The output of the AND circuit A13 is connected to the reset terminal R of the inverter IN1, which inverts the play signal PL.
The output of the OR circuit OR16 which takes the OR condition of the output of 3 is added, and in this case, the output of the AND circuit A13 is used to select the flip-flop FF4.
0 is reset and the stop signal ST becomes "0". In other words, the key press timing is determined by the latch circuit L4.
If the key press timing is later than the note length data TL2 latched to the above note length data,
After matching TL2, the progress of the automatic performance is temporarily stopped until a key is pressed, and a signal "1" is input to the slow pressed key input terminal S of the tempo control circuit 30, and correction is made to slow down the automatic performance. Data is formed and output to tempo oscillator 280. In the above operation description, it is assumed that the rest detection signal RD output from the rest detection circuit 40 is "0". However, when the rest detection signal RD is "1", the rest detection signal RD is The AND circuit A14, which takes an AND condition with the length match signal LEQ, outputs the code length data TL2 latched in the latch circuit L4 by the count value of the code length counter 120 at the timing when the code length match signal LEQ is generated, that is, in the comparison in the comparator 270. At the time when the signal "1" (pulse signal) coincides with the "1" signal, a signal "1" (pulse signal) is outputted via the OR circuit OR14. This signal “1”
Then, the next melody data is read out. Note that the tempo control circuit can be composed of only an up-down counter that uses the signal when the key press timing is early as the count-up input and the signal when the key press timing is slow as the count-down input, but Predetermined number of times (5 to 20)
It is preferable to use the difference between the earlier and later number of key presses for tempo control. Further, in this embodiment, the present invention is applied to an electronic musical instrument having a melody keyboard and an accompaniment keyboard, but it may also be applied to an electronic musical instrument with a single keyboard, or for accompaniment performance such as automatic bass performance, automatic chord performance, etc. This can be easily realized by providing separate storage means and data writing/reading means in the same manner as automatic obbligado performance. Furthermore, the tempo of the automatic performance according to the present invention can be controlled based on the operation timing of not only the key press device but also other manual operation means, such as switches and pedals arranged on the panel surface of the electronic musical instrument. Good too. As explained above, according to the present invention, the progress of the automatic performance is automatically tracked in accordance with the operation timing, so that it is possible to match the progress of the automatic performance with the operation timing. In order to control the progress of automatic performance based on the difference between the earlier number of times and the later number of times, considering only whether the operation timing is early or late with respect to the timing, it is possible to keep the progress of automatic performance stable, that is, according to the operation timing. You can control the tempo to gradually speed up or slow down.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of the apparatus shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the invention. 1...Score, 2...Data reading device, 3...Keyboard for melody, 4...Keyboard for accompaniment, 5...Obligado data memory, 6...Melody data memory, 7, 8...Data writing/reading control circuit, 11,
12, 120... note length counter, 13... counter, 14... address counter, 15... key display device, 16, 20, 25, 27, 270... comparator, 17, 26... melody sound forming circuit , 24...
Obrigado sound forming circuit, 28, 280... Tempo oscillator, 29... Tempo setter, 30... Tempo control circuit, 31... Pattern memory, 32...
Accompanist formation circuit, 33... Rhythm sound source circuit, 36
...Shift register, 37...Fast key press number detection circuit, 38...Late key press number detection circuit, 39...Subtractor.

Claims (1)

[Scope of Claims] 1. A storage means for storing performance timing data, a reading means for reading the timing data from the storage means, and a performance timing and manual operation indicated by the timing data read by the reading means. early/late detection means for comparing operation timing in the means to detect whether the operation timing is earlier or later than the performance timing; detecting the number of times the operation timing is early or late from the output of the early/late detection means; An automatic performance device comprising tempo control means for controlling the tempo of automatic performance based on the detection result. 2. The storage means stores note length data as well as pitch data, and the pitch data is read out by the reading means and added to a pressed key display device to display the key to be pressed. The automatic performance device according to scope 1. 3. The reading means detects the elapsed time point of the performance timing by counting tempo clocks, and detects the elapsed time point of the performance timing at each elapsed time point or, if the operation timing is earlier than the performance timing, the readout means detects the elapsed time point of the performance timing by counting the tempo clock. 2. The automatic performance device according to claim 1, wherein the note length data is read out from the storage means in synchronization with the operation timing. 4. The automatic performance device according to claim 1, wherein the early/late detection means detects whether the operation timing is earlier or later than the performance timing only when the difference between the performance timing and the operation timing is within a predetermined time. . 5. The automatic performance device according to claim 1, wherein the tempo control means includes a stop means for temporarily stopping the automatic performance between the performance timing and the operation timing when the operation timing is later than the performance timing. . 6. The tempo control means controls the tempo of automatic performance based on the difference between the earlier and later times of a predetermined number of comparisons from the current operation timing among the detection outputs of the early/late detection means. An automatic performance device according to claim 1.