JPH03637B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a power-on reset circuit for a display controller.

Prior Art and Problems to be Solved by the Invention In a control device incorporating a register or the like, a power-on reset is performed as an initial setting when the power is turned on. This power-on reset is performed immediately after the power is turned on until the power supply voltage level becomes sufficiently stable. Therefore, the reset is normally canceled after the power supply voltage level reaches a predetermined value and when the predetermined clock count is completed. It will be done. However, in the conventional power-on reset for display control devices, since the above-mentioned clock uses a clock with a relatively short period from the clock generation circuit, the number of stages of the counter that counts the clock becomes large, and as a result, However, there was a problem in that the manufacturing cost was high.

Means for Solving the Problems In view of the above-mentioned problems, an object of the present invention is to provide a power-on reset circuit for a display control device that is low in manufacturing cost.
This is achieved by using a counter that counts vertical synchronization signals with a relatively long period.

Operation The counter described above is constructed with a smaller number of stages.

Embodiment FIG. 2 is an overall configuration diagram of a display system to which a power-on reset circuit according to the present invention is applied. In FIG. 2, the display device 1 is controlled by a display control device 2.
In this case, the display control device 2 receives a vertical synchronization signal and a horizontal synchronization signal from the display device 1;
Display blanking signal VOW as display output
and a background blanking signal.

As shown in FIG. 3, the display control device 2
are address memory control circuit 201, memory address register 202, horizontal character size register 203, horizontal position register 204, vertical character size register 205, vertical position register 206,
Blinking register 207, horizontal character size control circuit 209, horizontal display position control circuit 210,
Vertical character size control circuit 211, vertical display position control circuit 212, blinking control circuit 213,
Clock generation circuit 214, timing generator 21
5. It is composed of a display character selection circuit 216, a display data memory 217, a character generator 218, a shift register 219, a display control circuit 220, a power-on reset circuit 221, and the like. Note that a detailed explanation of each element will be omitted.

In FIG. 3, registers 203-207 need to be reset for a predetermined period of time when the power is turned on. A power-on reset circuit 221 is provided for this purpose. Conventionally, the clock generation circuit 21
4 clock signal to the power-on reset circuit 22.
1, and because the necessary reset time was secured by this fast clock signal, the number of stages of the counter that counted the clock signal tended to increase. In the present invention, the slow vertical synchronization signal
VSYNC is supplied to the power-on reset circuit 221, thereby reducing the number of stages of the counter that counts the synchronization signal.

FIG. 1 is a circuit diagram showing one embodiment of a power-on reset circuit according to the present invention. In Figure 1, _Vcc is the power supply terminal, Vcc is the reset terminal,
VSYNC is a vertical synchronization signal terminal. Here, these terminal names also indicate terminal voltages. DETH is a voltage detection circuit (inverter) that detects that the voltage has exceeded a predetermined value V _thH and generates a low level signal _S1 , DETL is a voltage
A voltage detection circuit (inverter) that detects that RESET has exceeded a predetermined value V _thL and generates a low level signal S ₂ , and DET is a voltage detection circuit (inverter) that detects that RESET has exceeded a predetermined value V _{thL .}
This is a voltage level detection circuit that generates a pulse signal by detecting that the voltage level has decreased. Here, the respective predetermined values V _thH and V _thL have a relationship of V _thL <V _thH .

The reset terminal is also used to control the generation of the reset signal RESET by applying an external signal. In other words, if you externally set the voltage to a low level lower than V _thH ,
The output _S1 of the voltage detection circuit DETH becomes high level and is therefore sent out as the reset signal RESET. On the other hand, if the voltage is made higher than V _thH , the output S ₁ of the voltage detection circuit DETH becomes low level, and therefore the signal RESET is not sent out. In this case, it is assumed that the other input of the OR circuit OR is also at low level. However, in the following explanation,
It is assumed that no external signal is applied to the reset terminal.

G is a MOS transistor whose gate is controlled by the output _S4 of the RS flip-flop FF. INV is an inverter, AND is an AND circuit, and CNT is a counter for counting.

The operation of the circuit shown in FIG. 1 will be explained with reference to the timing diagram shown in FIG. When the power is turned on at time _t0 , the voltage _Vcc gradually increases as shown in FIG. 41, and the vertical synchronizing signal oscillates as shown in FIG. 42. In this state, the output _S4 of the flip-flop FF is undefined, so the transistor G is not turned on, and as shown in _{FIG .} If so, the signals S ₁ and S ₂ are both at high level as shown in FIGS. 4 and 5. Therefore, the signal _S1 is the reset signal RESET
Sent as .

Next, at time t ₁ , when the voltage reaches V _thL , the output S ₂ of the voltage detection circuit DETL changes from high level to low level, and then at time t ₂ , the power supply voltage V _cc reaches V thL of the voltage level detection circuit DET. When the threshold V _th is reached, the voltage level detection circuit
DET generates a pulse signal _S3 shown in FIG. 46.
As a result, the output S ₄ of the AND circuit AND is shown in Fig. 4, 7.
The counter CNT is reset. At the same time, flip-flop FF is set, and its output _S5 changes from low level to high level as shown in FIG. 4. As a result, transistor G is turned on and the voltage is again reduced to a low level as shown in FIG. 4.

As mentioned above, when the counter CNT starts and counts a predetermined number of vertical synchronization signals (1 in this case) and overflows, the counter output _S6 changes from low level to high level as shown in FIG. Then the flip-flop FF is reset,
As a result, transistor G is cut off and the voltage begins to rise again as shown in FIG. 4. And at time t ₃ , =V _thL
Then, the counter CNT is reset. Furthermore, at time _t4 , when VthH increases and reaches _VthH , the output _S1 of the voltage detection circuit DETH becomes low level, and the reset signal RESET is therefore released. Here, the period from the operation of the voltage detection circuit DETL to the operation of the voltage detection circuit DETH (t ₃ ~
_t4 ) is the oscillation stabilization time.

Note that the number of stages of the counter CNT, that is, the number of counted pulses of the vertical synchronization signal can be changed as necessary.

Effects of the Invention As explained above, according to the present invention, the reset time is ensured by counting the vertical synchronization signal with a relatively long period, so the number of counter stages for this purpose can be reduced, and the manufacturing cost can be reduced. can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a power-on reset circuit for a display control device according to the present invention, FIG. 2 is an overall configuration diagram of a display system to which the circuit of FIG. 1 is applied, and FIG. FIG. 2 is a detailed circuit diagram of the display control device, and FIG. 4 is a timing diagram showing the circuit operation of FIG. 1. 1: Display device, 2: Display control device, 221: Power-on reset circuit,
DET: voltage level detection circuit, DETH: first voltage detection circuit, DETL: second voltage detection circuit, G:
Switching element, FF: flip-flop,
CNT: Counter.

Claims (1)

[Claims] 1 Reset terminal RESET, a reset signal is generated when the potential of the reset terminal is below a predetermined value V _thH .
a first voltage detection circuit DETH that generates RESET;
a second voltage detection circuit that generates a clear signal when the potential of the reset terminal is below a predetermined value V _thL ;
DETL, the switching element G connected between the reset terminal and ground, the power supply voltage level is a predetermined value.
A voltage level detection circuit DET that detects that V _th has been reached and generates a pulse signal, a flip-flop FF that is set by the pulse signal and turns on the switching element, and a voltage level detection circuit DET that detects that V th has been reached and generates a pulse signal; A power-on reset circuit for a display control device, comprising a counter CNT which resets the flip-flop and turns off the switching element when the counter CNT is placed in a counting state and counts a predetermined number of vertical synchronizing signals VSYNC of the display.