JPH0363811B2 - - Google Patents

Info

Publication number
JPH0363811B2
JPH0363811B2 JP3712984A JP3712984A JPH0363811B2 JP H0363811 B2 JPH0363811 B2 JP H0363811B2 JP 3712984 A JP3712984 A JP 3712984A JP 3712984 A JP3712984 A JP 3712984A JP H0363811 B2 JPH0363811 B2 JP H0363811B2
Authority
JP
Japan
Prior art keywords
bonding
wire
substrate
area
semiconductor pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3712984A
Other languages
Japanese (ja)
Other versions
JPS60182147A (en
Inventor
Koichi Chiba
Yoshio Terasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59037129A priority Critical patent/JPS60182147A/en
Publication of JPS60182147A publication Critical patent/JPS60182147A/en
Publication of JPH0363811B2 publication Critical patent/JPH0363811B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明は半導体ペレツトのインナーボンデイン
グパツドとリードフレームとをワイヤボンデイン
グする方法に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for wire bonding an inner bonding pad of a semiconductor pellet to a lead frame.

［背景技術の問題点］ 従来から、第１図に示すように、基板１上にダ
イボンドされた半導体ペレツト２の内部および表
面部に形成された回路部（図示を省略）と、前記
基板１上に形成された導体パターンとを電気的に
接続する場合には、前記半導体ペレツト２上に設
けられた前記回路部の端子である多数のボンデイ
ングパツド３ａ，３ｂ…とこれらに対応する導体
パターンの端子であるリードフレーム４ａ，４ｂ
…とを、自動ボンデイング装置を用いて金線等の
ボンデイングワイヤ５ａ，…によりそれぞれ電気
的に接続する方法がとられている。[Problems with Background Art] Conventionally, as shown in FIG. When electrically connecting conductor patterns formed on the semiconductor pellet 2, a large number of bonding pads 3a, 3b, etc., which are terminals of the circuit section provided on the semiconductor pellet 2, and the corresponding conductor patterns are connected. Lead frames 4a and 4b which are terminals
. . are electrically connected to each other by bonding wires 5a, . . . such as gold wires, using an automatic bonding device.

［背景技術の問題点］ 一般に、半導体ペレツト２のボンデイングパツ
ド３ａ，３ｂ…は半導体ペレツト２の辺に沿つて
設けられ、かつリードフレーム４ａ，４ｂ…も半
導体ペレツト２の辺に沿つて基板１上に設けられ
ている。[Problems with the Background Art] Generally, the bonding pads 3a, 3b, . . . of the semiconductor pellet 2 are provided along the sides of the semiconductor pellet 2, and the lead frames 4a, 4b, . is placed above.

このため、ボンデイング操作を、半導体ペレツ
ト２の一つの辺２ａに沿つて設けられたボンデイ
ングパツド３ａの列からこれと隣接する半導体ペ
レツト２の他の辺２ｂに沿つて設けられたボンデ
イングパツド３ｂの列に移す場合には、次の辺に
移つて最初のボンデイング操作におけるボンデイ
ングワイヤ５b1のたるみ（ループ）の方向が不安
定になり、ボンデイングパツド４ｂの間隔が狭い
場合には、隣接するボンデイングワイヤ５b1，５
b2どうしの接触が生じてしまうという難点があつ
た。 For this reason, the bonding operation is performed from a row of bonding pads 3a provided along one side 2a of the semiconductor pellet 2 to a row of bonding pads 3b provided along the other side 2b of the semiconductor pellet 2 adjacent thereto. When moving to the next side, the direction of the slack (loop) of the bonding wire 5b1 in the first bonding operation becomes unstable, and if the gap between the bonding pads 4b is narrow, Bonding wire 5b 1 , 5
b There was a problem in that the 2 pieces came into contact with each other.

すなわち、半導体ペレツト２の一つの辺２ａに
沿つて配列されたボンデイングパツド３ａ群と、
この辺２ａに沿つて配列されたリードフレーム４
ａ群とをワイヤボンドしている間は、ボンデイン
グワイヤ５ａはほぼ180゜異なる方向に交互に屈曲
されているので、ボンデイングワイヤのたるみの
方向は常に基板とほぼ直角の方向となり、横方向
にたるみが生じるようなことはない。 That is, a group of bonding pads 3a arranged along one side 2a of the semiconductor pellet 2;
Lead frames 4 arranged along this side 2a
During wire bonding with group a, the bonding wires 5a are bent alternately in different directions approximately 180 degrees, so the direction of slack in the bonding wires is always approximately perpendicular to the substrate, and there is no slack in the lateral direction. There is no such thing as occurring.

しかしながら、半導体ペレツト２の一つの辺２
ａに沿うボンデイングパツド３ａ群とリードフレ
ーム４ａ群間のボンデイング操作から、これと隣
接する辺２ｂに沿うボンデイングパツド３ｂ群と
リードフレーム４ｂ群間のボンデイング操作に移
る場合には、前の辺２ａにおけるボンデイング操
作により生じた曲がりぐせがボンデイングワイヤ
に残つているため、次の辺２ｂに移つて最初のボ
ンデイング操作の際に、この曲がりぐせがボンデ
イングワイヤ５b1に横方向の曲がり成分として現
われ、次にボンデイングされたボンデイングワイ
ヤ５b2と接触して不良となることがあつた。 However, one side 2 of the semiconductor pellet 2
When moving from the bonding operation between the bonding pads 3a group and the lead frame 4a group along the side 2b to the bonding operation between the bonding pads 3b group and the leadframe 4b group along the adjacent side 2b, the previous side Since the bending caused by the bonding operation at 2a remains in the bonding wire, when moving to the next side 2b and performing the first bonding operation, this bending appears as a horizontal bending component in the bonding wire 5b1 , Next, it sometimes came into contact with the bonding wire 5b2 that was bonded, resulting in a defect.

［発明の目的］ 本発明はこのような問題点を解決するためにな
されたもので、常にたるみの方向を基板面に対し
て直行させることにより、常に隣接するボンデイ
ングワイヤ相互の接触のおそれのない、ボンデイ
ング方法を提供することを目的とする。[Purpose of the Invention] The present invention has been made to solve these problems, and by always making the direction of slack perpendicular to the substrate surface, there is always no fear of adjacent bonding wires coming into contact with each other. , aims to provide a bonding method.

［発明の概要］ すなわち本発明のワイヤボンデイング方法は、
基板上の所定の位置に半導体ペレツトをダイボン
ドし、この半導体ペレツトに設けた多数のボンデ
イングパツドと前記基板上にこれらと対応させて
設けたリードフレームとをボンデイングワイヤを
用いてそれぞれ電気的に接続するワイヤボンデイ
ング方法において、前記基板上またはその近傍に
ワイヤボンド操作可能な電気的に独立したエリア
を設けておき、所定の方向にボンデイング操作を
行ない次いで異なる方向にボンデイング操作を行
なうにあたり、予め前記エリア内において新たに
ボンデイングすべき方向にワイヤボンデイング操
作を行なつた後、次のワイヤボンデイングを行な
うことを特徴としている。[Summary of the invention] That is, the wire bonding method of the present invention includes:
A semiconductor pellet is die-bonded to a predetermined position on a substrate, and a number of bonding pads provided on this semiconductor pellet are electrically connected to lead frames provided correspondingly on the substrate using bonding wires. In the wire bonding method, an electrically independent area where wire bonding can be performed is provided on or near the substrate, and when bonding is performed in a predetermined direction and then in a different direction, the area is The method is characterized in that after a wire bonding operation is performed in the direction in which new bonding is to be performed, the next wire bonding is performed.

［発明の実施例］ 以下本発明を第２図に示す一実施例について説
明する。なお第２図において、第１図と共通する
部分には同一符号を付してある。[Embodiment of the Invention] An embodiment of the present invention shown in FIG. 2 will be described below. In FIG. 2, parts common to those in FIG. 1 are given the same reference numerals.

この実施例のワイヤボンデイング方法に用いる
基板１上には、同図に示すように予め半導体チツ
プ２の辺２ｂと平行にリードフレーム４ａ，４ｂ
と同材質の矩形の金属箔、例えば銅箔からなる電
気的に独立したエリア６が設けられている。 Lead frames 4a, 4b are placed in advance on the substrate 1 used in the wire bonding method of this embodiment in parallel with the side 2b of the semiconductor chip 2, as shown in the figure.
An electrically independent area 6 is provided which is made of a rectangular metal foil made of the same material as, for example, copper foil.

このエリア６は、リードフレーム４ａ，４ｂの
形成時に同時に金属箔を基板１上へ接合させて形
成するようにしてもよく、接着剤を用いて事後的
に設けるようにしてもよい。また必要に応じて、
めつき、蒸着等の手段により形成させてもよい。 This area 6 may be formed by bonding metal foil onto the substrate 1 at the same time as the lead frames 4a, 4b are formed, or may be provided afterwards using an adhesive. Also, if necessary,
It may be formed by means such as plating or vapor deposition.

またこのエリア６の幅および長さは、ボンデイ
ングワイヤの張り方向が変る側のボンデイング操
作、すなわちボンデイングパツド３ｂ、リードフ
レーム４ｂ間のボンデイング操作が充分行なうこ
とができる範囲であればよい。 The width and length of this area 6 may be within a range that allows sufficient bonding operation on the side where the tension direction of the bonding wire changes, that is, the bonding operation between the bonding pad 3b and the lead frame 4b.

したがつてこのエリア６は、１個のみで形成さ
れていてもよく、ボンデイングパツド３ｂとリー
ドフレーム４ｂと同サイズのもの１組を対にして
形成するようにしてもよい。 Therefore, this area 6 may be formed of only one piece, or may be formed of a pair of bonding pads 3b and lead frame 4b of the same size.

さらにこのエリア６は、半導体ペレツト２の４
辺にそれぞれボンデイングパツドが設けられてい
る場合には、張り方向が変る次の辺のボンデイン
グ方向に対応させて、各辺毎に別々に設けておい
てもよく、また共通に使用し得る大きさのエリア
を１個設けておくようにしてもよい。 Furthermore, this area 6 contains 4 of the semiconductor pellets 2.
If bonding pads are provided on each side, they may be provided separately on each side to correspond to the bonding direction of the next side where the tension direction changes. Alternatively, one area may be provided.

この実施例のボンデイング方法は、第２図に示
した基板１を用いて次のように行なわれる。 The bonding method of this embodiment is carried out as follows using the substrate 1 shown in FIG.

まず、第２図に示すように、半導体チツプ２の
辺２ａに沿つて、常法によりボンデイングワイヤ
５ａを用いてボンデイングパツド３ａ群とリード
フレーム４ａ群間のボンデイング操作が行なわれ
る。 First, as shown in FIG. 2, a bonding operation between the bonding pads 3a group and the lead frame 4a group is performed along the side 2a of the semiconductor chip 2 using a bonding wire 5a in a conventional manner.

しかして辺２ａに沿う最後のボンデイングパツ
ド３ａとリードフレーム４ａとのボンデイング操
作を終了した後、キヤピラリー（図示せず）のボ
ンデイング操作の方向を、辺２ｂに沿うボンデイ
ングパツド３ｂとリードフレーム４ｂ間のボンデ
イング操作方向に変更して、エリア６内で一回ま
たは必要に応じて複数回のボンデイング操作を行
なう。 After completing the bonding operation between the last bonding pad 3a and lead frame 4a along side 2a, the direction of the bonding operation of the capillary (not shown) is changed to the bonding pad 3b and lead frame 4b along side 2b. The bonding operation is performed once or multiple times as necessary within the area 6 by changing the direction of the bonding operation in between.

この操作により、エリア６内にボンデイングさ
れたボンデイングワイヤ５ｎがワイヤボンドされ
るが、このときボンデイングワイヤ５ｎには、辺
２ａに沿うボンデイング操作による曲がりぐせの
影響を受けて横方向に曲がりのあるたるみが形成
される。一方、これによつてキヤピラリー内のボ
ンデイングワイヤには、エリア６内におけるボン
デイング操作により、辺２ｂに沿うボンデイング
操作により形成される曲がりぐせと同方向の曲が
りぐせが形成される。 Through this operation, the bonding wire 5n bonded in the area 6 is wire-bonded, but at this time, the bonding wire 5n has a lateral bend due to the bending caused by the bonding operation along the side 2a. is formed. On the other hand, as a result, a bend in the same direction as the bend formed by the bonding operation along the side 2b is formed in the bonding wire in the capillary by the bonding operation in the area 6.

この後、辺２ｂに沿つてボンデイングパツド３
ｂ、リードフレーム４ｂ間のワイヤボンデイング
が行なわれるが、このときすでにボンデイングワ
イヤ５b1には、エリア６内におけるボンデイング
操作により辺２ｂ側のボンデイング操作により生
ずる曲がりぐせと同方向の曲がりぐせが形成され
ているので、辺２ｂに沿うボンデイングパツド３
ｂとリードフレーム４ｂとは基板１の面に直交す
る方向のたるみが形成される。したがつてボンデ
イングワイヤ５b1とこれに隣接するボンデインク
ワイヤ５b2とが接触するようなことはなくなる。 After this, attach the bonding pad 3 along the side 2b.
b. Wire bonding between the lead frames 4b is performed, but at this time, the bonding wire 5b1 has already formed a bend in the same direction as the bend caused by the bonding operation on the side 2b side due to the bonding operation in the area 6. Therefore, bonding pad 3 along side 2b
A slack is formed between the lead frame 4b and the lead frame 4b in a direction perpendicular to the surface of the substrate 1. Therefore, there is no possibility that the bonding wire 5b 1 and the bonding wire 5b 2 adjacent thereto come into contact with each other.

なおエリア６は、全てのボンデイング操作が終
了した後、除去してもよく、またそのまま残して
おいてもよい。 Note that the area 6 may be removed after all bonding operations are completed, or may be left as is.

また以上の実施例では、エリア６を基板１上に
設けた例について説明したが本発明はこのような
実施例に限定されるものではなく、エリア６を基
板外に設けるようにしてもよい。 Further, in the above embodiment, an example in which the area 6 was provided on the substrate 1 was described, but the present invention is not limited to such an embodiment, and the area 6 may be provided outside the substrate.

［発明の効果］ 以上の記載から明らかなように本発明によれ
ば、ボンデイングワイヤのたるみは、常に基板の
表面と直交する方向にのみ生ずるので、隣接する
ボンデイングワイヤどうしが接触するおそれはな
くなり、製品歩留りが飛躍的に向上する。[Effects of the Invention] As is clear from the above description, according to the present invention, slack in the bonding wire always occurs only in the direction perpendicular to the surface of the substrate, so there is no risk of adjacent bonding wires coming into contact with each other. Product yield improves dramatically.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のワイヤボンデイング方法を説明
するための平面図、第２図は本発明のワイヤボン
デイング方法を説明するための平面図である。 １……基板、２……半導体ペレツト、３ａ，３
ｂ……ボンデイングパツド、４ａ，４ｂ……リー
ドフレーム、５，５ａ，５b1，５b2，５ｎ……ボ
ンデイングワイヤ、６……基板外のエリア。 FIG. 1 is a plan view for explaining the conventional wire bonding method, and FIG. 2 is a plan view for explaining the wire bonding method of the present invention. 1...Substrate, 2...Semiconductor pellet, 3a, 3
b...Bonding pad, 4a, 4b...Lead frame, 5, 5a , 5b1, 5b2 , 5n...Bonding wire, 6...Area outside the board.

Claims (1)

【特許請求の範囲】[Claims] １ 基板上の所定の位置に半導体ペレツトをダイ
ボンドし、この半導体ペレツトに設けた多数のボ
ンデイングパツドと前記基板上にこれらと対応さ
せて設けたリードフレームとをボンデイングワイ
ヤを用いてそれぞれ電気的に接続するワイヤボン
デイング方法において、前記基板上またはその近
傍にワイヤボンド操作可能な電気的に独立したエ
リアを設けておき、所定の方向にボンデイング操
作を行ない次いで異なる方向にボンデイング操作
を行なうにあたり、予め前記エリア内において新
たにボンデイングすべき方向にワイヤボンデイン
グ操作を行なつた後、次のワイヤボンデイングを
行なうことを特徴とするワイヤボンデイング方
法。1. A semiconductor pellet is die-bonded to a predetermined position on a substrate, and a number of bonding pads provided on the semiconductor pellet are electrically connected to lead frames provided correspondingly on the substrate using bonding wires. In the wire bonding method for connecting, an electrically independent area where wire bonding can be performed is provided on or near the substrate, and when bonding is performed in a predetermined direction and then in a different direction, the A wire bonding method characterized in that after performing a wire bonding operation in a direction in which new bonding is to be performed within an area, the next wire bonding is performed.
JP59037129A 1984-02-28 1984-02-28 Wire bonding method Granted JPS60182147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59037129A JPS60182147A (en) 1984-02-28 1984-02-28 Wire bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59037129A JPS60182147A (en) 1984-02-28 1984-02-28 Wire bonding method

Publications (2)

Publication Number Publication Date
JPS60182147A JPS60182147A (en) 1985-09-17
JPH0363811B2 true JPH0363811B2 (en) 1991-10-02

Family

ID=12488998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59037129A Granted JPS60182147A (en) 1984-02-28 1984-02-28 Wire bonding method

Country Status (1)

Country Link
JP (1) JPS60182147A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101598999B1 (en) * 2012-11-16 2016-03-02 가부시키가이샤 신가와 Wire bonding device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JPS60182147A (en) 1985-09-17

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