JPH0363831A - Microcomputer - Google Patents

Abstract

PURPOSE:To enable a pattern generated in simulation for a single user cell to be used as it is in the simulation for whole of a chip by providing a means to select whether the output signal of a frequency division circuit or a signal from an external terminal is supplied to a user cell as a clock. CONSTITUTION:At a case other than the simulation of the user cell, switching circuits 43, 44 are energized and switching circuits 42, 45 are interrupted since a test mode signal is set at 0, therefore, the outputs 50, 51 of the frequency division circuit 34 go to system clocks phi1, phi2. In the simulation of the user cell, the test mode signal is set at 1, and the switching circuits 43, 44 are energized, and the circuits 42, 45 are interrupted, therefore, the signals inputted to terminals 8 and 41 go to the system clocks phi1, phi2, respectively. Thereby, it is possible to use a simulation pattern for the single user cell as it is as the pattern in the simulation for the whole of the chip.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a CPU core type standard cell custom L
It relates to a microcomputer that becomes SI.

[Conventional technology]

Among standard cell type custom LSIs, C
A custom LSI called the PU core method uses CPU, R
OM, RAM, I10 boat, serial I10. By combining large-scale cells prepared by LSI manufacturers such as timers, or by combining basic gate cells prepared by LSI manufacturers, users can design their own circuits (hereinafter referred to as "user cells"). By combining it with large-scale cells prepared by , users can freely configure microcomputers that suit their own purposes.

Such a microcomputer is hereinafter referred to as a custom microcomputer.

FIG. 3 shows a block diagram of a custom microcomputer composed of a user cell and a large-scale cell.In this custom microcomputer, CPU1. It includes a timer 2 and a system clock generator 5 having a built-in I10 port 32 oscillator, and these are all large-scale cells prepared in advance by the manufacturer, and 4 is a user cell made by combining basic gate cells. The system clock generator 5 has a terminal 8.
By dividing the oscillation clock by the oscillator connected to 9,
System clocks φ1 and φ2 are connected to CPU1, timer 2, and I.
10 boats 3 and user cells 4. moreover,
CPtJ 1, timer 2, I10 port 3, user cell 4 has address bus 6, data bus 7, read signal 10,
They are connected by a write signal 11 and a reset signal (not shown).

If a user designs such a custom microcontroller,
The user cell simulation is performed by the user. Particularly in the early stages of design, simulation is performed on a single user cell in order to shorten the simulation period, and once the simulation has progressed to a certain extent and circuit modifications in the user cell have been completed, the simulation shifts to the entire chip. When simulating a single user cell, it is necessary to define a simulation button at a terminal that interfaces between the CPU and the user cell. That is, test patterns for the address bus 6, data bus 7, read signal 10, write signal 11, reset signal, and system clocks φ1 and φ2 were defined.

Figure 4 is an operational waveform diagram in the simulation of this user cell alone, and a time chart of the address bus, data bus, read signal, and system clock φ1, φ2 patterns during read. In order to define the system clock as an input button, patterns of φ1 and φ2 as shown in FIG. 4 were defined.

[Problem to be solved by the invention]

The oscillation clock of an oscillator, which is constructed by connecting an external resonator to an oscillation circuit constructed of a feedback resistor and an inverting amplifier, cannot guarantee the high-level width and low-level width of the clock, so it is usually a frequency-divided oscillation clock. A clock is used as the system clock.

FIG. 5 shows an example of the internal circuit of the system clock generator 5 shown in FIG. 3, and FIG. 6 shows a time chart of the system clocks φ1 and φ2 generated from the circuit shown in FIG.

In FIG. 5, the oscillation clock by the oscillator connected to the external terminal 8.9 is divided by two and becomes the system clock φ1.
, φ2. Time 1 when both φ1 and φ2 are not 1 in FIG. is inverter 23.25~28.30~3
3, 35, 36 and the delay time of NAND gates 24, 29, etc., and prevents data leakage in flip-flops etc. that occurs when system clocks overlap.

In the case of simulation for the entire chip, the system clocks φ1 and φ2 are supplied from the system clock generator 5 to the user cells, so simulation patterns must be defined for the address bus, data bus, read signal, write signal, and reset signal. FIG. 7 shows the relationship between the address bus, data bus, read signal, and system clock at the time of reading in a simulation of the entire chip, in which there is no need to define the system clock.

In simulating the entire chip, the system clock uses the clock generated by the system clock generator, so the relationship between the pattern and the clock is different compared to simulating a single user cell, so There was a drawback that the simulation pattern could not be used as is for simulation of the entire chip.

An object of the present invention is to provide a means for selecting whether to supply the output signal of the frequency dividing circuit to the user cell as a clock or to supply the signal input from an external terminal to the user cell as a clock. To provide a microcomputer in which a simulation button created during a simulation can be used as is during a simulation of the entire chip.

[Means to solve the problem]

The configuration of the present invention is to provide a microcomputer configured by combining a plurality of cells that operate based on a defined system clock. Alternatively, the present invention is characterized by comprising a switching means for selecting supply of a clock signal inputted from an external terminal to a specific cell among the plurality of cells as the system clock.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a system clock generation section of a custom microcomputer according to an embodiment of the present invention.

In the figure, 34 is a frequency divider circuit, 20 is an oscillation circuit composed of a feedback resistor and an inverting amplifier, and an oscillation clock is input to the frequency divider circuit 34 by a crystal oscillator connected to terminals 8 and 9. Ru. 42 to 45 are switching circuits, which are in a conductive state when the control signal is "1" and are in a cutoff state when the control signal is "O".

When the user cell is not being simulated, the test mode signal is "O", so the switching circuits 43 and 44 are in a conductive state and the switching circuits 42 and 45 are in a cut-off state. Therefore,
The output 50.51 of the frequency dividing circuit 34 is the system clock φ1
, φ2. During user cell simulation, the test mode signal becomes "1", switching circuits 43 and 44 are in a conductive state, and circuits 42 and 45 are in a cut-off state.

Therefore, the signals input to terminals 8 and 41 become system clocks φl and φ2, respectively.

FIG. 2 is a block diagram showing a second embodiment of the invention. 42 to 45.47 are switching circuits that become conductive when the control signal is "1", and the switching circuit 47 is the oscillation circuit 20a.
included in.

Since the test mode signal is "O" at times other than user cell simulation, the switching circuits 43, 44, 4
7 is in a conductive state, switching circuits 42 and 45 are in a cut-off state,
Terminal 9 is connected to oscillation circuit 20a. The oscillation clocks of the oscillators connected to the terminals 8 and 9 are input to the frequency dividing circuit 34, and the output signals 50 and 51 become the system clocks φ1 and φ2, respectively.

During user cell simulation, the test mode signal becomes "1", and the terminal 9 is logically separated from the oscillation circuit 20a. At this time, the switching circuits 43 and 44 are in a cutoff state, and the switching circuits 42 and 45 are in a conductive state. Therefore, the signals input to the terminal 9.8 become the system clocks φ1 and φ2, respectively.

〔Effect of the invention〕

As explained above, the present invention includes means for selecting whether to supply the output signal of the frequency dividing circuit to the user cell or to supply the signal input from the external terminal as the system clock of the microcomputer. Therefore, the simulation button for a single user cell can be directly used as a button for simulation for the entire chip, which has the effect of reducing the burden on the user in microcomputer development.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system clock generation section of a microcomputer according to an embodiment of the present invention, and FIG. 2 is a block diagram of a system clock generation section of a second embodiment of the present invention.
Fig. 3 is a block diagram showing the configuration of a general microcomputer, Fig. 4 is a time chart showing the simulation button in a simulation of a single user cell of a conventional microcomputer, and Fig. 5 is the system clock generation shown in Fig. 3. FIG. 6 is a time chart showing the operation of the system clock generation section in FIG.
FIG. 7 is a time chart showing simulation patterns in a simulation of the entire chip of a conventional user cell. DESCRIPTION OF SYMBOLS 1... CPU, 2... Timer, 3... I10 boat, 4... User cell, 5... System clock generation part, 6... Address bus, 7... Data bus, 1
0...Read signal, 11...Write signal, 20...
・Oscillation circuit, 8°9.41...External terminal, 34...
Frequency dividing circuit, 22° 23.25 ~ 28.30 ~ 33,35
, 36° 46... Inverter, 24.29... NA
ND gate, 42-45... switching circuit, 51.52.
...Output signal of the frequency divider circuit.

Claims (1)

[Claims] In a microcomputer configured by combining multiple cells that operate based on a defined system clock, there is a frequency divider circuit that divides the clock signal, and an output signal of this frequency divider circuit or input from an external terminal. 1. A microcomputer comprising: switching means for selecting supply of a clock signal obtained as the system clock to a specific cell among the plurality of cells.