JPH0363849A - Cache memory of set associative system - Google Patents

Abstract

PURPOSE:To easily perform the test of a tag memory by providing a decoder circuit to generate a way hit signal by receiving a way selection signal, and a third selector to select and output either the way hit signal from the circuit or the way hit signal from a priority storage means. CONSTITUTION:The decoder circuit 14 which receives the way selection signal from the outside to instruct a specific way and generates the way hit signal, and a selector 15 which receives a diagnostic mode signal 12 and selects and outputs either the way hit signal from the decoder circuit 14 or the one from the priority storage means 8 are provided. And a way is selected with the way selection signal 13 inputted from the outside by setting a mode at a diagnostic mode with the diagnostic mode signal 13. Thereby, algorithm to generate a test pattern for the diagnosis of an address tag memory 5 is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides an address tag memory and an LRU (Least Receiver) included in a cache system.
The present invention relates to a set associative type cache memory that allows a bit memory to be easily tested.

[Conventional technology]

FIG. 3 is an address configuration diagram and a block diagram of a four-way set associative cache memory for explaining a conventional method of diagnosing a set associative cache memory. This four-way set associative cache memory is described in "Interface J" published by CQ Publishing Co., Ltd., September 1987 issue, page 205.

In FIG. 3, 1 is an address to access the cache memory, 2 is an address tag that is a part of the address 1, 3 is a set select that is a part of the address 1, and 4 is a part of the address 1. 5 is an address tag 2 that holds the address tag in the cache memory, 6 is a valid bit memory that indicates whether the data held in the data block memory 7 (described later) is valid or invalid; 7 is a data block memory that holds data in the cache memory, and 8 is L as a data replacement priority level storage means for each way.
This is an RU bit memory, and the LRU bit memory 8 performs data replacement using LRU (1, gast Recent).
y Used) is a status register controlled by the algorithm. Furthermore, 9 is an address tag comparator that compares the address data held in the address tag 2 and the address tag memory 5 to check whether they match; The first selector 11 selected is the second selector selected by the address tag comparator 9, and a is the output data output from the second selector 11.

Next, the operation will be explained.

When address 1 is given from outside, set select 3
The contents of the address tag memory 5 of each way selected in the word select 4 are sent to the address tag comparator 9, and the contents of the data block memory 7 are also sent to the first selector 10, and the word data selected in the word select 4 is sent to the second selector 10. is sent to the selector 11 of. Then, it is checked whether the contents of the address tag memory 5 selected by the address tag comparator 9 match the address tag 2, and if a matching way exists, the second selector 11 selects the way. Output the way data as output data a. However, if there is a mismatch in the address tag comparator 9, the main memory outside the cache memory,
(not shown), reads the data, sends the data to the MPU, and stores the data in the data block memory 7 in the cache memory. At this time, the LRU algorithm determines in which way the data should be stored, and this information is stored in the LRU bit memory 8.

Next, a method of diagnosing the address tag memory 5 of this cache memory system will be described.

The basic method is to first access the cache system with an arbitrary address, write an address tag that is part of the previous address to the tag memory of the entry accessed in set select 3, and then The objective is to check whether cache hit determination and cache hit determination are performed correctly when the cache system is accessed using the same cache entry as before. In other words, if an address with the same bit pattern string as the address tag 2 previously written to the address tag memory 5 is accessed, it is determined to be a cache hit, the contents of the data memory are output, and the address tag 2 and the written address tag 2 are accessed. Addresses with different bitbump string groups are determined to be cache waste, and it is checked to see if an external memory access cycle occurs in order to fetch data into the data block memory 7.

At this time, it should be noted that the way in which address tag 2 is written follows the priority level indicated by the LRU bit of each entry at that time.

Therefore, when creating a test vector, it is necessary to take this point into consideration and to know the state of the LRU bit at the time when each test vector is applied.

Next, a method for diagnosing the LRU bit memory 8 of this cache memory will be described.

In this conventional example, since it is not possible to directly write data to the LRU bit memory 8 from the outside, in order to set the LRU bit memory 8 to a value that should be diagnosed, data in the main memory is written to the cache memory multiple times. is necessary.

On top of that, in order to confirm that the LRU bit memory 8 is set to the desired value, it is necessary to read the cache memory multiple times and write the main memory data to the cache memory multiple times. It is. In this case, for the same reason as before, it is necessary to know the state of the LRU at each point in time when creating a test button.

[Problem to be solved by the invention]

Address tag memory 5 and LRU bit memory 8 in conventional set-associative cache memory
Since the test is performed using the method described above, the test button to write to the address tag memory 5, that is,
It is not possible to easily control from the outside which way the tag address is written. Therefore, in creating a test button, it is necessary to know the state of the LRU bit, that is, the history of way accesses to each entry, which poses a problem that makes it difficult to create a test button.

Further, as is clear from FIG. 3, since the LRU bit memory 8 itself cannot be accessed directly from the outside, the same problem as above exists when creating a test button for it.

The present invention was made in order to solve the above problems, and an object of the present invention is to obtain a set associative type cache memory that allows tag memory and LRU tests to be easily performed.

(Means for Solving the Problems) A set associative cache memory according to claim 0 of the present invention includes a decoding circuit that generates a way hit signal in response to an external way selection signal instructing a specific way, and a diagnostic circuit. A third selector is provided for receiving the mode signal and selecting and outputting one of the Weihit signal from the decoding circuit and the Weihit signal from the priority storage means.

The set associative cache memory according to claim (2) of the present invention includes a decoding circuit that generates a way hit signal in response to an external way selection signal instructing a specific way, and a decoding circuit that generates a way hit signal in response to a diagnostic mode signal. a third selector for selecting and outputting one of the Weihit signal from the decoding circuit and the Weihit signal from the priority storage means; A control circuit for updating the contents of the storage means is provided.

[Effect]

In the set associative cache memory according to claim (1), when the diagnosis mode is set by the diagnosis mode signal, a way is selected by the way selection signal inputted from the outside.

In the set associative cache memory of claim (2), when the diagnostic mode signal is set to the diagnostic mode, a way is selected by the way selection signal inputted from the outside, and the contents of the priority storage means are changed according to the selection result. Updated.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the set associative type cache memory according to claim (1), which is most suitable for testing the address tag memory 5. In this figure, the same reference numerals as in FIG. 3 indicate the same things, 12 is a diagnostic mode signal, 13 is a way selection signal, 14 is a decoding circuit, 15 is a selector circuit as a third selector, 16
is a way hit signal obtained by decoding the way selection signal 13 by the decoding circuit 14;
7 is a weight signal generated by the LRU bit memory 8 as a priority storage means.

Next, the operation will be explained.

The normal operation of the four-way set associative cache memory shown in FIG. 1 is exactly the same as the operation of the conventional cache memory shown in FIG. 3, and differs only in the operation in the diagnostic mode. The procedure for testing the address tag memory in diagnostic mode will be described below.

First, the diagnostic mode signal 12 is set to "1" and the way selection signal 13 is set to a level corresponding to the way to be selected.

The way selection signal 13 has the number of bits corresponding to the number of ways included in the cache system, and for example, for 4 ways, it has 2 bits.

Next, the contents of the address tag memory 5 of each way are cleared, and the cache system is accessed using an arbitrary address. Since the accessed entry does not have address tag 2 to be hit in any way, an external bus cycle occurs to fetch data to external memory, and part of the previous address is added to the address tag. It is stored in the address tag memory 5 as an address tag. At this time, if the diagnostic mode signal 12 is at the ``''1n level, the selector circuit 15 selects the way hit signal 16, so the way in which the address tag 2 is written is the way select signal 13.
will be determined by.

By repeating this operation for all ways of all entries, a desired test button can be written in all bits of the address tag memory 5.

At this time, it should be noted that when writing the test button to the address tag memory 5 of each entry, the way in which the button is written does not depend on the contents of the LRU bit memory 8, and the way selection signal 13 is always The point is that it only depends on the level. Therefore, without knowing the contents of the LRU bit memory 8, a test button can always be written to any way of any entry in one cycle.

Therefore, all entries in this cache system are sequentially accessed using appropriate address button groups, that is, address button groups that should be hit by the cache and address button groups that should not be hit, so that the cache can correctly determine hits and misses. By checking whether or not the address tag memory 5 is present, the address tag memory 5 can be tested.

Further, FIG. 2 is a block diagram showing an embodiment of the set associative cache memory according to claim (2), which is most suitable for testing the LRU bit memory 8. In this figure, the same reference numerals as in FIG. 1 indicate the same parts, and 18 is a control circuit, in which the way specified by the way hit signal 16 obtained by decoding the way selection signal 13 in the diagnostic mode is the accessed way. It has the function of updating the LRU bit memory 8 as a function.

Therefore, according to this embodiment, when testing the address tag memory 5 in the previous procedure, the L
The bit contents of the RU bit memory 8 can be understood from very simple logic. Although it is necessary to indirectly know whether the LRU bit memory 8 is set to a desired value through subsequent reading operations several times, the setting operation can be easily performed as described above.

〔Effect of the invention〕

As explained above, the set associative cache memory according to claim (1) of the present invention includes a decoding circuit that generates a way hit signal in response to an external way selection signal instructing a specific way, and a diagnostic mode signal. Since a third selector is provided which selects and outputs either the way hit signal from the decoding circuit or the way hit signal from the priority storage means in response to the received way hit signal, it is possible to directly select a way from the outside. This has the effect that the algorithm for creating a test button for diagnosing the address tag memory is greatly simplified.

Further, the set associative cache memory according to claim (2) includes a decoding circuit that generates a way hit signal in response to an external way selection signal instructing a specific way, and a decoding circuit that generates a way hit signal in response to a diagnostic mode signal. a third selector for selecting and outputting either the Weicht signal or the Weicht signal from the priority storage means; and a third selector for selecting and outputting either the Weicht signal or the Weicht signal from the priority storage means; Since a control circuit for updating the contents of the means is provided, it is possible to directly select a way from the outside, and the contents of the priority storage means can be updated according to the selection result, making it possible to diagnose the priority storage means. This has the effect of greatly simplifying the algorithm for creating test patterns.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the set associative cache memory according to claim (1), and FIG.
The figure is a block diagram showing an embodiment of a set associative cache memory according to claim (2), and FIG. 3 is a block diagram of a conventional four-way set associative cache memory. In the figure, 1 is an address, 2 is an address tag, 3 is a set select, 4 is a word select, 5 is an address tag memory, 6 is a valid bit memory, 7 is a data block memory, 8 is an LRU bit memory, and 9 is an address tag Comparator, 10°11 is the 1st. A second selector, 12 is a diagnostic mode signal, 13 is a way selection signal, 14 is a decoding circuit, 15 is a selector circuit, 16.17 is a way hit signal, and 18 is a control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A data block memory that receives an address consisting of an address tag, set select, and word select as input and holds data in the cache memory, and an address tag that stores the address tag in correspondence with the contents of the data block memory. a memory, a valid bit memory for indicating whether the memory in the data block is valid or invalid, a priority storage means for storing data replacement priority for each way, the address tag and the address tag memory. an address tag comparator that compares data in the address tag comparator, a first selector that selects word data by the word select, and a word data from the first selector that is selected and output based on the output of the address tag comparator. In a set associative cache memory having a second selector, a decoding circuit generates a way hit signal in response to an external way selection signal indicating a specific way, and a decoding circuit generates a way hit signal in response to a diagnostic mode signal from the decoding circuit. A set associative type cache memory comprising a third selector that selects and outputs one of the way hit signal and the way hit signal from the priority storage means. (2) A data block memory that receives an address consisting of an address tag, set select, and word select as input and holds data in the cache memory, and an address tag that stores the address tag in correspondence with the contents of the data block memory. a memory, a valid bit memory for indicating whether the memory in the data block is valid or invalid, a priority storage means for storing data replacement priority for each way, the address tag and the address tag memory. an address tag comparator that compares data in the address tag comparator, a first selector that selects word data by the word select, and a word data from the first selector that is selected and output based on the output of the address tag comparator. In a set associative cache memory having a second selector, a decoding circuit generates a way hit signal in response to an external way selection signal indicating a specific way, and a decoding circuit generates a way hit signal in response to a diagnostic mode signal from the decoding circuit. a third selector for selecting and outputting one of the way hit signal and the way hit signal from the priority storage means; A set associative type cache memory, further comprising a control circuit that updates the contents of the priority storage means in accordance with a way hit signal.