JPH0363860B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to signal processing systems, particularly digital wireless communication lines using multi-value quadrature amplitude modulation systems such as 16-value quadrature amplitude modulation (16-QAM) or higher. This invention relates to an economical signal processing method that improves the deterioration of scrambling function that sometimes occurs.

[Conventional technology]

Conventionally, in digital wireless communication systems, scramble processing is performed on transmission signals for the purpose of flattening the transmission spectrum in the radio section and facilitating the extraction of bit timing signals on the receiving side.
This scrambling process is performed in conjunction with the insertion and extraction (multiplexing) of validity check bits and frame synchronization signals necessary for monitoring the radio section.
This is performed by the signal processing devices of the transmitting terminal station and the receiving terminal station. In a microwave band digital wireless communication system with a large transmission capacity, a digital multiplexed signal multiplexed by a digital multiplexing terminal device is input as an input signal, but this digital multiplexed signal is usually Scrambling processing is performed using a predetermined number of stages of pseudorandom codes (PN codes). For this reason, the signal processing device on the radio line side is designed to superimpose this and perform synchronous scrambling processing in synchronization with the frame synchronization signal, thereby achieving the overall goal of flattening the spectrum.

On the other hand, the radio receiving equipment of each intermediate relay station, including the receiving end station, constantly monitors the reception spectrum characteristics of each received signal, and when an abnormality is detected, an adaptive equalization circuit installed in each receiving equipment is activated. The frequency spectrum of the receiver output is compensated to be flat by controlling. The purpose of this compensation is to compensate for changes in transmission band characteristics due to fading or the like in each radio transmission path, and to prevent deterioration of the bit error rate. Therefore, in the conventional signal processing device described above, when the scrambled signal from the digital multiplexing terminal device is cut off and the input to the signal processing device becomes a continuous “1” or “0”, the wireless line side Since only the scrambling process is performed by the signal processing device, spectrum spreading is insufficient and the compensation effect of the transmission band characteristics by the adaptive equalization circuit is reduced. In other words, when multiple digital multiplexed signals are transmitted using one radio carrier wave, such as in a multiphase phase modulation method, if one digital multiplexed signal is disconnected, the transmission quality of other digital multiplexed signals deteriorates. There is a problem that code errors increase.

[Problems to be solved by the invention]

As a method for solving the above-mentioned problems, each signal processing device is provided with a self-synchronized scrambling means and an input signal disconnection detection means for controlling it, and when the input signal is interrupted, this self-synchronized scrambling means is activated. A signal processing device which secures the same effect as scrambling processing using a necessary number of stages of PN codes in conjunction with constantly operating synchronous scrambling processing has been proposed by the applicant in Japanese Patent Application No. 71317/1983. proposed in the book. In modulation methods, such as 4-phase or 8-phase modulation methods, where multiple modulation input signals each play an equal role,
It is necessary to use such a signal processing device for all modulated input signals. However, in a multilevel orthogonal amplitude modulation method such as 16-value QAM, the four modulation input signals input to the modulator are not all equal, as will be described in detail later, and each orthogonal modulation component has an amplitude. a modulation input signal of a large level signal that modulates a large carrier wave;
There is a modulation input signal of a small level signal that modulates a carrier wave with a small amplitude, and its contribution to the spread spectrum is also not the same. Therefore, the above-mentioned patent application does not necessarily apply to all modulated input signals.
Even without providing the signal processing device described in the specification of No. 59-71317, it is possible to achieve a configuration that does not interfere with the flattening of the spectrum and the operation of the equalization circuit of each receiving device. The object of the present invention is to
A signal processing method that does not adversely affect the spread spectrum effect even when the input digital multiplexed signal is interrupted in a digital wireless communication line using a multilevel quadrature amplitude modulation method of QAM or higher, and allows the line to be configured economically. The goal is to provide the following.

[Means to solve the problem]

The signal processing method of the present invention is a signal processing method that performs synchronous scrambling and descrambling processing of a transmission signal at a transmitting terminal station and a receiving terminal station of a digital wireless communication line using a 16-value or higher multi-value orthogonal amplitude modulation method. , among the plurality of modulated input signals of orthogonal modulation components, the modulated input signal, which is a large level signal with a high carrier signal level, is input to the transmitting terminal station from a digital multiplexing terminal device. a signal input disconnection detecting means for detecting a signal input disconnection of the digital multiplexed signal and generating an input disconnection information signal and a signal input status signal; and a synchronous type controlled by the signal input status signal when the digital multiplexed signal is disconnected. and a self-synchronized scrambling means for superimposing a scramble operation on the scrambled signal, the self-synchronized scrambling means being activated by the input disconnection information signal sent from the transmitting terminal station to the receiving terminal side. a self-synchronized descrambling means for restoring the scrambling operation of the scrambling means; The present invention is configured so that it does not include self-synchronous scrambling means and self-synchronous descrambling means.

[Effect]

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a vector diagram showing the amplitude and phase of a 16-value QAM signal. As shown in Figure 1, 16 values
16 signal vector points A ₁ of QAM modulated signal
〜A ₄ , B ₁ 〜 _{B 4} , C ₁ 〜 C ₄ , D ₁ 〜 D ₄ are A, B,
C and D four-phase phase modulation signals (indicated by solid arrows)
It is obtained by superimposing a four-phase phase modulation signal (indicated by a broken arrow) obtained by orthogonally modulating a small level signal with an amplitude S=L/2. 16 values like this
The four modulation input signals for QAM are divided into large level signals and small level signals, and their contributions to spectrum spread are also different.
Naturally, the contribution for large level signals is large,
The contribution for small level signals is considered to be small. In fact, in a line using conventionally known signal processing equipment, the digital multiplexed signal from the digital multiplexing terminal equipment was disconnected, and the number of stages of the equivalent PN code for scrambling received by the modulated input signal was reduced. When it is a modulated input signal for a small level signal, the deterioration in the bit error rate of other signal systems is slight and can be ignored, but when it is a modulated input signal for a large level signal, the effect is ignored. I can't. Therefore, the modulation input signal system for large level signals is
Using the signal processing device described in the specification, when the digital multiplexed signal from the digital multiplexing terminal equipment is cut off, the self-synchronized scrambling circuit works to maintain the spread spectrum effect and modulate the small level signal. If a conventional signal processing device is used in the input signal system to avoid complicating the circuit, there will be almost no adverse effect on the line quality even if any digital multiplexed signal is interrupted, and it will also be economical. It is possible to configure various wireless lines.

〔Example〕

Figure 2 is a block diagram of the transmitting terminal station according to an embodiment of the present invention, and Figure 3 is a block diagram of the receiving terminal station.
This figure shows the configuration of one transmission direction of a value QAM digital wireless communication line. In FIG. 2, four systems of digital multiplexed signals 101 to 104 that perform 16-QAM modulation on one radio carrier wave are each output to N
It is scrambled with the PN code of the stage,
Of these, 101 and 103, which are the modulation input signals of the small level signal, are sent to the modulation circuit of the transmitting device 3 via the conventionally used normal transmission signal processing device 1.
02 and 104 are connected to the modulation circuit of the transmitting device 3 via the transmitting signal processing device 2 equipped with signal input disconnection detecting means and self-synchronized scrambling means described in Japanese Patent Application No. 59-71731. The transmission signal processing device 1 for small level signals includes a code conversion circuit 1
1. Transmission code processing circuit 12, scrambling circuit 1
3 and a scramble signal generation circuit (SCR signal generation circuit) 14, a bipolar format digital multiplexed signal 101 is converted into a unipolar signal by a code conversion circuit 11, and a transmission code processing circuit 1
2, the speed is converted, and additional bits such as a frame synchronization signal and a parity check bit for monitoring the radio section are inserted. This speed-converted signal is scrambled in the scramble circuit 13 in synchronization with the frame synchronization signal by the M-stage PN code generated by the scramble signal generation circuit 14 under the control of the timing signal 105 from the transmission code processing circuit 12. A modulated input signal 106 that has been subjected to equivalent scrambling processing according to the M+N stage PN code is sent to the transmitter 3. When the digital multiplexed signal 101 is interrupted due to a failure of the digital multiplexing terminal equipment, the modulated input signal 106 is converted to the M-stage PN by the scramble circuit 13.
The signal is only subjected to scrambling processing using the code.

On the other hand, the transmission signal processing device 2 for large level signals includes a code conversion circuit 21, a transmission code processing circuit 22, a scramble circuit 23, a scramble signal generation circuit (SCR signal generation circuit) 24, an input disconnection detection circuit 25, a Synchronous scrambling circuit (S.
SCR circuit) 26, self-synchronous scramble signal control circuit (S.SCR control circuit) 27, and self-synchronous scramble signal generation circuit (S.SCR generation circuit)
28, and operates as follows. The digital multiplexed signal 102 is sent to the code conversion circuit 21
(same as 11), transmission code processing circuit 22, scramble circuit 23 (same as 13), and scramble signal generation circuit 24 (same as 14), as in the case of the transmission signal processing device 1 for small level signals described above. After speed conversion (digital multiplexed signal 101
Even if signals 104 to 104 are asynchronous, each signal is synchronized after speed conversion and operates using the same bit clock signal) and is scrambled and applied to the self-synchronized scrambling circuit 26. When the digital multiplexed signal 102 is normally input, no scramble signal is input from the self-synchronous scramble signal control circuit 27 to the self-synchronous scramble circuit 26, and therefore the signal from the scramble circuit 23 is input as modulation. signal 107
It is sent to the transmitting device 3 as a. If the digital multiplexed signal 102 is disconnected, the input disconnection detection circuit 25 detects this and generates an input disconnection information signal 108 and a signal input status signal 109, which are sent to the transmission code processing circuit 22 and the self-synchronized scrambling circuit, respectively. The signal is sent to the signal control circuit 27. Transmission signal processing circuit 2
When receiving the input disconnection information signal, the terminal 2 changes the sign of the input disconnection information bit among the additional bits and transmits this information to the receiving terminal side. In the scramble circuit 23, scrambling processing is performed using the M-stage PN code generated by the scramble signal generation circuit 24 as described above, but since the digital multiplexed signal 102 is in a disconnected state, the PN code signal remains unchanged. Self-synchronous scrambling circuit 26
is input. The self-synchronized scramble signal control circuit 27 that receives the signal input status signal 109 supplies the M′-stage PN code generated by the self-synchronized scramble signal generation circuit 28 to the self-synchronized scramble circuit 26, and performs self-synchronized scrambling. circuit 2
6 superimposes a scramble process on the output of the scramble circuit 23 and sends the output to the transmitter 3. Self-synchronous scramble signal generation circuit 28
is configured to receive feedback of the output of the self-synchronous scrambling circuit 26 and to set a scramble signal using the timing signal 110 from the transmission code processing circuit 22.

According to the above configuration, the digital multiplexed signal 1
When 01 and 102 are input correctly,
The number of equivalent PN code stages that contribute to the spectrum spread of modulated input signals 106 and 107 are both N+.
M, but the equivalent value of the modulated input signals 106 and 107 when the digital multiplex signal is interrupted is
The number of stages of the PN code is N for the former, but N for the latter.
+M′ and if M′=M is selected, there will be no change at all, and it will not affect the operation of the adaptive equalization circuit of each radio receiving device described above, and it is possible to prevent deterioration of line quality. . As mentioned above, the modulation input signal of the small level signal has a small contribution to the spectrum spread, so even if the number of stages of the equivalent PN code decreases due to disconnection of the digital multiplexed signal 101, it has little effect on the line quality. This can be ignored, and an economical line configuration can be achieved by avoiding complication of the transmission signal processing device.

The receiving terminal station side is configured as shown in FIG. 3, corresponding to the configuration of the transmitting terminal station side in FIG. 2. That is,
Among the demodulator outputs of the receiving device 4, the demodulation power signals 111 and 113 of small level signals are processed by a conventionally known reception signal processing device 5, and the demodulation output signals 112 and 114 of large level signals are processed by the Japanese Patent Application No. 59-71317. A received signal processing device 6 described in the book is connected.
The received signal processing device 5 is composed of a frame synchronization circuit 51, a descrambling circuit 52, a received code processing circuit 53, and a code conversion circuit 54, and the demodulated output signal 111 is frame synchronized in the frame synchronization circuit 51 and descrambled. In circuit 52, the scrambling process by scramble circuit 13 on the transmitting side is restored using the M-stage PN code, and the speed is converted in reception code processing circuit 54 to generate additional bits such as a frame synchronization signal for wireless section monitoring and parity check bits. After the signal is removed, the signal is sent to the code conversion circuit 54, where it is converted into a bipolar signal, and sent to the receiving side digital multiplexing terminal equipment (not shown).

On the other hand, the received signal processing device 6 includes a frame synchronization circuit 61, a descrambling circuit 62 (same as 52), a received code processing circuit 63 (same as 53), and a code conversion circuit 64 (same as 54). Self-synchronous descrambling circuit (S.DSCR circuit) 65, input disconnection detection circuit 66, self-synchronous descrambling signal generation circuit (S.DSCR generation circuit) 67, and self-synchronous descrambling signal control circuit (S.DSCR control) circuit) 68. If the digital multiplexed signal 102 is normally input on the transmitting side, the input loss detection circuit 66 checks the signal of the input loss information bit among the additional bits, and controls the self-synchronized descrambling signal control circuit 68. Since the descrambling signal 115 is not sent to the self-synchronous descrambling circuit 65, the self-synchronous descrambling circuit 65 sends the input as is to the output. Therefore, the demodulated output signal 112 is processed in the same manner as in the case of the received signal processing device 5 described above,
The bipolar signal is supplied from the code conversion circuit 64 to the digital multiplexing terminal device on the receiving side. When the digital multiplexed signal 102 is disconnected on the transmitting side, an input disconnection information signal is sent to the input disconnection detection circuit 6.
6 detects this, controls the self-synchronized descramble signal control circuit 68, sends the descramble signal generated by the self-synchronized descramble signal generation circuit 67 to the self-synchronized descramble circuit 65, It is configured to restore the scrambling process of the self-synchronous scrambling circuit 23. Self-synchronized descrambling signal generation circuit 67
is the timing signal 1 from the frame synchronization circuit 61
16 and is configured to generate a descrambling signal.

The embodiment shown in FIG. 2 described above shows a case where four systems of independent digital multiplexed signals 101 to 104 are transmitted using one radio carrier wave, and digital multiplexed signals 102 and 104 for large level signals are transmitted.
Each of the transmission signal processing devices 2 is provided with an input disconnection detection circuit 25. However, one system of digital multiplexed signal with a high bit rate (approximately 4 times) is divided into four, and one radio carrier wave is divided into 16 values.
In the case of QAM modulation and transmission, one detection circuit is provided in the transmission circuit before division as a signal input disconnection detection means, and its output is used by the transmission signal processing device (2 in Figure 2) for two large level signals. (not including the input disconnection detection circuit 25), the spread spectrum state of the wireless line can be kept almost constant regardless of the presence or absence of an input signal.

In the above-described embodiment, the case of the 16-value QAM method has been described, but the technical concept of the present invention can also be applied to the case of a multi-value quadrature amplitude modulation method. That is, the 64-value QAM modulation signal is considered to be a composite signal obtained by orthogonally modulating three carrier waves with different amplitudes, and the carrier wave amplitude is 4:2:1. Therefore, for a modulated input signal of a large level signal with the largest amplitude, the transmitting side is equipped with the same self-synchronized scrambling means and signal input disconnection detecting means as the transmitting signal processing device 2 of FIG. By being equipped with a self-synchronized descrambling means similar to the received signal processing device 6 shown in FIG. Conventionally known transmitting and receiving signal processing devices (1 in Fig. 2 and 5 in Fig. 3) that maintain line quality and do not have the above-mentioned means for modulating input signals of small level signals with the smallest carrier wave amplitude are used. ), it is possible to configure a digital wireless communication line that maintains economic efficiency without deteriorating quality. Note that for a modulated input signal of a middle level signal with an intermediate carrier wave amplitude, the above-mentioned means may be provided in the same manner as for large level signals if characteristics are important, but if economy is emphasized. In some cases, the above-mentioned means may not be provided.

〔Effect of the invention〕

As explained in detail above, according to the signal processing method of the present invention, the input signal from the digital multiplexing terminal equipment is disconnected in a digital wireless communication line using a multi-value quadrature amplitude modulation method of 16-value QAM or higher. Even in such cases, the scrambling process maintains the purpose of spectrum flattening, and has the effect of economically configuring the line without degrading the line quality.

[Brief explanation of drawings]

Fig. 1 is a vector diagram explaining the amplitude and phase of a 16-value QAM signal, Fig. 2 is a block diagram of the transmitting side according to an embodiment of the present invention, and Fig. 3 is a block diagram of the receiving side corresponding to Fig. 2. It is. 1, 2... Transmission signal processing device, 3... Transmission device, 4... Receiving device, 5, 6... Reception signal processing device, 11, 21, 54, 64... Code conversion circuit,
12, 22... Transmission code processing circuit, 13, 23...
...Scramble circuit, 14, 24...Scramble signal generation circuit (SCR signal generation circuit), 25, 6
6... Input disconnection detection circuit, 26... Self-synchronous scramble circuit (S.SCR circuit), 27... Self-synchronous scramble signal control circuit (S.SCR control circuit),
28... Self-synchronous scramble signal generation circuit (S.SCR generation circuit), 51, 61... Frame synchronization circuit, 52, 62... Descrambling circuit, 5
3, 63... Reception code processing circuit, 65... Self-synchronous descrambling circuit (S.DSCR circuit), 67
...Self-synchronous descrambling signal generation circuit (S.
DSCR generation circuit), 68... Self-synchronous descrambling signal control circuit (S.DSCR control circuit).

Claims (1)

[Claims] 1. In a signal processing method that performs synchronous scrambling and descrambling processing on transmission signals at the transmitting and receiving terminal stations of a digital wireless communication line using a 16-value or higher multivalue orthogonal amplitude modulation method, each orthogonal modulation component is For each modulated input signal, which is a large level signal with a high carrier wave signal level among a plurality of modulated input signals, the transmitting terminal station receives a signal input disconnection of a digital multiplexed signal input from a digital multiplexing terminal device. signal input disconnection detection means for detecting an input disconnection information signal and a signal input status signal; self-synchronized scrambling means that performs a scrambling operation, and is activated by the input disconnection information signal sent from the transmitting terminal station to the receiving terminal station side to restore the scrambling operation of the self-synchronized scrambling means. The self-synchronizing scrambling means includes a self-synchronizing descrambling means, and the self-synchronizing scrambling means and the self-synchronizing descramble means for the modulated input signal of a small level signal having a low carrier signal level among the plurality of modulated input signals of each orthogonal modulation component. A signal processing method characterized by not having a type descrambling means.