JPH0363883A - Zigzag address generation circuit - Google Patents

Abstract

PURPOSE:To compress a circuit scale and to accelerate the generation of a zigzag address by using two up/down counters, and feeding back coincidence with a constant value and underflow to a control part. CONSTITUTION:The up/down counters 1 and 2 which output address values in directions of X and Y by counting up and down a clock and output an underflow signal when a down count value reaches 0, and comparators 3 and 4 which output a coincidence signal when an output address value reaches (n-1) when counting up are provided. When the counter on one side generates the underflow signal, the counting up and down of both counters are switched by stopping the counting of the counter in the next clock period, and after counting (n), the switching of the counting up and down of both counters in the next clock period are performed when the coincidence detection signal of the comparator on one side is outputted. Furthermore, the counting of the counter is stopped in the next clock period, and the generation of the address is completed when the counting of both counters 1 and 2 reach (n). In such a way, the zigzag address generation circuit with small circuit scale and operable at high speed can be obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding a zigzag address generation circuit for generating an address for reading DCT converted data, an object of the present invention is to provide a zigzag address generation circuit that has a small circuit scale and can operate at high speed. In the address generation circuit for zigzag tracing of ×n pixel blocks, an up/down counter counts up and down the clock to output address values in the X and Y directions, and outputs an underflow signal when the count reaches 0. and a comparator that outputs a coincidence detection signal when the output address value reaches n-1 during up-counting. Initially, O is loaded into both counters, one is counted up and the other is down-counted, and one of the counters is When a counter underflow signal is generated, the counter stops counting for a certain clock period, and both counters are switched between up and down counting, and after n counts, when a match detection signal is output from one comparator, both counters start counting in the next clock period. close-up,
The down-counting is switched, and the counting of the counter is stopped for the next clock period, and the address signals of both counters are terminated when n is counted.

(Industrial Field of Application) The present invention provides DCT (Discrete CT) of image data.
This invention relates to a zigzag address generation circuit for generating a DCT-transformed data read address when band compression is performed by Co51ne Transform) transformation.

Pixel data is characterized in that power is concentrated on the low frequency side. Therefore, band compression becomes possible by separating the low frequency region where power is concentrated using DCT transformation and transmitting it.

In order to sequentially extract low frequency components in which power is concentrated from DCT-transformed image data, an address signal that traces two-dimensional pixel data in a zigzag pattern is required.

A circuit that generates such a zigzag address is required to be small in circuit scale and capable of operating at high speed.

[Conventional technology]

FIGS. 5A, 5B, and 5C are diagrams illustrating pixel data and the generation of zigzag addresses for the pixel data.

FIG. 5(a) shows an 8×8 pixel block.

For pixel data as shown in FIG. 5(a), two-dimensional DC
When the pixel data is discretely divided in the frequency direction by T-transform and transformed, the transformed frequency components are shown in Figure 5 (b
), a DC component appears in the upper left part, and high frequency components gradually appear toward the lower right.

In order to sequentially extract each frequency component from the pixel data whose frequency components are separated in this way, from the low frequency component where the power is concentrated to the high frequency component, it is necessary to
As shown in Figure (C), the components of each frequency may be read out using addresses that start from the upper left and are traced diagonally in a zigzag manner.

Conventionally, as a circuit for generating such a zigzag address, a circuit has been used in which the zigzag address is written in a read-only memory (ROM) and the required address is generated by sequentially reading the zigzag address. It was getting worse.

[Problem to be solved by the invention]

In the conventional zigzag address generation circuit, the ROM
This necessitates a circuit for generating addresses for the ROM, which makes it difficult to reduce the circuit scale, and there are problems in that the speed at which addresses are generated is determined by the operating speed of the ROM.

The present invention is an attempt to solve the problems of the prior art as described above, and it is possible to reduce the circuit scale and also reduce the ROM.
It is an object of the present invention to provide a zigzag address generation circuit whose address generation speed is not limited by the operating speed of the zigzag address generation circuit.

[Means to solve the problem]

As shown in FIG. 1, the present invention has an nxn
To generate an address for zigzag tracing a pixel block, an up/down counter 1.2 and a comparator 3 are used.
, 4, and a control section 5.

The up/down counter 1.2 counts up or down the clock according to the instruction, respectively.
, and outputs the address value in the Y direction, and also outputs an underflow signal when down-counting is instructed at the count value O.

Comparators 3 and 4 convert the output address values of counters 1 and 2 into (
n-1), and when they match, a match detection signal is output.

In the control unit 5, first, O is loaded into both counters, one counter is counted up and the other counter is counted down, and when an underflow signal is generated from one counter, the next clock period is started. Then, the process of stopping the counting of this counter and switching between up-counting and down-counting of both counters is repeated.

After n has been counted in either counter, when a match detection signal is output from either counter, both counters are switched between up-counting and down-counting in the next clock period, and also in the next clock period. In this step, the process of stopping the counting of this counter is repeated.

Then, when the count values of both counters reach n, address generation is terminated.

[Effect]

In the zigzag address generation circuit of the present invention, when an enable signal is given, the clock is counted up or down according to the instruction, and
Two up/down counters that output an address value in the Y direction and also output an underflow signal when downcounting is instructed with a count value of 0, and the output address value of each counter is set to a constant value (n-1). An address for zigzag tracing an n×n pixel block is generated by two comparators which output a match detection signal when a match is found.

At this time, the control unit performs the following control. In other words, in the initial state, both counters are loaded with 0, and one counter is placed in an up-counting state and the other counter is placed in a down-counting state to perform counting. . This performs diagonal tracing. In this case, when an underflow signal is generated from one of the counters, that is, when X or Y becomes O when counting down in the X or Y direction, by stopping the counting of that counter in the next clock period, , χ or Y is O
Y or X is incremented while remaining at . At the same time, both counters are switched between up-counting and down-counting, thereby starting diagonal tracing in the opposite direction. This process is repeated.

After the maximum value n has been counted in either counter, that is, after reaching the upper right or lower left point, when a match detection signal is output from any comparator in the up-count state, the next clock period Both counters are switched between up-counting and down-counting, and the counting of the counter to which the coincidence detection signal is output is stopped in the next clock period. This keeps X or Y at n and Y or X +1
trace is then started diagonally in the opposite direction. This process is also repeated.

In this way, when the count values of both counters finally reach n, that is, when the lower right point is reached, the counting of both counters is stopped, thereby completing the series of address generation.

〔Example〕

FIG. 2 shows the configuration of one embodiment of the present invention.

1 is the first up/down counter (U/D C0UT
) and generates an X-direction address (X-ADR), 2
is the second up/down counter (U/D C0UT)
A Y-direction address (Y-ADR) is generated. Up-down counter l.

2 is enable (EN), down count (D), up count (U) switching (D/lJ) as a control signal
and load (LO) signals. Also, on the output side of the up/down counter 1.2, there is a comparator (C
MP) 3.4 is provided. Furthermore, a control section (CONT) 5 is provided to control these operations.

FIG. 3 is a time chart (1) showing an example of the operation in the first embodiment shown in FIG. 2, and illustrates the case where it is applied to an 8×8 pixel block.

The operation of the zigzag address generation circuit of the present invention will be explained below based on these two figures.

The desired zigzag address is one in which the addresses (ADR) in the X and Y directions change sequentially from the upper left point (0°0) every clock (CLK) as shown in FIG. In the figure, the arrow indicates that the enable signal is stopped for one clock period. Also number (1)~
The circle corresponds to the following description.

(1) The control unit 5 first loads O into both up/down counters 1 and 2 by giving the LO multiplication signal. This generates address (0,0).

At this time, the control unit 5 operates in the X direction (up/down counter 1)
The D/U signal in the Y direction (up/down counter 2) is set in the D state. This generates an underflow (UF) signal in the Y direction. U
This is generated from the up/down counter when a downcount is instructed in a state where the F times signal count is 0.

(2) With the next CLK signal, the X direction changes to 1, but the Y direction is kept at 0 because the UF double signal was generated at the previous timing, and the EN signal is stopped and disabled. Therefore, address (1, O) is generated.

At this time, the control unit 5 switches the D/U signal in the X direction to the D state and switches the D/U signal in the Y direction to the U state due to the generation of the UF multiplied signal in the Y direction in the previous timing. .

(3) With the next CLK signal, the X direction changes to O, the Y direction changes to l, and therefore address (0, 1) is generated.

At this time, the D/U signal in the X direction remains D, and therefore a UF multiplied signal is generated in the X direction. The D/U signal in the Y direction is U.
It remains as it is.

(4) At the next CLK signal, the EN signal stops in the X direction and becomes 0.
, the Y direction changes to 2, and the address (0,2)
occurs.

At this time, the control unit 5 switches the D/U signal in the X direction to the U state and switches the D/U signal in the Y direction to the D state due to the generation of the UF multiplied signal in the X direction at the previous timing.

(5) With the next CLK signal, the X direction changes to 1, the Y direction also changes to 1, and therefore the address (1, 1) is generated.

At this time, the D/U signal in the X direction remains U, and the D/U signal in the Y direction remains D.

(6) With the next CLK signal, the X direction changes to 2 and the Y direction changes to 0, thus generating address (2, O).

At this time, the D/U signal in the X direction remains U, the D/U signal in the Y direction remains D, and therefore the UF signal in the Y direction remains U.
A double signal is generated.

(7) With the next CLK signal, the X direction changes to 3, but the Y direction stops the EN signal and is kept at O, so the address (
3, O) occurs.

At this time, the control unit 5 switches the D/U signal in the X direction to the D state and switches the D/U signal in the Y direction to the U state because the UF multiplied signal was generated in the Y direction at the previous timing.

(8) With the next CLK signal, the X direction changes to 2 and the Y direction changes to 1, thus generating address (2, 1).

At this time, the D/U signal in the X direction remains D, and the D/U signal in the Y direction remains U.

Similarly, every time 0 occurs in the X or Y direction, U
The F times signal is generated, and the count progresses gradually while switching between down-counting and up-counting, and a zigzag address is generated, but when the lower left point, that is, address (0, 7) is reached, the control method changes. .

(9) Comparators 3.4 compare the X address and Y address with "6", and when they match during up-counting, generate the XCMP signal and YCMP signal, respectively.
These signals become valid from the time 7 first appears at the X address, as indicated by the circle in FIG.

The D/U signal in the X direction is D and the D/U signal in the Y direction is U up to address (1, 6), but due to the generation of the YCMP signal, the next CLK signal
), the D/U signal in the X direction becomes U, and the D/U signal in the Y direction becomes D. At the same time, a flip-flop (FF) (not shown) in the control section 5 operates to set the value 7 in the Y direction.

00) With the next CLK signal, the X direction changes to 1, but the Y direction remains at 7, so an address (1°) is generated.

At this time, the D/U signal in the X direction remains D, and the D/U signal in the Y direction remains D.

(11) With the next CLK signal, the X direction changes to 2 and the Y direction changes to 6. Therefore, address (2,6) is generated.

At this time, the D/U signal in the X direction remains U, and the D/U signal in the Y direction remains D.

02) When the count progresses and the address becomes (6, 2), the XCMP signal is generated, and when the address becomes (7, 1) by the next CLK signal, the D/U signal in the X direction becomes D. , the D/U signal in the Y direction is U. At the same time, the flip-flop operates to set the value 7 in the X direction.

Side The next CLK signal keeps the X direction at 7, but
The Y direction changes to 2, thus generating an address (7°2).

At this time, the D/U signal in the X direction remains D, and the D/U signal in the Y direction remains D.

Thereafter, in the same way, each time 6 occurs in the X or Y direction in the up-counting state, the χCMP signal or YCMP signal is generated, and the counting gradually progresses while switching between down-counting and up-counting of both counters.
A zigzag address occurs. When the lower right point, ie, the address (7,'?), is generated, the series of address generation ends. Then, the next time the LO signal is generated, it returns to the initial state.

Figure 4 shows the time chart of each signal (2) showing the above operation.
), <X> indicates the X direction, and <Y> indicates the Y direction.

In the X direction, EN is the X direction enable signal, LO
is a load signal, D/U is a down count up count switching signal, X-ADH is an address signal in the X direction,
CMP is a comparison match detection signal with 6 at the time of amplifier counting in the X direction, and XUF is an underflow signal.

In addition, in the Y direction, EN is a Y direction enable signal,
LO is a load signal, D/U is a down count up count switching signal, Y-ADR is an address signal in the Y direction, YCMP is a comparison match detection signal with 6 when counting up in the Y direction, and YUF is an underflow signal. . In addition, CMP/UF is connected to the XCMP signal or VCMP signal.
It shows the switching state of using either the UF signal or the YUF signal.

[Effects of the Invention] As described above, according to the present invention, two up/down counters are used, and the control unit receives the enable signal (EN), down count up count switching signal (D/U), and Zigzag is controlled by controlling the load signal (LO) and feeding back the coincidence signal (XCMP, YCMP) with constant values of the X address and Y address and the underflow signal (OF) in the X and Y directions to the control unit. - Can generate addresses.

Therefore, according to the present invention, the circuit scale can be considerably reduced compared to a zigzag address generation circuit using a ROM. Furthermore, since there is no speed limit due to the read cycle time of the ROM, etc., zigzag addresses can be generated at high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIGS. 3 and 4 are time charts (1) showing the operation of the circuit of the present invention. and (2)
, FIGS. 5(a), 5(c), and 5(c) are diagrams for explaining pixel data and its zigzag trace. 1.2 is up/down counter (U/D C0UT)
, 3.4 is a comparator (CMP), 5 is a control unit (CONT)
It is.

Claims (1)

[Claims] In a circuit that generates an address for zigzag tracing an n×n pixel block, the clock is counted up or down in accordance with instructions to output address values in the X and Y directions, and Up/down counters (1, 2) that output an underflow signal when the count reaches 0, and a match detection signal when the output address value of the counter (1, 2) reaches (n-1) during the up count. At first, both counters (1, 2) are loaded with 0, one counter is counted up and the other counter is down counted, and one of the counters is loaded with 0. When an underflow signal is generated from a counter, the counter stops counting in the next clock period, and both counters are switched between up-counting and down-counting, and after n is counted in either counter, either When a match detection signal is output from the comparator, both counters are switched between up-counting and down-counting in the next clock period, and counting of the counters is stopped in the next clock period, and the count value of both counters is changed. A zigzag address generation circuit characterized in that address generation is terminated when both become n.