JPH0363993A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent memory cell data from being destroyed by continuously holding the level of a chip activating signal until operation under execution is finished and further outputting a ready signal. CONSTITUTION:When the state of the chip activating signal 101 is changed, a change signal 102 is outputted from a latch circuit 2 and sent to a chip activating signal control circuit 1. Corresponding to the input of the change signal 102, the respective states of a status signal 105, refresh operation status signal 109 and precharge operation status signal 111 are investigated. When any one of a read/write control circuit 3, refresh control circuit 4 and precharge control circuit 5 is under operation, a hold signal is outputted to the latch circuit 2 and the level of the internal chip activating signal 103 is held as it is. Simultaneously, the prescribed ready signal 113 is outputted to an external part. Thus, a state that the cell data are destroyed can be prevented in advance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a dynamic semiconductor memory device that prevents malfunctions due to glitch noise in chip activation signals.

[Conventional technology]

Conventionally, this type of semiconductor memory device has generally been structured to operate in complete synchronization with a chip activation signal. Therefore, the structure is such that when the chip activation signal goes low, the operation starts, and when it goes high, the operation ends even if the operation is in progress.

[Problem to be solved by the invention]

The above-mentioned conventional semiconductor memory device has a tR structure in which when the chip activation signal becomes high level, the operation ends even if it is in operation, so a glitch occurs in the chip activation signal. When noise is superimposed, the cell
The disadvantage is that the data will be destroyed. Therefore,
In a conventional semiconductor memory device, the minimum value of the high level width and low level width of the chip activation signal is defined, and the input of glitch noise is prohibited.

[Means to solve the problem]

The semiconductor memory device of the present invention includes a latch circuit that holds a chip activation signal input from the outside, a read/write control circuit that performs a read/write operation, a refresh control circuit that performs a refresh operation, and a precharge operation. monitors the operation start signal and operation end signal outputted from the precharge control circuit, the read/write control circuit, the refresh control circuit, and the precharge control circuit, and causes the chip activation signal to change before the operation ends. In this case, the device is configured to include a chip activation signal control circuit that controls the latch circuit to hold the chip activation signal and also outputs a predetermined ready signal to the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a chip activation signal control circuit 1, a latch circuit 2, a read/write 111161 circuit 3, a refresh control circuit 4, a precharge control circuit 5, and a column.・Decoder 6 and address buffer 7
, a row decoder 8 , a memory cell array 9 ,
It is composed of:

In FIG. 1, a chip activation signal 101 input from the outside is latched by a latch circuit 2 and transmitted to a read/write control circuit 3, a refresh control circuit 4, and a precharge control circuit 5.

The read/write control circuit 3 is activated during a read/write operation, and when the internal chip activation signal 103 becomes low level, a read/write operation status signal 105 is sent to the chip activation signal control circuit l. After the signal is output and the start of operation is notified, the address, buffer drive signal 106 and row - Decoder drive signal 107, column decoder drive signal 10g and sense amplifier drive signal 110 are output.

When the read/write operation in the read/write control circuit 3 is completed, a read/write operation status signal 105 is sent to the precharge control circuit 5 and the chip activation signal MI11 circuit 1 to notify the end of the operation. . Refresh: The L9 control circuit 4 is activated during refresh operation, and when the internal chip activation signal 103 sent from the latch circuit 2 becomes low level, the refresh operation status signal 109 is output and the chip is activated. The signal is sent to the control circuit 1 to signal the start of operation. After that, from the refresh control circuit 4,
Address buffer drive signal 106, row decoder drive signal 107 and sense amplifier drive signal 110 are output to address buffer 7, row decoder 8 and sense amplifier of memory cell array 9, respectively. When the refresh operation by the refresh control circuit is completed, the refresh control circuit 4 outputs a refresh operation status signal 109 to the precharge control circuit 5 and the chip activation control circuit 1, thereby transmitting the completion of the refresh operation. Ruru.

The precharge control circuit 5 is activated after the read/write operation and the refresh operation, and receives an internal chip activation signal 10 sent from the latch circuit 2.
3 becomes high level, the precharge operation status signal 11 is sent to the chip activation signal III control circuit 1.
After 1 is output to signal the start of operation, a precharge signal 112 is output to memory cell array 9.

Further, as the operation in the precharge control circuit 5 is completed, a precharge operation status signal 111 is output to the read/write control circuit 3, the refresh @ control circuit 4, and the chip activation signal control circuit 1. The end of the operation is communicated.

In the chip activation signal control circuit 1, each operation status signal 1 output from the read/write control circuit 3, the refresh control circuit 4, and the precharge control circuit 5 is
05, 109, and 10, and the change signal 102 output from the latch circuit 2 are monitored, and through this monitoring action, changes in the chip activation signal 101 are detected during read/write, refresh, and precharge operations. This prevents a situation in which the operation is interrupted and the cell data is destroyed.

That is, when a change occurs in the state of the chip activation signal 10F, a change signal 102 is outputted from the latch circuit 2 and sent to the chip activation signal control circuit 1. In the chip activation signal control circuit l, in response to the input of the change signal 102, each status signal, that is, the read/write operation status signal 105, the refresh operation status signal 109, and the precharge operation status signal 1 is activated.
11 is checked, and if the previous operation has been completed, the level of the internal chip activation signal 103 output from the latch circuit 2 is changed. On the contrary, lead/
If any of the write control circuit 3, refresh control circuit 4, and precharge control circuit 5 is in operation, the holding signal 104 is output to the latch circuit 2, and the change in the chip activation signal 101 is suspended, and the internal The level of the chip activation signal 103 is maintained as it is. At the same time, a predetermined ready signal 113 is sent to the outside.
is output.

Next, after the operation is completed, the level of the holding signal 104 outputted to the latch circuit 2 is changed, and the level of the internal chip activation signal 103 outputted from the latch circuit 2 is changed.

Furthermore, if the completed operation is a read/write or refresh operation, the output of the ready signal 113 is stopped immediately after the next precharge operation is completed.

The ready signal 113 is kept at the level of the chip activation signal 101 internally due to bridge noise or the like, and is continuously output while the cycle is extended until the end of the operation. Therefore, by inputting this ready signal 113 to the CPU's ready terminal or the like, it is possible to prevent other accesses from overlapping during a cycle that is being extended internally.

〔Effect of the invention〕

As described above in detail, the present invention provides that even when the chip activation signal changes without being able to maintain its minimum value, the chip activation signal remains unchanged until the ongoing operation is completed. By continuing to maintain the level of and outputting a ready signal, it is possible to prevent memory cell data from being destroyed.

Control circuit, 4...Refresh control circuit, 5.-
. . . Precharge control circuit, 6 . . . Column decoder 27 . . . Address buffer, 8 . .
...-Row decoder, 9.--Memory cell array.

Claims (1)

[Scope of Claims] A latch circuit that holds a chip activation signal input from the outside, a read/write control circuit that performs a read/write operation, a refresh control circuit that performs a refresh operation, and a precharge circuit that performs a precharge operation. Monitors the operation start signal and operation end signal output from the charge control circuit, the read/write control circuit, the refresh control circuit, and the precharge control circuit, and when the chip activation signal changes before the operation ends. A semiconductor memory device comprising: a chip activation signal control circuit that controls the latch circuit to hold the chip activation signal and further outputs a predetermined ready signal to the outside. .