JPH03639B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a waveform reading device suitable for simultaneously generating a plurality of signals of different frequencies, such as in an electronic musical instrument. Conventional configurations and their problems Conventionally, in the field of electronic musical instruments, there are two methods for simultaneously generating musical tones of different frequencies corresponding to multiple keys: a method with independent waveform generators, and a method with a single waveform generator. There is a method in which waveforms of multiple frequencies are generated simultaneously by operating in a time-divisional manner. When generating musical sound waveforms digitally, the former method has the disadvantage that it requires as many DA converters as there are waveform generators to convert digital signals into analog signals. In the latter case, since one waveform generator is operated in a time-division manner, sample values are inevitably generated. It is necessary to use a DA converter when outputting these sample values. Conventionally, a method has been used that adds multiple sample values and then performs DA conversion. In this case, only one DA converter is required, but since the dynamic range of the addition result increases, the disadvantage is that a large number of bits is required in the DA converter in order to accurately DA convert the addition result. . Further, the plurality of sample values are required to be values sampled at the operating frequency of the DA converter. That is, each of the plurality of musical tones must be calculated assuming a common sampling frequency. However, the frequencies of multiple musical tones generally consist of 12 different frequencies according to 12 equal temperament, and all these frequencies and the sampling frequency have a harmonic relationship (simply put, the sampling frequency is an integral multiple of the fundamental frequency of the musical tone). If this happens, the sampling frequency will become very large and it will be completely impractical. on the other hand,
Practical sampling frequency, e.g. 20
At around 50KHz, the fundamental frequency of a musical tone of any scale and the sampling frequency are in an anharmonic relationship, and the aliasing frequency due to sampling deviates from the frequency of the harmonic component of the musical tone, resulting in a turbulent sound. Also, it is not possible to use a waveform generation method that prepares one cycle of waveform sample values and reads them repeatedly. In order to obtain high-quality musical tones, it became necessary to increase the number of samples or perform interpolation calculations between sample values, which also had the disadvantage of requiring a large-scale waveform generator. Purpose of the Invention The present invention eliminates the above-mentioned drawbacks by making the speed of internal waveform generation and waveform calculation asynchronous with the fundamental frequency of musical tones, and reading out according to a readout frequency that is an integral multiple of the fundamental frequency of musical tones. This is what I did. Structure of the Invention The present invention writes the occurrence of a calculation request corresponding to a read frequency that occurs periodically in accordance with the read frequency into a calculation request flag register, and requests a calculation request to a waveform generator by referring to the calculation request flag register. generates a new waveform sample value when there is an occurrence of the waveform, writes it into the buffer memory via a writing device, and erases the record of the occurrence;
The readout device reads out the new waveform sample value from the buffer memory in which the new waveform sample value is written in accordance with the readout frequency, and
This device is characterized by being able to simultaneously output waveforms synchronized with each of the two readout frequencies. DESCRIPTION OF THE EMBODIMENTS FIG. 1 is a block diagram of an embodiment of the present invention.
1 is a notebook clock generator (NCG),
By dividing the master clock signal MCK, there are 12 note clocks C corresponding to 12 equal temperament scale tones,
Generate C#, D, ..., B. 2 is a timing pulse generator (TPG) that generates necessary pulse signals. 3 is the notebook clock selector (NCS)
In response to the note data specifying the scale note to be generated, the above 12 note clocks C and C
It has a function of selecting and outputting a note clock corresponding to specified note data from #, D, . . . B. In this embodiment, sound is produced even if up to eight keys on the keyboard are pressed at the same time. Since we are assuming a so-called 8-channel pronunciation, each note clock is selected for the 8 note data.
Eight note clocks NCK1 to NCK8 are output. Table 1 shows the relationship between the note names, the frequency division number of the master clock MCK in the note clock generator (NCG) 1, and the scale frequency.

[Table] The selected note clocks NCK1 to NCK8 are applied to the calculation request flag register 4, respectively.
The calculation request flag register 4 is composed of eight SR flip-flops FG1 to FG8. Note clock NCK1~8 are each SR flip-flop
It is applied to the set terminals S of FG1 to FG8. and,
Note clocks NCK1-8 are output. Then, each time the note clocks NCK1 to NCK8 are output, the SR flip-flops FG1 to FG8 are set, and their output is the calculation request flag 1.
~8 (CRF1~8) become "1". Calculation end signals CEN1-8, which will be described later, are applied to the reset terminals R of the SR flip-flops FG1-8, and each time the calculation end signals CEN1-8 become "1", the calculation request flags CRF1-8 are set to "0". Become. 5 is a readout device, which receives readout signals TRS1~
Generates 8. Read signal is calculation request flag
A pulse signal with a predetermined width starting from the rising edge of CRF1 to CRF8, which is a note clock NCK1.
Repeat at a frequency of ~8. The reading device 5 is composed of shift registers SR1 to SR8 which are shifted by a master clock MCK and an AND gate with an inverter on one side, and is provided corresponding to each of the eight channels. 6 is a calculation request detection controller, 7 is a waveform calculator,
These 6 and 7 constitute a waveform generator. The calculation request detection controller 6 is provided with eight CTLs 1 to 8 corresponding to each of the eight channels.
Channel 1 will be explained. The timing pulse generator TPG2 supplies a calculation start signal CST1, a calculation end signal CEN1, a sample end signal SEN1, and a calculation clock signal CCK to CTL1. A calculation request flag CRF1 is applied to one input terminal of the AND gates 20 and 21, and a calculation start signal CST1 and a calculation end signal CEN1 are applied to the other input terminals, respectively. The outputs of the AND gates 20 and 21 are the set terminal S of the SR flip-flop 22.
and reset terminal R, respectively. The output of the AND gate 21 is also applied to the set terminal S of the SR flip-flop 23 and the reset terminal R of the SR flip-flop FG1 in the calculation request flag register 4. A sample end signal is sent to the reset terminal R of the SR flip-flop 23.
SEN1 is applied. The output Q of the SR flip-flop 22 is applied to the AND gate 24 as the computation cycle signal CLC1, which outputs the computation clock signal CLC1.
It controls the application of CCK to the channel CH1 of the waveform calculator 7. The output Q of the SR flip-flop 23 is applied as a sample signal SMP1 to a gate _G1 of a writing device 8 and a switch _Q1 of a buffer memory 10, which will be described later. The waveform calculator 7 has 8 channels CH1 to CH8, and calculates sample values of a musical sound waveform having a predetermined scale and octave according to note data, octave data, and key-on/off data according to a calculation clock signal CCK. is calculated and output to gates _G1 to _G8 . With a given number of clocks,
Any method that calculates sample values of a new waveform may be used. The writing device 8 is a latch or gate G ₁ .
It consists of _G8 and DA converter 9. While the waveform calculator 7 completes the calculation and outputs a correct output, sample values are supplied to the next-stage DA converter 9 in correspondence with the sample signals SMP1 to SMP8. sample signal SMP
When 1 to 8 are "0", the output of each gate _G1 to _G8 becomes high impedance, so that it does not affect other gates. The output of the DA converter 9 is applied to a buffer memory 10. The buffer memory 10 is composed of writing transistor switches Q ₁ -Q ₈ , voltage holding capacitors C ₁ -C ₈ , and reading transistor switches Q ₁₁ -Q ₁₈ . Sample signals SMP1-8 are applied to the gates of write transistor switches _Q1 - _Q8 , respectively, and read signals TRS1-TRS8 are applied to read transistor switches _Q1 - _Q8 , respectively. When sample signal SMP1 becomes “1” and is applied to transistor switch _Q1 , transistor switch _Q1
When turned on, the output voltage V ₁ of the DA converter 9 is charged to the capacitor C ₁ via the transistor switch Q ₁ , and when the sample signal SMP 1 becomes “0” thereafter, the voltage V ₁ is held. Read signal TRS
When 1 becomes “1”, switch Q ₁₁ is turned on,
The charge on the capacitor C ₁ flows into an addition hold circuit consisting of an operational amplifier 11 and a capacitor _CF , and an output voltage −V ₁ C ₁ / _CF appears at the output terminal 12 and is held. FIG. 2 shows the operation timing of the main parts of the embodiment of FIG. In FIG. 2, calculation time slots 1 to 8 are prepared. Calculation start signal CST1 at the beginning of calculation time slot 1
occurs. At the end of calculation time slot 1, a calculation end signal CEN1 is generated. At the end of calculation time slot 2, an end-of-sample signal SEN1 is generated. These pulses correspond to calculation time slots 1-8.
It occurs repeatedly as a cycle. When note clock NCK1 corresponding to note data is generated for channel 1 at an unrelated period, FG1 of calculation request flag register 5 is set by NCK1 in FIG. 2, and calculation request flag
CRF1 becomes “1”. Calculation request flag CRF1
is delayed and gated by shift register SR1 by a time slightly smaller than the width of one calculation time slot to generate read signal TRS1. When calculation time slot 1 is reached and calculation start signal CST1 is generated while calculation request flag CRF1 remains "1", calculation start signal CST1 is output to gate 2.
0 and sets the SR flip-flop 22, so the calculation cycle signal CLC1 becomes "1". Calculation cycle signal CLC1 opens AND gate 24 and calculation clock signal CCK is added to channel CH1 of waveform calculator 7 to perform a new waveform sample calculation. The calculation is completed within the calculation time slot, and when the calculation end signal CEN1 arrives, the calculation request flag CRF1 is still applied to the AND gate 21 at this time, so
Calculation end signal CEN1 is sent to SR flip-flop 22
, set SR flip-flop 23,
Reset SR flip-flop FG1. Therefore, the calculation cycle signal CLC1 becomes "0",
Gate 24 closes and the supply of calculation clock signal CCK ends. The calculation request flag CRF1, which is the output of the SR flip-flop FG1, becomes "0", indicating that the execution of the calculation corresponding to the occurrence of the calculation request has been completed. SR flip-flop FG1 of calculation request flag register 4 is the next note clock NCK1.
Prepare for the arrival of Since the SR flip-flop 23 is set, the sample signal SMP1 becomes "1", the gate _G1 is opened, and the waveform sample which is the calculation result is supplied to the DA converter 9. Then, the transistor switch _Q1 is also turned on, and the output voltage _V1 of the DA converter 9 is applied to the capacitor _C1 . After the voltage on capacitor C ₁ has been sufficiently accurately charged to voltage V ₁ , an end-of-sample signal SEN 1 is generated and resets the SR flip-flop 23 .
Sample signal SMP1 becomes "0". When the sample signal SMP1 becomes "0", the gate _G1 is closed and the output becomes high impedance, and at the same time, the transistor switch _Q1 is also turned off, and the capacitor _C1 holds the voltage _V1 . Next, when the note clock signal NCK1 reaches the SR flip-flop G1, the readout signal TRS1 is sent via the readout circuit 5.
becomes "1", and the above voltage _V1 is transferred to the capacitor C _F through the transistor switch _Q11 . As described above, when the note clock signal NCK1 is generated, the previous waveform sample value is read out, the calculation request flag is set, and the channel CH
Wait until calculation time slot 1 is reached, and when calculation time slot 1 of channel CH1 is reached, waveform calculation for channel CH1 is executed, and in the next time slot 2, DA conversion of the calculation result and writing to buffer memory are performed. ing.
The frequency of note clock signal NCK1 supplied to channel CH1 varies depending on the note data.
In general, it exists in a range slightly less than twice that from C to B. Therefore, when the frequency of the notebook clock NCK1 is low, the calculation request flag CRF1 becomes "1".
Calculation time slot 1 may be reached even though the calculation time slot has not yet reached CLC.In this case, there is no need to calculate the waveform sample yet, so the calculation cycle signal
1 is kept at "0". Conversely, if the frequency of note clock NCK1 becomes too high, there is a possibility that calculation time slot 1 will not arrive in time. If the period is greater than 8+2 calculation time slots, there is no need to worry about this. Similar operations are performed for channels CH2 to CH8. Figure 3 shows calculation request flags CRF1-4, calculation cycle signals CLC1-4, DA conversion cycles (DAC1-4), and output cycles when note clock signals NCK1-4 of various cycles arrive at channels CH1-4. (OTC1-4) are shown. DA conversion cycles DAC1-4 correspond to sample signals SMP1-4. Output cycles OTC1-4 correspond to read signals TRS1-4. The thick rising edges of calculation request flags CRF1-CRF4 indicate generation of note clock signals NCK1-4. In calculation time slots 1-4, waveform calculations for channels CH1-4 are performed, respectively. Since a note clock signal with a large period is applied to channel CH2,
In calculation time slot 2, calculations are actually executed only slightly more than every other time. The dotted line indicates the calculation request flag.
Since CRF2 is 0, the calculation is in a suspended state.
Channel CH3 is an example where the period of note clock NCK3 is small, and note clock NCK3 occurs in the next DA conversion cycle of the next calculation time slot, so calculation execution is delayed by one time, but the output cycle operates normally. . Channel CH4 is an example in which calculation execution is delayed because note clock NCK4 occurs in the calculation time slot, but the output cycle operates normally. As described above, the internal calculation cycle and the external read cycle cannot be synchronized, and
Even in a system where there are multiple read cycles and read timings may match between multiple channels, by doing as in this example, writing and DA conversion can be internally synchronized. Moreover, reading can be performed independently for each channel. In the embodiment of FIG. 1, the waveform calculator 7 and the gate 8
are provided independently for each channel, but in the timing diagram shown in Figure 3, the calculation time slots are completely independent, and the writing is similarly independent, so each channel has one channel and TDM (time division multiplexing) operation is performed. You can let them do that. FIG. 4 also shows a calculation request detection control circuit 6.
This is another embodiment of the present invention in which TDM operation is performed. FIG. 5 shows the timing and signal waveforms of each part in FIG. 4. In FIG. 4, parts having the same functions as those in the embodiment of FIG. 1 are designated by the same numbers and their explanations will be omitted. The timing pulse generator TPG2 generates a calculation clock signal CCK, a calculation start signal CST, and a calculation end signal CEN, as shown in FIG.
{TS} specifies calculation time slots 1 to 83
This is a signal consisting of bit codes A, B, and C. These signal groups are supplied to the calculation request detection control circuit 6. The calculation request detection control circuit 6 includes AND gates 20, 21, 24, an SR flip-flop 22,
It is composed of a shift register 25, a multiplexer 27, and demultiplexers 26 and 28. 7
is a TDM waveform calculator, 8 is a latch, and 9 is a TDM waveform calculator.
It is a DA converter. The rest is the same as the embodiment shown in FIG. In FIG. 5, master clock MCK is frequency-divided once to become calculation clock signal CCK. Ten calculation clock signals CCK form one calculation time slot. Each calculation time slot is {TS}
will be instructed. {A, B, C}={1, 1, 1) represents the calculation time slot. The first calculation clock signal CCK of each time slot is the calculation start signal.
CST and the last calculation clock signal CCK become the calculation end signal CEN. Similar to the embodiment in Figure 1, the calculation request flag CRF
1 to 8 are set in the calculation request flag register 4. These calculation request flags CRF1 to CRF8 are sequentially scanned by the multiplexer 27. When {TS}=(111), calculation request flag CRF1 is selected and applied to AND gates 20 and 21. Calculation request flag
If CRF1="1", the SR flip-flop 22 is set, the calculation cycle signal CLC becomes "1", and the calculation clock signal CCK is supplied to the waveform calculator 7. Since {TS} is supplied to the waveform calculator, waveform calculations corresponding to note data and octave data to be performed in calculation time slot 1 can be executed. The calculation is completed with the last of the 10 calculation clock signals CCK, and the calculation result is latched into latch 8 at the falling edge of that clock signal. The reset signal RESET output from the AND gate 21 is used as the latch clock. The reset signal RESET resets the SR flip-flop 22 and sets the calculation cycle signal CLC to "0". At this time, the demultiplexer 26 has
Since {TS}=(111) is input, the reset signal RESET is sent to channel CH1 of calculation request flag register 4, that is, SR flip-flop FG.
The calculation request flag is applied to the reset terminal R of 1.
Set CRF1 to “0”. SR flipflop 2
The calculation cycle signal CLC, which is the output of 2, has a pulse width equivalent to 9 calculation clock signals CCK, but this signal is delayed by 20 master clock signals MCK, that is, 1 calculation time slot, in the shift register 25. and is applied to the demultiplexer 28 as a sample signal SMP. When the sample signal SMP is output, {TS}=(011). For this {011}, the channel
A sample signal is sent to transistor switch _Q1 so that the buffer memory corresponding to CH1 is selected.
Since SMP is derived, the calculation result of latch 8 is DA
It is stored and held in the buffer memory of channel CH1 via converter 9. When {TS}=(011) and becomes channel CH2, if calculation request flag CRF2 is "1", the same operation as channel CH1 is performed.
{TS} = (101), that is, the calculation request flag when the calculation time slot 3 of channel CH3 is reached.
If CRF3 is "0", SR flip-flop 22 is not set. Therefore, the calculation cycle signal CLC remains “0” and the channel CH
Waveform calculation in step 3 is not performed. sample signal
Since SMP is also “0”, no sample is performed,
Buffer memory channel CH3 holds the previous calculation results as they are. Meanwhile, each channel has a note clock signal.
When NCK1-8 occurs, as in the case of Figure 1,
The read signals TRS1 to TRS8 are generated, and the capacitors C1 _{to C1} corresponding to each channel of the buffer memory 10
Read the holding voltages _V1 to _V8 of _C8 . In Fig. 1, note data, octave data, and aon-off data are data based on the determination of which channel of channels CH1 to CH8 is assigned the pitch and octave of the pressed key by a so-called generator assigner. It is supplied as. The generator assigner is a well-known technology, and its configuration is not directly related to the essence of the present invention, so a description thereof will be omitted. Although the waveform calculator 7 calculates a new sample value every 10 clocks in FIG. 4, this is not limited to 10 clocks. For example, if the sample value to be read is written in memory in advance, all you need to do is read the address following the previous memory address, so there is no need for 10 clocks, and the time for incrementing the address and reading the memory is sufficient. It is sufficient. The waveform calculator 7 may be one that calculates analog sample values instead of digital samples. In this case, an analog computer such as a voltage-controlled music synthesizer may be utilized. In the buffer memory 10 of FIGS. 1 and 4, the outputs of the channels 1 to 8 are added together, but the charges of the capacitors C ₁ to C ₈ of each channel may be read out independently. FIG. 6 is an example. In FIG. 6, the output of the buffer memory 10 is as follows for each transistor switch _Q11 to _Q18 .
It is output independently. 31 to 38 are analog multipliers. Reference numeral 13 denotes an envelope signal generator that receives key on/off data corresponding to key presses and key releases of each channel and generates an envelope signal of a musical tone, a so-called envelope signal. In this embodiment, since the envelope is applied at the output stage of the buffer memory 10, the waveform calculator 7
Unlike the illustrated embodiment, no envelope calculation is required. Therefore, it is no longer necessary to add key on/off data to the waveform calculator 7. FIG. 7 shows another example of the waveform calculator 7. 7th
In the figure, 50 is an address register that stores wave address data WAD of a read-only memory (ROM) 53 in which musical waveforms are stored;
Each word consists of 8 bits and is provided corresponding to 8 channels. 51 is an adder that adds 1 to the address; 52 is a shifter that bit-shifts the added address data into octave data; 53 is a read-only memory ROM consisting of 256 addresses (8 bits per word); It stores the minutes. The address register 50 contains the calculation time slot code {TS}
and read/write signal R/W are applied,
The wave address data WAD stored in the register specified by {TS} is read out with R/W="1", is incremented by 1 by the adder 51, and is read out as R/W.
= “0” and is written to the same register again. Therefore, address data WAD advances by +1. In the calculation time slot, if the calculation cycle signal CLC = “0”, there is no need for calculation.
The +1 data is blocked by the AND gate 60, and the wave address data WAD remains as it was. The wave address data WAD is shifted by shift 52 in accordance with the height of the octave. When shifted one bit higher, the increment is doubled for the address of the read-only memory ROM 53, so the ROM address advances faster and the fundamental frequency of the generated waveform is doubled.
Waveform sample data WD, which is the output of the read-only memory ROM 53, is applied to the data input terminal of the multiplication DA converter 58. Reference numeral 54 denotes a register for storing envelope address data EAD for eight channels, and any register can be read or written using the calculation time slot code {TS} and the read/write signal R/W. 56 is a step data generator that holds different step data for each note data, and for each calculation time slot,
Outputs the step number corresponding to that note. 55 is the selected step number and envelope address data
This is an adder that adds EAD. The output of adder 55 is supplied to register 54 and ROM 57.
A memory 57 stores waveform data from the rise to the fall of the musical tone envelope. When the key is pressed, the key-on data becomes "1" and the envelope address data which is the contents of the register of a predetermined channel among the registers 54
EAD is initialized to 0. Then, among the 12 step numbers, the step number ΔEAD corresponding to the pressed note is set to envelope address data EAD=0.
is added and stored in the original register again, and the envelope data ED at the address of EAD+ΔEAD is read from the read-only memory ROM 57. If so, the calculation cycle signal
If CLC is “0”, envelope address data
EAD does not advance. In this way, when a key is pressed, the envelope data ED from the rise to the fall of the sound is read out, and the DA converter 59 reads out the envelope data ED from the rise to the fall of the sound.
An analog voltage envelope signal V _ENV is obtained. The above operation is performed in units of calculation time slots.
Since it is TDM, the envelope signal V _ENV
It is also converted into TDM and output. envelope signal
V _ENV serves as a reference voltage for the multiplication DA converter 58. The multiplication DA converter 58 has a reference voltage V _ref =V _ENV ,
It has the function of outputting the result of multiplication with the waveform data input WD as an output voltage. Therefore, the output of the multiplication DA converter 58 is stored in the read-only memory ROM 53.
The sound source waveform sample stored in the ROM 57 is multiplied by the envelope waveform sample stored in the read-only memory ROM 57 in a semi-digital manner, and the timing is synchronized with the internal calculation time slots 1 to 8. is output. Therefore, by applying the signal to the buffer memory 10 similar to that shown in FIG. 4, it can be read out as a sound source sample value with an envelope at the desired note clock occurrence timing. The embodiment of FIG. 7 is characterized by the DA converters 58 and 5.
By using two of 9, envelope multiplication can be performed without using digital multiplication. By adding a multiplication DA converter between DA converters 58 and 59 or to the output of DA converter 58, and inputting data corresponding to the overall amplitude to its digital input, the musical tone signal of each channel can be adjusted. It is also possible to set the level independently. Regarding the relationship between the key-on-off data and the envelope curve, the above embodiment describes a simple case. It may also have a function such as a damper that rapidly attenuates the envelope after key-off. Next, the buffer memory 10 will be explained. The output of the buffer memory 10 in FIG. 1 is provided with an operational amplifier 11 and a feedback capacitor C _F to add the outputs of each channel of the buffer memory 10.
1 and the capacitor C _F have not only an additive effect but also an integral effect. In other words, the operational amplifier 11 and the capacitor C _F are a hold circuit, and this hold circuit accepts the charge independently held by each of the capacitors C ₁ to C ₈ via the transistor switches Q ₁₁ to _{Q 18} at a predetermined timing. . After accepting the charge, if we ignore the leakage current, C _F /
The voltage corresponding to C ₁ , C _F /C ₂ , ..., C/C ₈ is maintained. In this way, the voltage across the terminals of capacitor C _F is maintained as it is. It can also be called a hold action instead of an integral. In other words, the previous sample voltage that was read is held as is. Therefore, the write voltage to the buffer memory 10 in FIG. 1 needs to be a waveform difference value. To obtain the waveform difference value,
The difference between the previous value WD (nT - T) and the current value WD (nT) of the waveform sample data output by the waveform calculator 7, WD (nT) - WD (nT - T), should be calculated and output. . This is because when the square wave is waveform sampled in the differential format as shown in FIG. 13a, the operational amplifier 11
The outputs of are accumulated or integrated to form a waveform as shown in FIG. 13b. Therefore, if you try to obtain a certain desired waveform at the terminal 12, the DA converter 9
The waveform to be output must be in differential format (or differential) data. These operations can be performed digitally. Buffer memory 10 and operational amplifier 1 in Figure 4
1. When using the capacitor C _F , it is also necessary to write differential sample data to the latch 8. Also in FIG. 6, when a hold circuit is provided at the output of the read transistor switches _Q11 to _Q18 , it is necessary to write differential sample data to the latch 8. In FIG. 7, since a hold circuit is provided at the output of the buffer memory 10, the buffer memory 10
The input voltage to 0 must be a differential sample value. 60 is a difference sample value calculator. 8th
The figure is a diagram of this part, FIG. 9 is an example of the differential sample value calculator, and FIG. 10 is its timing diagram.
In FIG. 8, the multiplication DA converter 58 and the DA converter 59 each contain waveform sample data WD.
(nT-T), WD (nT) and envelope data ED
(nT−T) and ED(nT) are supplied. The previous data WD (nT-T) and ED (nT-T) are supplied at φ _A in Fig. 10, and the waveform sample data WD (nT) and envelope data ED are supplied at φ _B.
(nT), that is, the current data is supplied. In FIG. 9, switch Q ₁₀₀ , capacitor C _A ,
The operational amplifier 70 outputs the previous data WD (nT−
Voltage V(nT-T) corresponding to T) x ED(nT-T)
This is a sample and hold circuit that holds . Voltage V corresponding to the current data WD (nT) × ED (nT)
(nT) is applied to one end of capacitor C _B at φ _B when switch Q ₁₀₁ is turned on, but at this time, the previous V (nT - T) is applied to the other end when switch Q ₁₀₂ is turned on. be done. Therefore, the voltage between the terminals of capacitor C _B is ΔV (nT) = V (nT) - V (nT - T). Since the switch Q ₁₀₃ is turned on at φ _C , ΔV(nT) is outputted via the buffer amplifier 80 and supplied to the buffer memory 10. As described above, the difference sample value calculator 60 generates the difference voltage between the musical tone sample data, which is the product of the waveform sample data and the envelope data. FIG. 11 shows another embodiment of the buffer memory 10. In FIG. 11A, Q ₁ , Q ₁₁ , and Q ₂₁ are transistor switches, C ₁ is a capacitor, R ₁ is a summing resistor, and the operational amplifier 11 and resistor _RF constitute a summing amplifier. R ₂ is a summing resistor for channel 2. FIG. 11B shows the waveform of the signal at each point in FIG. 11A. The input terminal 110 has
The output of the DA converter is input in the form of current I _1N . Transistor Q ₁ is turned on for T _S1 by signal S ₁ and charges capacitor C ₁ . At the leading edge of T _S1 the signal S ₂ turns on transistor Q ₂₁ and capacitor C ₁
has been discharged, so V _CAP =I _1N ·T _S1 /C is charged and held during time T _S1 . Transistor Q ₁₁
When TRS ₁ comes, a voltage is generated in the resistor _RF according to the discharge current of the capacitor C ₁ to the resistor R ₁ , and a voltage waveform corresponding to the discharge current is read out at the terminal 12 . T _S1 is set to have a time width inversely proportional to the note frequency of channel 1. note frequency
If _NOTE is high, the frequency of sample occurrence is high,
The energy of each sample, i.e. the capacitance
If the amount of charge on C ₁ is the same with respect to the note frequency, then
The level of the output waveform increases in proportion to the note frequency _NOTE . In this case, according to the chromatic scale within one octave, the volume increases by 2 ^1/12 = 0.5 dB as the note gets higher, which is inconvenient. Therefore, in Figure 11, since the V _CAP holding voltage is controlled in inverse proportion to the note frequency _NOTE ,
The difference in level can be kept almost constant for any scale. To make T _S1 inversely proportional to note frequency _NOTE ,
You can create 12 different pulse widths using a monostable multivibrator and select from these, or you can create _S1 signals with different pulse widths using a counter. FIG. 12 shows another embodiment of the buffer memory 10, and FIG. 12A shows an example of its circuit, the first
Figure 2B shows the waveform. Compared to FIG. 11, there is no transistor switch Q ₂₁ and the pulses applied to transistor switches Q ₁ and Q ₁₁ are different. A voltage of a waveform sample value is applied to the input terminal 110 . The capacitor _C1 is charged by the sample signal SMP1. Transistor switch _Q11 receives a pulse width T _M1 at the same timing as the TRS1 signal.
A signal MTRS1 is applied. When the transistor switch _Q11 is turned on, the discharge current I _R1 of the capacitor _C1 flows into _{the resistor R F via} the resistor R1. The pulse width T _M1 is set to be approximately inversely proportional to the note frequency _NOTE . In this way, the higher the note frequency _NOTE , the shorter the time for the current I _R1 to flow, and the smaller the energy. On the other hand, the 11th
As explained in the figure, since the output frequency is proportional to the note frequency, the two cancel each other out, and the output level becomes approximately constant regardless of the note. In the embodiments of FIGS. 11 and 12, the output summing amplifier does not have a hold function, so the input need not be a differential sample value. In the explanation of FIGS. 1 and 4 above, the occurrence of calculation requests is recorded in parallel and calculations are performed in pre-ordered calculation time slots. Another example may be as follows. That is, when a calculation request occurs, its channel number is recorded in eight registers in the order of occurrence. The eight registers can be FIFO (first-in-first-out) memory. Although computational requests may occur simultaneously on several channels,
In this case, priority will be given in order of channel number. For this purpose, a circuit similar to a daisy chain type interrupt control circuit can be used as a peripheral IC such as a microcomputer. The waveform generator is
Read the FIFO memory, know the channel number to be calculated, and write the note corresponding to that channel.
Calculate the waveform sample value of the octave and write the calculation result to the corresponding channel of the buffer memory via the write need. When the writing is completed, the FIFO memory is read again and the next waveform calculation is executed. On the other hand, the calculation results are read out when recording the occurrence of a calculation request in the FIFO memory. In this embodiment, if there is a calculation request channel number in the FIFO memory, the waveform calculation for any channel is continuously performed, but when there is no record of calculation requests in the FIFO memory, the waveform calculation is stopped. Additionally, the order of waveform calculations is the order of request occurrence. In the above explanation, the note clock in FIGS. 1 and 4 was selected based on note data. Therefore, regarding octaves, waveforms that differ by an octave are created by doubling or halving the number of samples within the fundamental period of the waveform. However, the present invention is not limited to this, and by dividing the frequency of the note clock, a readout signal that also includes octave information can be created. Also, C, C#, D, D can be used as a notebook clock.
#, E, F only, F#, G, G#, A, A
For # and B, a total of 12 chromatic scales can be created by changing the number of samples. In short, the method is not limited to a completely separate method in which note selector 3 performs octave control and waveform calculator 7 performs octave control. Effects of the Invention As explained above, the waveform readout device of the present invention writes the occurrence of a calculation request corresponding to the readout frequency that occurs periodically according to the readout frequency into the calculation request flag register, Generates a new waveform sample value when a calculation request occurs by referring to the calculation request flag register, writes it to the buffer memory via the writing device, erases the record of the occurrence, and generates a new waveform sample value according to the read frequency. , from the buffer memory where the above new waveform sample values are written,
said readout device reads said new waveform sample value, said at least two different waveform sample values are read out;
This makes it possible to simultaneously output waveforms synchronized with each of the two readout frequencies. Therefore, even if the note clock frequency is set independently of the master clock frequency, normal operation can be achieved because the internal calculation and readout can be asynchronous. Therefore, it is possible to independently apply vibrato, glide, portamento, etc. to each note clock frequency. In addition, not only is it sufficient to use only one DA converter in the writing device, but they also operate independently for each channel, so even if two channels of sound are played simultaneously, there is no cross-modulation distortion due to quantization distortion. No outbreak. Therefore, an inexpensive DA converter of about 8 bits can be used. Furthermore, since the sampling frequency can be made an integral multiple of the fundamental frequency of the waveform, all aliasing components generated and harmonic components of the sample waveform caused by quantization can be removed, and all harmonic components of the fundamental frequency can be removed. It is possible to match the harmonics of the fundamental frequency, thus creating a clear sound.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
3 is a timing diagram showing the concept of its operation, FIG. 4 is a block diagram of the second embodiment of the present invention, FIG. 5 is an operation timing diagram thereof, and FIG. 6 is a timing diagram of the present invention. FIG. 7 is a block diagram of an embodiment of the buffer memory section used in the present invention, and FIG. 7 is a block diagram of an embodiment of the waveform calculator, writing device, and buffer memory section used in the present invention. FIGS. Block diagram of the embodiment, No. 10
The figures are the timing diagram of Fig. 8, Fig. 9, Fig. 11,
FIG. 12 is a block diagram of an embodiment of the buffer memory and its operation timing diagram, and FIG. 13 is a waveform diagram for explaining the operation. 1... Note clock generator, 2... Timing generator, 3... Note clock selector, 4... Calculation request flag register, 5...
Reading device, 6... Calculation request detection controller, 7...
...Waveform calculator, 8...Gate or latch, 9...
...DA converter, 10...buffer memory.

Claims (1)

[Claims] 1. A waveform generator that generates a plurality of waveforms, a plurality of read frequency generators that generate at least two different read frequencies, a device that controls a waveform request, a writing device, and a capacitor. a plurality of buffer memories and a plurality of readout devices, and generates a new waveform sample value by notifying the waveform generator of the occurrence of a waveform request corresponding to the readout frequency that occurs periodically in accordance with the readout frequency. the new waveform sample value is written in the buffer memory via the writing device, and the readout device reads out the new waveform sample value from the buffer memory to which the new waveform sample value has been written according to the readout frequency. It is possible to simultaneously output waveforms synchronized with each of at least two different readout frequencies, and further, the writing device converts the waveform sample value into an analog signal using a digital-to-analog converter, and the buffer memory stores the analog signal. . A waveform readout device, wherein the digital-to-analog converter performs multiple time-division operations corresponding to the at least two readout frequencies. 2. The waveform reading device according to claim 1, wherein the waveform generator operates by time division multiplexing and sequentially generates waveforms of designated channels in calculation time slots provided for each channel in advance. 3. The analog signal output by the writing device is a difference between musical tone sample values, the difference is written into a buffer memory, and the difference read from the buffer memory is accumulated by a hold circuit. The waveform readout device according to scope 1. 4. The waveform generator includes a sound source waveform generator and an envelope generator, and the writing device includes a DA converter and a multiplication DA converter, and writes one of the sound source waveform and envelope data output from the waveform generator to the above.
DA converter, add the other to the above multiplication DA converter,
2. The waveform reading device according to claim 1, wherein the output of the DA converter is added to the multiplication DA converter and multiplied, and the output is written into a buffer memory. 5. The waveform reading device according to claim 4, wherein the output of the multiplication DA converter is subjected to a differential calculation and written to the buffer memory.