JPH0364068A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and in particular to a dynamic random access memory device equipped with a charge storage section (stacked capacitor cell) having a stacked structure. -Relates to memory (hereinafter referred to as DRAM) and its manufacturing method.

[Prior Art] DRAM is already well known. FIG. 6 is a block diagram showing an example of the overall configuration of such a conventional DRAM.

Referring to FIG. 6, a DRAM includes a memory cell array 1000 including a plurality of memory cells as a storage part, a row decoder 2000 and a column decoder 3000 connected to an address buffer that selects the address, and an input/output circuit. and an input/output interface section including a connected sense amplifier. A plurality of memory cells serving as a storage portion are arranged in a matrix consisting of a plurality of rows and a plurality of columns. Each memory cell is connected to a corresponding word line connected to row decoder 2000 and a corresponding bit line connected to column decoder 3000, thereby
00. A memory cell is selected by one word line and one bit line selected by row decoder 2000 and column decoder 3000 in response to externally applied row address signals and column address signals. Data is written into the selected memory cell, or data stored in the selected memory cell is read out.

This data read/write instruction is performed by a read/write control 21+ signal applied to the control circuit.

Data is N (-nXm) bit memory cell array 10
It is stored in 00. Address information regarding the memory cell to be read/written is stored in the row and column address buffer 7, and the row decoder 2000 selects a specific word line (one word line out of n word lines). m-bit memory cells are coupled to the sense amplifier via bit lines. Next, column decoder 300
By selecting a specific bit line (selecting one bit line out of m bit lines) by 0, one of the sense amplifiers is coupled to the input/output circuit, and reads out according to a command from the control circuit. Alternatively, writing is performed.

FIG. 7 is an equivalent circuit diagram of one memory cell 100 of a DRAM shown for explaining write/read operations of the memory cell. According to this figure, one memory cell 100 consists of a pair of field effect transistor Q and capacitor Cs. The gate electrode of field effect transistor Q is connected to word line 200, one source/drain electrode is connected to one electrode of capacitor Cs, and the other source/drain electrode is connected to one electrode of capacitor Cs.
The drain electrode is connected to the bit line 300.

When writing data, a predetermined voltage is applied to the word line 200 to turn on the field effect transistor Q, so that the charge applied to the bit line 300 is stored in the capacitor Cs. On the other hand, when reading data, a predetermined voltage is applied to the word line 200 to turn on the field effect transistor Q, so that the charge stored in the capacitor Cs is taken out via the bit line 300.

FIG. 8 shows, for example, an IEDM (International
nal electron devices m
88-pp, 596-599 is a partial cross-sectional view of a DRAM memory cell having a conventional bit line embedded stacked capacitor cell; Here, the bit line buried type refers to a type in which a pit line is formed in the lower layer of the electric storage section. FIG. 9 is a plan view thereof. FIG. 8 shows a cross section taken along the line ■-■ in FIG. 9. In the figure, on the silicon substrate 1,
A gate electrode 3 which also serves as a word line is provided through a gate oxide film 2.
are formed at intervals. On the silicon substrate 1,
One impurity region 52 and the other impurity region 52 separated by the gate electrode 3 are formed as source/drain regions. A bit line 82 is formed to be connected to one impurity region 52. Bit line 82 is word line 3
It is formed perpendicular to. An insulating film 4 is formed between the word line 3 and the bit line 82.

A storage node 112 is formed on the bit 1182 with an insulating film 14 interposed therebetween. storage node 1
12 is formed so as to be in electrical contact with the other impurity region 52. Cell plate 132 is formed to face storage node 112 with capacitor dielectric film 122 in between. In this way, since the bit l182 is formed in the lower layer of the storage node 112 and the cell plate 132 as a charge storage section, the active region 182 is arranged diagonally with respect to the bit line 82 and the word line 3. .

On the other hand, the cross-sectional structure of a memory cell in which the bit line is located above the charge storage section is shown in FIG. Referring to FIG. 10, one impurity region 53 has an underlying pad 93.
A bit line 83 is connected thereto. A storage node 113 is connected to the other impurity region 53 via an underlying pad 93. A cell plate 133 is formed on the storage node 113 with a capacitor dielectric film 123 interposed therebetween. In order to form the bit line 83 in the upper layer of the charge storage section consisting of the storage node 113 and the cell plate 133 in this manner, it is necessary to form a thick interlayer insulating film 103 between them. Therefore, a margin M is required between the cell plate 133 and the side wall portion of the contact hole for connecting the bit line 83 to the impurity region 53.

However, in the structure shown in FIG. 8, storage node 112 and cell plate 132 can be formed so as to extend over the contact portion where bit line 82 is connected to impurity region 52. Therefore, it becomes possible to expand the planar area of the charge storage section.

Therefore, it becomes possible to increase the capacitance of the capacitor.

Furthermore, FIG. 11 shows, for example, IEDM88-1)p
, 246-249 is a partial cross-sectional view of a DRAM memory cell having a conventional stacked capacitor cell shown in FIG. FIG. 12 is a plan view thereof. Figure 11 shows
A cross section taken along the line XI-XI in FIG. 12 is shown. In the figure, a tungsten plug 84 is inserted through an underlay pad 94b so as to be electrically connected to one impurity region 54.
a is formed. A tungsten bit line 84 is formed so as to contact this tungsten plug 84a. The storage node 114 is electrically connected to the other impurity region 54 via the underlying pad 94a.
is formed. This storage node 114 is formed along the inner surface of a recess selectively formed in the thick flat interlayer insulating film 104 and the flat upper surface of the interlayer insulating film 104. Cell plate 134 is formed on storage node 114 with capacitor dielectric film 144 interposed therebetween. Although not shown in FIG. 12, the bit line 84 is connected to the XI-
It is formed along the XI line and electrically connected to impurity region 54 via contact 164. Storage node 114 is connected to impurity region 54 via contact 154. In this way, since the contact 154 of the storage node 114 exists in the direction in which the bit line 84 extends, the active region 184 is arranged perpendicular to the word 13. Further, in this structure, a field shield 74 is employed as the isolation region.

According to the structure of the memory cell shown in FIG.
Since it is formed along the inner surface of the recess formed in the flat interlayer insulating film and the upper surface of the interlayer insulating film, the surface area of the charge storage portion can be expanded in the vertical direction. Therefore, it is possible to increase the capacitance of the capacitor within a limited occupied area. Furthermore, since the storage node constituting the charge storage section is formed by patterning on a flat interlayer insulating film, its processing can be easily performed.

[Problems to be Solved by the Invention] However, according to the conventional bit line buried stacked capacitor cell shown in FIG. 8, the surface area of the storage node forming the charge storage section is expanded in the lateral direction. , this is the limit to the expansion of surface area in the lateral direction. Therefore, it is difficult to cope with the significant reduction in the area occupied by the charge storage section as semiconductor elements become further miniaturized and highly integrated.

On the other hand, according to the conventional stacked capacitor cell shown in FIG. 11, a margin is required between the edge of the cell plate and the edge of the contact portion of the bit line.

Furthermore, when a storage node, which is a charge storage section, is formed to extend in the vertical direction as semiconductor devices become smaller, the depth of a contact hole for connecting a bit line to an impurity region becomes deeper. Therefore, it is difficult to form the contact hole with high precision. Furthermore, there is a problem in that it is difficult to selectively form a tungsten film in the contact hole.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor memory device having a stacked capacitor cell that can obtain a large capacity with a small occupied area, and a method for manufacturing the same. It is to be.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a semiconductor substrate, one impurity region and the other impurity region, a gate electrode, a wiring layer, a storage node, and a cell plate. The semiconductor substrate has a main surface and is of a first conductivity type. The impurity region is
They are formed on a semiconductor substrate and spaced apart from each other so as to define a channel region. The gate electrode is formed on the channel region with an insulating film interposed therebetween. The wiring layer is insulated and formed above the gate electrode so as to be in electrical contact with one of the impurity regions. The storage node is in electrical contact with at least the other impurity region, is formed to have a sidewall portion extending substantially perpendicular to the main surface of the semiconductor substrate, and is located above the wiring layer. The cell plate is formed on the storage node via a dielectric film.

A method for manufacturing a semiconductor memory device according to the present invention includes the following steps.

(a) A step of forming gate electrodes at intervals on the main surface of a first conductivity type semiconductor substrate with an insulating film interposed therebetween.

(b) A step of forming one impurity region and the other impurity region separated by the gate electrode.

(C) A step of forming an insulated wiring layer above the gate electrode so as to be in electrical contact with one impurity region.

(d) Forming on the wiring layer an insulating layer having a recessed portion consisting of a bottom surface exposing the surface of at least the other impurity region and side surfaces extending substantially perpendicular to the main surface of the semiconductor substrate.

(e) forming a storage node so as to electrically contact at least the bottom surface of the recess and extend along the side surfaces;

(f) A step of forming a cell plate on the storage node via a dielectric film.

[Function] In the present invention, the storage node, which is a charge storage section, is formed so as to extend approximately perpendicularly to the main surface of the semiconductor substrate at a side wall portion, and is in electrical contact with the other impurity region. There is. Further, the wiring layer is formed so as to be in electrical contact with one of the impurity regions. A storage node exists above the wiring layer. Therefore, the surface area of the storage node is expanded by the surface area of the sidewall portion, so that the capacitance of the capacitor can be increased. Further, since the wiring layer that electrically contacts one of the impurity regions is formed below the storage node, it is not necessary to form a deep contact hole for contacting the bit line and the substrate. Furthermore, since the storage node extends sufficiently in the lateral direction without being affected by the contact region of the bit line, the capacitance of the capacitor can be increased in a plan view as well. Therefore, a charge storage section having a stacked structure that can obtain a large capacitance with a smaller occupied area can be formed.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a partial cross-sectional view conceptually showing the structure of a DRAM memory cell having a stacked capacitor cell according to the present invention, and FIG. 1(b) is a partial plan view corresponding to the cross-sectional view. It is a diagram. Note that Fig. 1(a) is similar to Fig. 1(a).
A cross section taken along line 1-1 of b) is shown. Moreover, FIG. 2 is a plan view showing the partial plan view shown in FIG. 1(b) in a different direction.

An embodiment of the structure of a memory cell according to the present invention will be described with reference to these figures.

On a p-type silicon substrate 1, a gate electrode 3 which also serves as a word line is formed of polycrystalline silicon with a gate oxide film 2 interposed therebetween. The word lines 3 are formed so as to extend in a fixed direction at a predetermined distance from each other. The n-type impurity region that should become the source or drain region is
L consisting of a low concentration impurity region 5 and a high concentration impurity region 6
It has a DD structure. A bit line 8 made of polycrystalline silicon is formed to be electrically connected to one of the impurity regions. Bit line 8 is formed perpendicular to word line 3 . A storage node 11 is formed in the other impurity region so as to be electrically connected via an underlying pad 9 made of polycrystalline silicon. This storage node 11 has a storage node hole 11 formed in the interlayer insulating film 10 formed above the bit Ij18.
It is formed along the inner surface of a. A cell plate 13 is formed on the storage node 11 with a capacitor dielectric film 12 interposed therebetween.

Bit line 8 is formed to be in electrical contact with the impurity region at bit line contact 16 . Storage node 11 is formed to be in electrical contact with the impurity region via underlying pad 9 at storage node contact 15 portion. Since electrical contact with the silicon substrate 1 is thus formed, the active region 18 is connected to the bit line 8 and the word line 3, as shown in FIG. 1(b) and tJ2. They are provided so as to intersect diagonally.

Next, a method for forming a specific structure of the above memory cell will be described. FIGS. 3A to 3M are partial cross-sectional views sequentially showing a method for manufacturing a memory cell having a stacked capacitor cell according to an embodiment of the present invention.

First, referring to FIG. 3A, isolation regions 7 made of a silicon oxide film are formed at intervals so as to surround an element formation region on p-type silicon substrate 1. As shown in FIG.

Thereafter, thermal oxidation treatment is performed on the entire surface to form a thermal oxide film having a thickness of about several hundred amps. A polycrystalline silicon film 31 and a silicon oxide film 41 are formed on the thermal oxide film 21 using a chemical vapor deposition method (CVD method).
formed by.

A resist film 17a is formed on the silicon oxide film 41 according to a predetermined pattern.

As shown in FIG. 3B, using resist film 17a as a mask, silicon oxide film 41 and polycrystalline silicon film 31 are selectively removed using anisotropic etching such as reactive ion etching. In this way, the gate electrode 3 and the silicon oxide film 41 are placed at desired portions within the active region.
a is formed. Using gate electrode 3 and isolation region 7 as a mask, arsenic or phosphorus at a low concentration of about 1012 to 10''' cm-2 is implanted into silicon substrate 1.

Referring to FIG. 3C, silicon oxide film 42 is formed over the entire surface of silicon substrate 1. Referring to FIG.

Furthermore, as shown in FIG. 3D, by selectively etching using anisotropic etching,
A sidewall 4 made of a silicon oxide film is formed only on the sidewall portion of the gate electrode 3. This side wall 4
Highly concentrated phosphorus or arsenic is implanted into the silicon substrate 1 using the isolation region 7 as a mask.

Referring to FIG. 3E, phosphorus or arsenic implanted into silicon substrate 1 is thermally diffused by performing in-furnace annealing treatment at a temperature of 850 to 900°C or rapid annealing treatment by lamp annealing at a temperature of 1000°C or higher. As a result, an LDD structure is formed consisting of a lightly doped n-type impurity region 5 of about 1016 to 10"cm-"a and a high-concentration impurity region 6 of about 1019 to 1021 cm-' to serve as a source or drain region. Ru.

As shown in FIG. 3F, an insulating film 140 made of a silicon oxide film is first formed on the impurity region 5.6 to which no bit line is connected. - Thereafter, a polycrystalline silicon film 81 whose resistance has been lowered by implanting arsenic or phosphorus, and a silicon oxide film 141 are formed on the entire surface of the silicon substrate 1 using the CVD method. silicon oxide film 1
41, a resist film 1 is formed according to a predetermined pattern.
7b is formed.

Referring to FIG. 3G, silicon oxide film 141 and polycrystalline silicon film 81 are selectively removed by anisotropic etching using resist film 17b as a mask. In this way, bit line 8 is formed so as to connect only to one impurity region 5.6.

Thereafter, as shown in FIG. 3H, a silicon oxide film 142 is again formed on the entire surface of the silicon substrate 1 using the CVD method.

As shown in FIG. 31, by performing the anisotropic etching process, a silicon oxide film is selectively left only on the side walls of the bit line 8, and a side wall 14 is formed.

At the same time, impurity region 5 connected to the capacitor section
, 6 are exposed.

As shown in FIG. 31, a polycrystalline silicon film 91 is formed over the entire surface of silicon substrate 1 using the CVD method. A resist film 17c is formed on this polycrystalline silicon film 91 according to a predetermined pattern. This resist film 1
By performing an anisotropic etching process using 7c as a mask, an underlying pad 9 made of polycrystalline silicon is formed.

Thirdly, as shown in the figure, a silicon oxide film 101 having a thick and flat surface is deposited on the entire surface of the silicon substrate 1.
It is formed using the D method. Thereafter, a resist film 17d is formed on this silicon oxide film 101 according to a predetermined pattern.
is formed. Using this resist film 17d as a mask, an anisotropic etching process is performed to form a contact hole so as to expose the surface of the underlay pad 9.

As shown in FIG. 3L, a polycrystalline silicon film 111 is formed over the entire surface along the inner surface of the contact hole and the upper surface of the interlayer insulation 1filO. This polycrystalline silicon film 11
On top of 1 is a resist @ 17 according to a predetermined pattern.
e is formed. Storage node 11 is formed by performing an anisotropic etching process using resist film 17e as a mask.

Finally, as shown in FIG. 3M, the capacitor dielectric 11
12 is formed on the surface of storage node 11. A cell plate 13 made of polycrystalline silicon is formed on the entire surface of the silicon substrate 1 on the capacitor dielectric film 12 . In this way, a memory cell having a stacked capacitor cell according to the present invention is completed.

Next, another embodiment of a memory cell having a stacked capacitor cell structure according to the present invention will be described.

FIG. 4 is a partial sectional view showing the structure of a memory cell as another embodiment of the present invention.

The difference from the structure shown in FIG. 1 is that storage node 11 has a side wall portion that is formed to extend substantially perpendicularly to the main surface of silicon substrate 1, and both sides of the side wall portion are It is formed so as to face the surface of the plate 13. This further increases the capacitance of the capacitor. That is, the first
According to the structure shown in the figure, in the storage node 11 formed along the side wall of the interlayer insulating film 10, only one side wall surface is used as a capacitor. According to the structure described above, both sides of the storage node 11 are used as capacitors.

Therefore, the capacitance of the capacitor having the structure shown in FIG. 4 is further increased compared to the capacitor having the structure shown in FIG.

The structure shown in FIG. 4 differs from the structure shown in FIG. 1 in that a silicon nitride film 19 is formed, as will be described in detail in the manufacturing method below.

Next, a method for manufacturing the memory cell structure shown in FIG. 4 will be described. FIGS. 5A to 5P are partial cross-sectional views showing a method for manufacturing a memory cell according to another embodiment of the present invention in order of steps. Note that the manufacturing steps shown in FIGS. 5A to 51 are similar to the manufacturing steps shown in FIGS. 3A to 31, so the explanation thereof will be omitted.

Referring to FIG. 51, underlay pad 9 made of polycrystalline silicon is formed so as to be in contact with impurity region 5.6 connected to the capacitor section.

Fifth, referring to the figure, a silicon nitride film 19 is formed to at least cover only the region where bit line 8 is formed.

Referring to FIG. 5L, a thick silicon oxide film 101 is formed over the entire surface of silicon substrate 1. Referring to FIG.

As shown in FIG. 5M, using a resist film 17d formed on the silicon oxide film 101 according to a predetermined pattern as a mask, a deep contact hole is formed in the interlayer insulating film 101a so as to expose the surface of the underlying pad 9. The hole is drilled.

As shown in FIG. 5N, a polycrystalline silicon film 111 is formed over the entire surface along the inner surface of this contact hole and the upper surface of interlayer insulating film 101a.

As shown in FIG. 50, polycrystalline silicon film 111 is etched off over the entire surface by performing an anisotropic etching process such as reactive ion etching without using a mask. In this way, the interlayer insulating film 1
The polycrystalline silicon film 111 is left only on the sidewall of the deep contact hole 01a. As a result, a storage node 11 is formed so as to be connected to an underlying pad 9 made of polycrystalline silicon. After that, the entire surface of the interlayer insulating film 101a is removed using a wet etching jig.

At this time, bit I! Since the silicon nitride film 19 formed above the bit line 8 formation region is used as a mask, the insulating film formed on the bit line 8 is not removed.

Finally, as shown in FIG. 5P, capacitor dielectric film 12 is formed to cover the surfaces of underlying pad 9 and storage node 11. A cell plate 13 made of polycrystalline silicon is formed on this capacitor dielectric film 12. In the manner described above, a memory cell as another embodiment of the present invention is completed.

Note that in the above embodiment, M constituting the memory cell is
Although an LDD structure is used for the transistor (OS), any structure may be used as long as it operates as a switching element, such as a single structure, a DDD structure, or a gate overlap structure.

Further, in the above embodiment, the gate electrode, the bit line,
Although polycrystalline silicon is used as the material for the underlying pad, storage node, and cell plate, a silicon metallized film or a laminated film of these may also be used.

[Effect of the Invention 1 As described above, according to the present invention, the storage node can be formed to extend both substantially perpendicularly and horizontally to the main surface of the semiconductor substrate, so that the surface area of the storage node can be reduced. can be further expanded. Therefore, it is possible to further increase the capacitor capacity.

Further, since the bit line is located below the storage node, there is no need for deep contact between the bit line and the substrate, so disadvantages in the manufacturing process can also be eliminated.

4. Drawings) Explanation FIG. 1 is a partial sectional view showing the structure of a memory cell of a semiconductor memory device according to an embodiment of the present invention, and a corresponding partial plan view.

FIG. 2 is a partial plan view showing a planar arrangement of memory cells of a semiconductor memory device according to an embodiment of the present invention.

Figure 3A, Figure 3B, Figure 3C, Figure 3D, Figure 3E,
Figure 3F, Figure 3G, Figure 3H, Figure 3I, Figure 3J,
3, FIG. 3, FIG. 3L, and FIG. 3M are partial cross-sectional views showing, in order of steps, a method for manufacturing a memory cell of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a partial cross-sectional view showing the structure of a memory cell of a semiconductor memory device according to another embodiment of the invention.

Figure 5A, Figure 5B, Figure 5C, Figure 5D, Figure 5E,
Figure 5F, Figure 5G, Figure 5H, Figure 51, Figure 51,
5th figure, figure 5L, figure 5M, figure 5N, figure 50,
FIG. 5P is a partial cross-sectional view showing a method of manufacturing a memory cell of a semiconductor memory device according to another embodiment of the present invention in order of steps.

FIG. 6 is a block diagram showing the overall configuration of a conventional DRAM.

FIG. 7 is an equivalent circuit diagram corresponding to one memory cell of the DRAM shown in FIG. 6.

FIG. 8 is a partial cross-sectional view of a prior art structure of a memory cell having stacked capacitor cells.

FIG. 9 is a partial plan view showing the planar arrangement of memory cells corresponding to the structure shown in FIG. 8.

FIG. 10 is a partial cross-sectional view showing the structure of a memory cell having a conventional stacked capacitor cell.

FIG. 11 is a partial cross-sectional view showing another prior art structure of a memory cell having stacked capacitor cells.

FIG. 12 is a partial cross-sectional view showing the internal arrangement of memory cells 4 corresponding to the structure shown in FIG. 11.

In the figure, 1 is a silicon substrate, 2 is a gate oxide film, and 3 is a silicon substrate.
is a gate electrode, 5 is a high concentration impurity region, 6 is a low concentration impurity region, 8 is a bit line, 11 is a storage node, 12
1 is a capacitor dielectric film, and 13 is a cell plate.

Note that in each figure, the numbers -n indicate the same or corresponding parts.

Fig. 2 6: Ipi (3 hours in a row) 11 Figure 812 Figure 3, Procedural amendment written by the person making the amendment (voluntary) Flat bottom 2 years 0 month '12 Representative 5, Subject of amendment (1) Detailed explanation column of the invention in the specification (2) Number of drawings 11. Contents of correction in FIG. 6 (1) "Electric storage section" on page 6, line 20 of the specification is corrected to "charge storage section."

(2) In pages 8, lines 16 to 18 of the specification, "therefore, to be connected" is corrected to "therefore, with the end of the cell plate 133."

(3) Correct "margin" on page 11, line 18 to line 19 of the specification to "margin M".

(4) "Insulating film" on page 25, line 6 of the specification is corrected to "silicon oxide film."

(5) Figure 11 of the drawings will be amended as shown in the attached sheet.

that's all

Claims (2)

[Claims] (1) A field effect transistor having one impurity region and the other impurity region formed on a semiconductor substrate, a wiring layer connected to one impurity region of the field effect transistor, and a stacked layer structure connected to the other impurity region A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type having a main surface; and a charge storage section formed on the semiconductor substrate and spaced apart from each other so as to define a channel region. a gate electrode formed above the channel region via an insulating film; and a gate electrode formed above the gate electrode so as to be in electrical contact with the one impurity region. The formed wiring layer is formed to have a sidewall portion that electrically contacts at least the other impurity region and extends substantially perpendicularly to the main surface of the semiconductor substrate, and is located above the wiring layer. A semiconductor memory device comprising a storage node and a cell plate formed on the storage node with a dielectric film interposed therebetween. (2) A field effect transistor having one impurity region and the other impurity region formed on a semiconductor substrate, a wiring layer connected to one impurity region of the field effect transistor, and a stacked layer structure connected to the other impurity region A method for manufacturing a semiconductor memory device having a charge storage section comprising: forming gate electrodes at intervals from each other on the main surface of a first conductivity type semiconductor substrate with an insulating film interposed therebetween; a step of forming one impurity region and the other impurity region separated by a gate electrode; a step of forming an insulated wiring layer above the gate electrode so as to be in electrical contact with the one impurity region; forming an insulating layer on the wiring layer, the insulating layer having a recess formed of a bottom surface exposing a surface of the other impurity region and a side surface extending substantially perpendicularly to the main surface of the semiconductor substrate; and at least the recess. forming a storage node in electrical contact with the bottom surface and extending along the side surface; and forming a cell plate on the storage node via a dielectric film. Method of manufacturing the device.