JPH0364111A - Memory device and digital signal processing device using the same - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing an access means writing a data to an address of a 1st memory represented by a 1st initial value, and reading a data written in an address represented by a count of a 2nd counter. CONSTITUTION:The device is provided with a 2n-bit 1st counter 1 counting clocks, a 2nd counter counting clocks by using a count of high-order n-bit as the initial value when low-order n-bit of the 1st counter 1 has a carry or reaches an optional initial value and a 1st memory 200 using the count of the 2nd counter as the address for the access. Then a data is written to an address represented by the initial value of the 2nd counter 2. That is, when the low-order bit of the 1st counter 1 is counted for 2<n> number of times, the succeeding sampling is implemented, the count of the 2nd counter 2 is incremented and the data at that time is written. Thus, only one write is implemented for sampling periods caused for each 2<n> number of times of the low-order n-bit and the power consumption for the write is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital signal processing device used in a digital filter and a memory device built therein, and particularly relates to a digital signal processing device used in a digital filter and a memory device built therein.
The present invention relates to a memory device that stores numerical values for product-sum calculations of filters, and a digital signal processing device that performs the calculations.

[Conventional technology]

For example, when implementing an FIR filter as a digital filter, sampling data
. −〇 and the filter coefficients must be used to perform the sum-of-products operation shown in equation (1) below.

However: Number of samplings n: Number of taps of the digital filter (natural number) Figure 14 is a processing flow diagram of the filter calculation shown in equation (1) by the PIR filter, in which the latest sampling data X is multiplied by the filter coefficient h0. , and the result of multiplying the previous sampling data Xk-1 by the filter coefficient , and repeat this in order to perform the product-sum operation shown in equation (1).

Figure 9 shows a conventional digital signal processing device (hereinafter referred to as Digital Sign) for realizing an FIR filter.
1 is a block diagram showing the configuration of a main part of an alProcessor DSP. In the figure, 200 is a data RAM for storing sampling data X(k,,i,), and the sampling data The multiplier 202 multiplies them and provides the multiplication result to one end of the adder (ALU) 203.Adder 2
At the other end of 03 is an accumulator (ACC) 2 which will be described later.
The previous addition results held in 04 are given, and these additions are performed. The addition result is held in the accumulator 204 and given to the other end of the adder 203 at the next timing.

In the DSP configured in this way, the data RAM 20
Sampling data Xn-=r stored in 0,
The filter coefficients stored in the data ROM 201,
are successively output every cycle and input to the multiplier 202. The multiplication result is input to one end of the adder 203, and added to the value held in the accumulator 204, that is, the previous addition result, input to the other end. In this way, the sum-of-products operation of equation (1) shown in the processing flow of FIG. 14 can be executed at high speed.

Next, the data RAM 200 and data ROM at this time
The data arrangement in 201 will be explained. 11th
The figure shows the filter coefficients written in the data ROM.

is a diagram showing the arrangement order of the latest sampling data
The coefficient ho for 3 is at address 0, and the filter coefficient X for the oldest sampling data X3-(N-1)
k-(N-11 is written at address N-1. These filter coefficients are predetermined and stored in the ROM.
This array cannot be changed during the operation. FIG. 12 is a diagram showing the arrangement order of sampling data X (k-41) written in the data RAM,
The latest sampling data is always written to address 0, and the oldest sampling data is always written to address N-1. For example, at sampling time t1, FIG. 12(a)
12(b) at sampling time tk++ one sampling period later.
By changing the arrangement order to the state shown in FIG. 14, the output of the FIR filter according to the processing flow shown in FIG. 14 can be easily obtained. That is, in the FIR filter, high-speed calculation processing is possible by delaying sampling data by one period for calculation in the next period for each sampling period.

Japanese Patent Application Laid-Open No. 63-2011 has proposed a method for easily realizing a one-cycle delay of sampling data written to this data ROMI.
There is one disclosed in Japanese Patent No. 66576. FIG. 10 is a block diagram showing the structure of the data ROM 1M of the DSP disclosed in the publication. In the figure, 200 is data R
OM, and a basic clock signal φ supplied from a control circuit (not shown) in the DSP. The memory cycle operates according to the basic clock signal φ.

defined by. Also, the data RAM 200 is a memory enable signal supplied as a control signal from the control circuit. According to the IE, the memory cycle is set to a selected state as a unit period. At this time, the operation mode of data RAM 200 is determined according to address shift mode signal SN and read/write signal R/H supplied from the control circuit. That is, each of the above-mentioned signals is applied to the timing generation circuit 5, which generates control signals to be described later for each section. In addition, within the data RAM 200, there are RAM cells as storage elements that are composed of a decoder 12 that decodes manually input address signals, a memory array 13 consisting of word lines and data lines, and a sense amplifier 11 to which the data lines are connected. A section 10 is provided, to which sampling data is latched and sampling data is outputted via a data bar 3 which latches sampling data read therefrom. Also RAM
The address given to the cell section 10 is specified by the address pointer 7, and the output thereof is a 10 I-bit address signal formula 0 to Ak and an address signal obtained by adding 1 to it by the plus I circuit 8, which is given to the selector 9. The selector 9 is given the timing signal φ, 2 from the timing generation circuit 5, and depending on its “L” or “M”, the address signal A0 to A of the address pointer 7 or the output of the plus 1 circuit 8 is output. is selected and outputted to the decoder 12 as a complementary internal address signal, LJ~~-04-.The decoder 12 is given a timing signal φ from the timing generation circuit 5, and when it is at "H", the complementary internal address signal is outputted to the decoder 12. A timing signal φ5° is applied to the sense amplifier 11, and its "H" level causes the memory array 1 to decode.
The data on data line No. 3 is read out. Further, the data buffer 3 is supplied with a write signal φ8 and a read signal φ from the timing generation circuit 5, and writing and reading of sampling data is performed by these H°''.

Next, the operation of the conventional data RAM configured as described above will be explained. FIG. 13 is a timing chart showing the access operation of the data RAM. Data RAM 2
In 00, the normal read mode shown by a solid line or the normal write mode shown by a broken line is performed in the first half of the memory cycle, and the address shift mode is performed in the second half of the memory cycle. The address shift mode is a mode that is executed when the address shift mode signal SN is "H". In this mode, the data 7174M 200 reads sampling data in the first half of the memory cycle, and in the second half reads the successive sampling data. Write to the address corresponding to the sampling period. As a result, reading and shifting of sampling data for product-sum calculations related to filter calculations can be performed simultaneously, and high-speed processing becomes possible. In order to obtain an address signal corresponding to the next sampling period based on the applied address signal, there is a plus 1 circuit 8 and a selector 9 that selects two address signals.

Data [lAM 200 is the basic clock signal φ. II HII between the memory enable signals prior to the rising edge of
, and is kept in the selected state only during the next i-meso recycling period. Simultaneously with this memory enable signal ME, the operation mode of the data RAM 200 is set in which the address shift mode signal SN and the read/write signal R/'W become u Ht+ or "'L".

In FIG. 13, the data RAM 200 is in the selected state in the normal read mode in the next memory cycle when the memory enable signal and the read/write signal R/W become "HIT" and the address shift mode signal SN becomes L''. The data RAM 200 has a memory enable signal ME and +1 bit address signals A, -.
Ak is supplied. Address signals A0 to All specify the desired data storage address "h".These address signals are input when the address shift mode signal SN is "L".
', and since the timing signal φ□ is set to "L", it is selected by the selector 9 and is supplied to the decoder 12 as complementary internal address signals 2 to 2.

In the data RAM 200, the basic clock signal φ. At the rising edge of , the memory enable signals are at ``T'', so the tie-off signals φ and Q become ``H'' for l memory cycle period, and the timing signal φ8 is gradually delayed.
1 and the read signal φ4 become "H" in sequence. Timing (when the word φaQ becomes "Hn", the decoder 12 enters the operating state, and one word line specified by the address signals A0 to A, that is, the address The word line corresponding to h11 becomes selected. Also, when the timing signal amount becomes "41", the sense amplifier 11 becomes activated, and the memory cell connected to the selected word line is transferred to the corresponding data line. The output read signal is amplified by the corresponding unit circuit of the sense amplifier 11.

Next, when the read signal amount becomes "H", the read data at address "h" amplified by the sense amplifier 11 is stored in the data buffer 3.

and the basic clock φ. The read mode ends because the memory enable signal amount becomes "L" prior to , and each circuit of the data RAM 200 enters a non-selected state.

Basic clock signal amount. At the rising edge of , when the memory enable signal ME is set to "H" and the read/write signal R/W is set to "L" at the same time, the data RAM
200 starts normal write mode.

At this time, in the data RAM 200, as shown by the broken line in FIG. 13, the write signal amount 8 becomes "H" when the word line selection operation is completed, and the write signal amount 8 becomes "H" as shown by the broken line in FIG. Data is input to a plurality of selected memory cells via the data buffer 3.

On the other hand, as shown in the second half of FIG. 13, the basic clock signal amount. When the memory enable signal ME is set to "H" at the rising edge of , and the address shift mode signal SN is set to "H" at the same time, the data RAM 200 starts the address shift mode.

Address signals A0 to A3 are supplied to the data RAM 200 along with a memory enable signal ME, and the read/write signal R/W is set to "H". Address signal A6~
Ak specifies address "i" where desired sampling data is stored.

In the data RAM 200, the basic clock signal amount. Since the memory enable signal MIE is "H" at the rising edge of , the timing signal φ□ becomes "HII" for one memory cycle period, and the timing signals φ□ and φ7 sequentially become "HII" with a little delay.

As a result, a continuous read operation similar to that in the read mode described above is performed, and the data stored in the memory cell at the address "HT1" is stored in the data buffer 3.

However, the basic clock signal amount. At the falling edge when the address shift mode signal SMi becomes “L”, the address shift mode signal SMi<“
Therefore, in the data RAM 200, the timing signal φ□ is set to "H".As a result, the selector 9 selects the output signal of the plus 1 circuit 8, that is, the address signal "i+1", and the complementary internal address signal 5-11
The signal is supplied to the decoder 12 as a signal. Also, at this time, the timing signal amount.

Before the timing signal φ, II is set to “H”, the timing signal φ, II
is temporarily set to "L II", and is set to "H" again at the time when the decoding operation by the decoder 12 is completed.

In other words, during a period in which the address signal transitions and the decoding operation by the decoder 12 is in a transient state, the decoder 1
The second word line selection operation is prohibited, and all word lines become unselected.

timing signal amount. is set to "H" again, so that the word line corresponding to address "i+1" is placed in a selected state. At this time, each data line and the sense amplifier 11
The read signal of the address signal read in the first half of this memory cycle remains established. Therefore, the read signal of the address signal read in the first half of this memory cycle remains established. Therefore, the read signal of the address signal read in the first half of this memory cycle remains established. The sampled data at the read address "i" is written.

In other words, the sampling data read from address "i" is output via the bus and written as is to address "i+1" corresponding to the next sampling period, essentially realizing a shifting process of sampling data. be done.

[Problem to be solved by the invention]

In the conventional data RAM configured as described above, in the address shift mode in which sampling data is read for the product-sum operation related to the filter operation, data is always written to an address that is the read address plus 1 when reading data. Since this is performed, more transistors must be operated than during reading, which poses a problem in that power consumption increases.

This invention was made in view of the above circumstances, and instead of changing the entire data arrangement in the data RAM between machine cycles, by changing the address specified by the address pointer, it is possible to access the data at high speed and reduce consumption. Memory device with reduced power and DSP using the same
The purpose is to obtain.

[Means to solve the problem]

The memory device according to the present invention counts 2n clocks.
When the first counter of bits and the lower n bits of the first counter carry over or reach an arbitrary initial value,
A second counter that counts the clock using a count value of upper n bits as an initial value, and a first memory that is accessed using the value of the second counter as an address,
The digital signal processing device according to the present invention writes data to the address indicated by the initial value of the second counter and reads the data written to the address indicated by the second counter. The above-mentioned memory device is provided with a second memory accessed using the value of the lower n bits of the first counter as an address, and the outputs thereof are subjected to a product-sum operation.

[Effect]

In the memory device of the present invention, when the lower bit of the first counter counts 2'' times, the next sampling is performed, the value of the second counter is incremented, and data is written at that time.

Therefore, writing is performed only once in every 2'' sampling period of the lower n bits, reducing power consumption required for writing.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings showing one embodiment thereof. FIG. 1 is a block diagram showing the configuration of a memory device according to the present invention. In the figure, 100 is a memory device, which is a data RAM 2 that stores sampling data.
Data ROM 20 that stores 00 and filter coefficients.
1. Further, l is a 2n-bit write address counter, which counts the clock φ1 supplied from a control circuit (not shown), and outputs the counting result of the upper n bits to the address counter 2 and the counting result of the lower n bits. Circuit 5 and data RO? 'l 201 respectively. The data ROM 201 uses the count result of the lower n bits for addressing when reading out the filter coefficients.

The timing generation circuit 5 generates a write signal -R and a count signal CT based on the count result of the lower n bits and the clock φ1. Write signal WR is address counter 2
and is given to the data RAM 200, and when loading the upper n bits of the write address counter 1 to the address counter 2 and writing sampling data to the data RAM 200, that is, every 2 degrees when the lower n bits become O, "H" is applied.
” and is used as their control signal.The count signal CT is also given to the address counter 2 and used for counting by the address counter 2.This shift signal C
T normally has the same timing as the clock φ, but becomes "L" when the write signal WR is °HII.

Data RAM addressed by address counter 2
? 200 sampling data is in data register A3
A clock φ is supplied from a control circuit (not shown). The filter coefficients of the data ROM 201, which are latched by the write address counter 1 and addressed by the lower n bits of the write address counter 1, are simultaneously latched into the data register A3.

Next, addressing in the address counter 2 of the memory device 100 configured as described above will be explained. Write address counter 1 has 2n bits, clock φ1
is incremented by

The lower n bits of write address counter 1 are data RO
Always output as the address of M 201, from O to 2'
It indicates values up to -1, and the top n pinpoints are output as the initial value of the address counter 2.

In the timing generation circuit 5, the lower n bits of the output of the write address counter 1 are all “H” = 2”1 to “L”.
It detects that the change to 0=0, outputs a write signal -R, and inputs the value of the upper n bits output from the write address counter 1 to the address counter 2 as an initial value for counting. That is, as mentioned above, the write signal -R becomes enabled once every 2'1 machine cycle = "H", and the D
The SP executes processing at an operating speed where this 21% machine cycle corresponds to one sampling period. Therefore, the lower n bits of write address counter 1 make one round from O to 2''-1 in one sampling period, and the data ROM 201 is accessed by the address indicated by it, and the upper n bits of write address counter 1 take one sampling period. The sampling data is incremented by 1 each time, and the sampling data is written to the address of the data RAM 200 that it points to.Additionally, in the address counter 2, the upper n bits of the manually inputted write address counter 1 are used as the initial value, and the sampling data is incremented by 1 by the count signal CT. The data RAM 200 is accessed by the address pointed to by the address.

Next, the operation of the memory device 100 configured as described above will be explained.

FIG. 2 is a timing chart explaining the addressing operation of the memory device, and FIGS. 3 and 4 are diagrams showing data arrays in the data RAM and data ROM.

As shown in FIG. 4, a filter coefficient h for the latest sampling data is stored in the data ROM 201 at address 0.
0 is also the filter coefficient h2n corresponding to the oldest sampling data sequentially from address l to address 2'i.
New filter coefficients h2''-2'...h, starting from -1
is stored.

The time tk for sampling the k-th sampling data Sampling data Xk is written to address i of data RAM 200. The relationship between k and i is: i = k (+wod, 2')'' (3) However, i = o, 1. ..., 2'-1. Here, equation (3) is expressed by changing k to 2. The remainder after dividing by `` is the address i.

In addition, in order to execute the calculation of the digital filter during the sampling period Δt, T=Δt/2” (4) However, 2f1: Data ROM 201 and RAM Since the data must be read from 200 and the sum of products operation must be performed, R
The address l of successive data of AM 201 is 1 = (i
+p) (mod, 2") ・"(5) However, p=o
, 1. ..., is given by 211-1-. the above(
4) The period T in the equation corresponds to one cycle of clocks φ0 and φ1, the above i corresponds to the value of the upper n bits of the output of the write address counter 1, the above p corresponds to the value of the lower n bits, and The above 2 corresponds to the value of n bits output from the address counter 2.

Assume that sampling data Xk-1 is written to address me 1 of data RAM 200 at sampling time tk-1. At this time, the arrangement of sampling data in the data RAM 200 is as shown in FIG. 3(a), with the oldest sampling data Xk-! at address i. D
is stored, and newer sampling data are stored sequentially from there to address 2'-1. Then, sequentially from address 0, sampling data X k-4+
Xk-(i-1>...X car 2 is stored.

With this state as the initial state of the data RAM 200, when the lower n bits of the write address counter 1 are all "L" at sampling time tk, that is, p=o in equation (5), the write signal WR changes from "L" to "L". The value i of the upper n bits of write address counter 1 changes to “H”.
is loaded into the address counter 2, and the value i is set as the initial value of the address counter 2. The sampling data Xk is written to the data RAM 200 using the value i of the address counter 2 as an address, and
becomes the state shown in FIG. 3(b). In FIG. 3(b), the latest sampling data X of l at the sampling time point is written to the address pointed to by the value i, and the oldest data Xk-+2 n-t> of the address pointed to by the value i+1 is written. ing.

That is, the latest sampling data X at the sampling time tk was written in the arrangement position of the oldest sampling data in FIG. 3(a) to obtain the arrangement shown in FIG. 3(b). Moreover, the sampling data X6 is a clock φ. The data is written to the data RAM 200 and inputted to the data register A3 at the same time as the tie selection.

On the other hand, since the data ROM 201 is accessed by the lower n bits of the write address counter 1, the filter coefficient h0 stored at the address O is the clock φ. The data is read out at the timing of and input to the data register B4.

When the write signal WR becomes "L I+" and the data read cycle state is entered, the write address counter 1 and address counter 2 are incremented by the clock φ and become p-t, and the address l of the liAM 200 is set as the address l from equation (5). R= (i+1)(iod, 2") -t+1 is obtained, and the oldest data The filter coefficients h2n-1 stored in are sequentially output and manually entered into data register A3 and data register B4, respectively.

Furthermore, with the next clock φ1, write address counter 1 and address counter 2 are incremented, and P
= 2, and from equation (5), the sampling data X1l-(211-21, which is one newer than the oldest sampling data stored in the address amount +2), is also the data RO
The filter coefficient h2n-2 stored at address 2 is read from M201 and input to data register A3 and data register B4, respectively. This operation is performed when the lower n bits of write address counter 1 are all “H”.
That is, repeat until p=2"-1. During this period, the address counter 2 is incremented 2"-1 times, and the latest sampling data xk and the oldest sampling data Xk-
(The sampling data is sequentially read out to the data register A3 in the order of 2r+Xk-+2n-9...+Xk-1.

Also, the data ROM 201 is a write address counter 1.
The lower n bits of the address are used as the address O1 and l...
. The filter coefficients h Olb zn-1 .

At sampling time ta+1, the lower n bits of write address counter 1 change from all "H" to all "L" again.
”, that is, p=2” -1 to P-0, the write signal WR changes to “H” and the upper n bits of write address counter 1 (! i + i
is set, and sampling data X and I are data l?
It is written to the address of the value i+1 of the API 200, and the result becomes as shown in FIG. 3(C), similar to the case of FIG. 3(b).

At the same time, sampling data X and l are written into data register A3.

At this time, the lower n bits of the write address counter 1 are all "L" (p=0), so the filter coefficient stored at address 0 of the data ROM 201 is read out to the data register B4. When the write signal -R becomes "L", the address counter 2 uses i+1 as the initial value and clock φ1.
The increment is started by P=1+ P=2・
..., P=2' -1 and the oldest sampling data X1l<zn-try Xk-(!+11)+...
- Read sampling data to data register B4 in the order of +Xk. In addition, the data ROM 201 uses the lower n bits of the write address counter l as an address and sets the address 1. Address 2...Filter coefficient h2n-1+ h2n-2+ stored in address 2''-1
..., read hI to data register B4.

In this way, at sampling time f-k+2, all the lower bits of write address counter 1 are set to "all from H11" again.
When the write signal -R becomes "H", the value of the upper n bits of the write address counter l is incremented to 1+2, and the sampling data X1l is written to the address of value i+2 of the data RAM 200 and read to the data register A3, and since the lower n bits of the write address counter 1 are all “L” (p=o), the value is written to the address 0 of the data ROM 201. The stored filter coefficient h0 is read out to the data register B4.This process is repeated to perform writing and reading of sampling data and successive output of filter coefficients.

As a result, it is only necessary to write the sampling data once in the sampling period, and there is no need to write it every time it is read as in the conventional case, and the number of write operations is reduced to 1/2'' of the conventional number of times.

Next, other embodiments of the invention will be described.

FIGS. 5 and 6 are diagrams showing data arrays in the data RAM and data ROM of other embodiments. In this embodiment, unlike the previous embodiment, the write address counter 1 and the address counter 2 are composed of decrementing counters, so that the sampling data stored in the data RAM 200 is the same as that shown in FIG. The filter coefficients stored in the data ROM 201 are arranged symmetrically around , and the order of arrangement with respect to the addresses is reversed from that shown in FIG. That is, in the data RAM 200, sampling data Xk-(f+I) is stored at address O, and sampling data
The oldest sampling data Xk-4'' is stored at address i.
In 201, the filter coefficient corresponding to the latest sampling data Xk-1 is stored at address 2'-1. However, the oldest sampling data Xk,,2 is at address 2″-2.
Filter coefficients 11211'-1 corresponding to 11 are stored, respectively. In this case, the only difference in operation is increment and decrement, and the other operations and configurations are the same as those in the above-described embodiment, so their explanation will be omitted.

Next, still another embodiment will be described.

In the two embodiments described above, counting starts from 0 for the lower n bits of the write address counter l, and the value of the upper bits when the counted value is carried over (overflow) is set as the initial value of the address counter 2. , in this embodiment, counting of the lower n bits starts from an arbitrary value A.

FIG. 7 is a block diagram showing the configuration of a memory device according to still another embodiment. In this embodiment, the count value of the lower bits is manually input to the matching circuit 6, and when it is determined that the count value matches A, the determination is sent to the timing generation circuit 5, and at the determined timing, the write signal WR is generated. ="HII" is output. At that time, the count signal CT is "L 1
It becomes 1. That is, in the data RAM 200, the lower n
Every time the counted value of the bits matches the value A (every 2'' times), data is written to the address indicated by the counted value of the upper n bits at that time.Other configurations and operations are the same as those described above. Since this is the same as the example, the explanation will be omitted.

In the embodiments described above, each counter is configured as a counter that increments or decrements, but it goes without saying that either one of the counters may be decremented and the other may be incremented.

Further, in the above embodiments, the case where the memory device is used in a DSP has been described as an example, but the memory device can also be used in other data processing devices.

Next, the DSP according to the present invention will be explained. FIG. 8 is a block diagram showing the configuration of the main parts of the DSP of the present invention for realizing an FTP filter. 100 in the figure
is a memory device of the present invention, and the j-th output Xk-4 of the data RAM 200 of the sampling period and the filter coefficient , which are outputted from the memory device, are given to a multiplier 202 and multiplied there.

The multiplication result is given to one end of the adder (ALU) 203, and the 11th multiplication result given to the other end of the adder (ALU) 203 is
It is added to the addition results up to the th addition, and is held in the accumulator (ACC) 204. The retained addition result is provided to the other end of adder 203.

In the DSP configured in this way, the sampling data X, -3 and the filter coefficients are clock φ. It is read out at the timing of , and multiplication, addition, and retention are performed.

This is repeated 2n times, and when one sampling period ends, new sampling data is stored in the data RAM 20.
It is written to an address that is incremented by 1 from 0, and a similar operation is performed.

[Effect of the invention] As explained above, according to this invention, the first and second
The addresses of the first memory and the second memory are specified by two counters, and the write operation is performed once per sampling period.
Because it only needs to be rotated, the power consumption of the memory can be reduced and high-speed access is possible. When used in DSP, it has excellent effects such as high-speed access, reduced power consumption, and suppressed heat generation. play.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a memory device according to the present invention, FIG. 2 is a timing chart explaining the addressing operation of the memory device, and FIGS. 3-4 are data RAM diagrams.
, a diagram showing the data arrangement of the data ROM, FIGS. 5 and 6 are diagrams showing the data arrangement of the data RAM and data ROM of another embodiment, and FIG. 7 is a block diagram showing the configuration of the memory device of still another embodiment. 8 is a block diagram showing the configuration of the main part of the digital signal processing device according to the present invention, and FIG.
The figure is a block diagram showing the configuration of the main parts of a conventional digital signal processing device, Figure 10 is a block diagram showing the configuration of a conventional data RAM, and Figures 11 and 12 are conventional data RO1.
13 is a timing chart showing a conventional data RAM access operation, and FIG. 14 is a processing flow diagram of a product-sum calculation in an FIR filter. 1... Write address counter 2... Address counter 5... Timing generation circuit 6...-number circuit 100... Memory device 200... Data RAM
201... Data ROM 202... Multiplier 203... Adder (ALυ) 204... Accumulator (^CC) Note that in the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (3)

[Claims] (1) a 2n-bit first counter that counts clocks; and setting the value of the upper n bits of the first counter as a first initial value based on the value of the lower n bits of the first counter; a second counter that counts the clock; a first memory that is accessed using the value of the second counter as an address; and writing data to the address of the first memory indicated by the first initial value. and access means for reading data written at an address indicated by the value of the second counter. (2) The first counter is configured to start counting from a second initial value where the value of at least the lower n bits is an arbitrary second initial value, and the value of the lower n bits of the first counter and the second initial value are Claim: further comprising a match determining means for determining a match, wherein when the match is determined, the value of the upper n bits of the first counter is set in the second counter as the first initial value. 1. The memory device according to 1. (3) The memory device according to claim 1 or claim 2, a second memory that is accessed chronologically using the value of the lower n bits of the first counter as an address, the first memory, and A digital signal processing device comprising: multiplication means for reading and multiplying values stored in a second memory; and addition means for obtaining a cumulative sum of product signals of the multiplication means.