JPH0364181A - Variable-speed reproduction mode detection circuit - Google Patents

Abstract

PURPOSE:To detect whether an input video signal is in the normal reproduction mode or the vari-speed reproduction mode by discriminating directly the time width of a vertical synchronizing signal included in the input video signal. CONSTITUTION:An input video signal is supplied to a synchronizing separator circuit 1, a composite synchronizing signal (a) is separated and a vertical synchronizing signal extraction circuit 2 integrates the composite synchronizing signal (a) to extract a vertical synchronizing signal (b), an edge detection circuit 3 detects the leading edge of the vertical synchronizing signal (b) and a leading signal (c) of the front edge of the vertical synchronizing signal (b) is fed to a sampling circuit 4. Then the composite synchronizing signal (a) is sampled for a period in excess of the time width of the vertical synchronizing signal included in the video signal at the normal reproduction mode with the detected from ridge taken as a reference and less than the time width of a simulated vertical synchronizing signal inserted to the video signal at the vari-speed reproduction to discriminate directly the time width of the vertical synchronizing signal (b) included in the input video signal. Thus, whether the input video signal is in the normal reproduction mode or the variable-speed reproduction mode is discriminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] Video signal handling equipment (video tape recorder, The present invention relates to a variable speed reproduction mode detection circuit suitable for use in various types of time base collectors, frame synchronizers, etc.).

[Summary of the invention]

The present invention focuses on the fact that the time width of the pseudo vertical synchronization signal inserted into the video signal during variable speed playback is set wider than the time width of the vertical synchronization signal during normal playback, and the time width of the vertical synchronization signal is This is a variable speed playback mode detection circuit that detects whether an input video signal is in variable speed playback mode by direct discrimination, and can be configured with a simple circuit using, for example, a mono multi-by-break and a flip-flop.

[Conventional technology]

Video tape recorder (VTR) variable speed playback (slow,
(still, high-speed search, etc.), the vertical synchronization signal included in the video playback signal may be missing compared to normal playback, and it cannot be played back as a video as it is, so a pseudo Usually, a synchronization signal (pseudo VD) is generated and interpolated or replaced with the pseudo VD.

However, during variable speed playback, the phase relationship between the horizontal synchronization signal in the reproduced video signal and the pseudo-VD is unstable, so it is necessary to synchronize separately from during normal playback, especially when using digital memory. In order to obtain a predetermined timing signal, synchronization processing that is different from that during normal playback is required.

Therefore, it is necessary to detect whether the input video signal is in normal playback mode or variable speed playback mode and switch the synchronization circuit.

As a technique for this purpose, for example, the following technique proposed by the present applicant is known.

First, in JP-A-56-126385, a technique for detecting variable speed reproduction by measuring the cycle of a reproduction vertical synchronization signal was described. Furthermore, in JP-A-56-120268 and JP-A-56-120269, the equalization pulse of the reproduction synchronization signal is counted during a predetermined period from the beginning of the reproduction vertical synchronization pulse, and detection is performed by determining the magnitude of this number. described the technology.

However, in the technique of JP-A-56-126385, the signal is regarded as a normal reproduction signal unless a predetermined frequency change is reached, so there is a problem in that it is not possible to detect all of the variable speed reproduction. For example, during still playback or frame-by-frame playback, there is no frequency change in the vertical synchronization signal, so even if a pseudo VD is generated, it may not be detected. Also, JP-A-5
The techniques of JP-A-6-120268 and JP-A-56-120269 also had the problem of complicated circuits.

[Problems to be Solved by the Invention] The present invention solves various problems of the conventional technology, and can reliably determine whether a human video signal is in normal playback mode or variable speed playback mode with a simple configuration. The object of the present invention is to obtain a variable speed playback mode detection circuit.

[Means to solve the problem]

The present invention includes a circuit for extracting a vertical synchronization signal from a composite synchronization signal separated from an input video signal, a circuit for detecting the leading edge of the extracted vertical synchronization signal, and a circuit for detecting the leading edge f of the extracted vertical synchronization signal. , the equalization pulse exceeds the time width of the vertical synchronization signal included in the video signal during normal playback and is less than the time width of the pseudo vertical synchronization signal inserted (interpolated or replaced) into the video signal during variable speed playback. The variable speed reproduction mode detection circuit includes a sampling circuit that samples the composite synchronization signal at a time when the composite synchronization signal does not exist.

The sampling circuit includes, for example, a sampling pulse generation circuit that generates a sampling pulse for sampling at the period, and a latch circuit that latches the composite synchronization signal in accordance with the generated sampling pulse.

[Effect]

In the present invention, a pseudo vertical synchronization signal (pseudo V
Focusing on the fact that the time width of D) is usually set wide, directly determine the length of the time width of the vertical synchronization signal included in the input video signal, rather than the period of the vertical synchronization signal or the number of equalization pulses. This makes it possible to detect whether the input video signal is in normal playback mode or variable speed playback mode.

For example, the vertical synchronization signal of a video signal normally reproduced by recording an NTSC television signal is selected to have a time width of 3H (H is one horizontal period), whereas the pseudo vertical synchronization signal is selected to have a time width of 6H, for example. Since an equalization pulse is inserted every 'AH in the vertical blanking period of the normally reproduced video signal, for example, 3H and 3.5H are inserted based on the leading edge of the extracted vertical synchronization signal. At about 3.25H in between, the composite synchronization signal separated from the input video signal is sampled and a high! By determining whether the signal is a novel or a low level, it is possible to reliably determine whether it is a vertical synchronizing signal of 3H duration that is normally reproduced or a pseudo VD of 6H duration inserted for variable speed reproduction. As a result, regardless of whether or not there is a change in the period of the vertical synchronization signal, if pseudo VD is included,
An input video signal in variable speed playback mode can be detected.

Furthermore, according to the present invention, the sampling circuit can be configured with the sampling pulse generation circuit, which can be configured with one mono-multivibrator, and the latch circuit, which can be configured with one D-type flip-flop. It can be a circuit configuration.

〔Example〕

An embodiment of the present invention will be described based on the block diagram shown in FIG.

First, the input video signal is connected to a synchronous separation circuit (SYNC, 5EP).
) 1 to separate the composite sync signal a, the vertical sync signal extraction circuit (V, 5EP) 2 integrates the composite sync signal a to extract the vertical sync signal, and the edge detection circuit 3 extracts the vertical sync signal a. Detect the leading edge of The detected rising edge signal C at the leading edge of the vertical synchronization signal is sent to the sampling circuit. The sampling circuit of this embodiment includes a sampling pulse generation circuit 41 consisting of one mono multi-talker bi-break (MM) and a D-type flip-flop (FF).
This is because the latch circuit 42 is configured to latch the composite synchronization signal a in the circuit 42. The MM41 is triggered by the rising edge signal C of the detected vertical synchronization signal S, and generates a sampling pulse of about 3.25)1 (H is one horizontal period). The sampling pulse is M
Since it is extracted from Q from M41, the D-type flip-flop 42 latches the composite synchronization signal a at about 3.25H from the leading edge rising signal C, and the composite synchronization signal a
If the composite synchronization signal is at a high level, a signal 1 is output for determining the normal reproduction mode, and when the composite synchronization signal is at a low level, a signal 0 is output for determining the variable speed reproduction mode from the Q terminal of the D-type PF 42.

Next, FIG. 2 shows a time chart of this embodiment. i)
is the time of normal reproduction, and the composite synchronization signal a has the same form as the decoded synchronization signal in a general television signal. The part marked VD is the width of the vertical synchronizing signal, and the vertical synchronizing signal obtained by integrating the signal a becomes as shown in b. To be exact, the rise of signal S is delayed by a very small amount compared to signal a, but this does not pose any problem for the purpose of the present invention, and signal C indicating the rise of signal S is obtained. Then, a sampling pulse d is generated based on the rising edge of the signal C, and the signal a is latched at the rising edge of the sampling pulse d (point A). Therefore, the level at point A where 3H<A<3.5H in the composite synchronization signal in the normal re-mode is determined to be a high level.

it) and 1ii) show the form of the composite synchronization signal a into which the pseudo VD is inserted in the variable speed playback mode. Even when the pseudo VD is replaced with the vertical synchronization signal, it can be handled in the same way as in 1ii).

The method for obtaining the signal is the same as in the normal playback mode, but the shape of the signal is different from the normal playback mode due to the presence of the pseudo-VD. However, only the rising timing information is obtained from the signal S, and the signal C and the signal d are obtained.

Here, at point A where 3H<A<3.5H, the composite synchronization signal a
When latched, point A is determined to be at a low level because this is the time when pseudo VD exists.

As described above, it is possible to easily and accurately determine whether the input video signal is a normal reproduction mode signal or a variable speed reproduction mode including pseudo-VD, and output the determination result.

According to the time chart in FIG. 2, the latch circuit 4
It can be seen that even if the object to be latched in step 2 is not the composite synchronization signal a, it can be determined by latching the integrated and extracted vertical synchronization signal a. However, here, V, SE of the integral method
In order to simplify the P circuit and to improve accuracy by adjusting the pulse width of the signal d if necessary, the composite synchronizing signal a is directly sampled.

〔Effect of the invention〕

By implementing the present invention, it is possible to obtain a variable speed playback mode detection circuit that can directly determine the length of the time width of a vertical synchronization signal included in an input video signal and determine whether the input video signal is in a normal playback mode or a variable speed playback mode. In other words, by implementing the present invention, it is possible to reliably detect an input video signal in variable speed playback mode as long as it includes a pseudo-VD, regardless of the presence or absence of fluctuations in the cycle of the vertical synchronization signal, and moreover, with an extremely simple configuration. This has the effect of providing a variable speed playback mode detection circuit that can be realized.

This variable-speed playback mode detection circuit is particularly effective in facilitating the handling of video signals in variable-speed playback mode in video signal handling equipment using digital memory, and is expected to be useful in industry.

2----m-・-----1---- Vertical synchronizing signal extraction circuit (V, 5EP) 3 ... Vertical synchronizing signal leading edge detection circuit (edge detection) 4------- −−−−−−−−・Sampling circuit 4t−・−Sampling pulse generation circuit (mono multivibrator MM) 42・−・−・−・−・−Latch circuit (D type flip flop FF)

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. Figure 2 is a time chart of the embodiment of the present invention, i) is normal playback, ii) is variable speed playback (pseudo-VD before VD)
, 1ii) shows the case of variable speed reproduction (pseudo 4g1VD and VD overlap). 1-11--... Synchronous separation circuit (SY
NC, SI! P) 1) Picture output by normal playback Block diagram of the embodiment of the present invention Fig. 11) Variable speed playback (VD before VD) Time chart of the embodiment of the present invention Fig. 2

Claims (1)

[Scope of Claims] A circuit for extracting a vertical synchronization signal from a composite synchronization signal separated from an input video signal; a circuit for detecting a leading edge of the extracted vertical synchronization signal; and a circuit for detecting a leading edge of the extracted vertical synchronization signal; When the time width exceeds the time width of the vertical synchronization signal included in the video signal during normal playback and is less than the time width of the pseudo vertical synchronization signal inserted into the video signal during variable speed playback, and there is no equalization pulse, A variable speed playback mode detection circuit comprising: a sampling circuit that samples a composite synchronization signal.