JPH0364964A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a DRAM of laminated type memory cell structure high in reliability by a method wherein a MOSFET is formed, then a resist is formed on a contact forming region, and an insulating film is deposited thereon, which is etched back. CONSTITUTION:A gate insulating film 3 and a gate electrode 4 are formed on the surface of a P-type silicon substrate 1, and the upper wall of the gate electrode 4 is covered with an insulating film 6t. As ions are implanted using the gate electrode 4 as a mask to form a source and a drain region both formed of an N-type diffusion layer 5 for the formation of a MOSFET which serves as a switching transistor. Then, a side wall insulating film 6s is left on the side wall of the gate electrode 4 in a self-aligned manner. Moreover, a resist R1 is left inside contacts C1 and C2. Furthermore, a silicon oxide film 7 is deposited on a region excluding the surface of the resist film R1. Thereafter, an etching-back resist R2 is applied so as to make the surface flat. The resist R2 applied surface is etched back through a reactive ion etching method to be flattened. Then, the resist R1 is removed, and a contact is formed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor memory device, and in particular to a method for manufacturing a semiconductor memory device.
This relates to the formation of contacts in AM and the like.

(Prior Art) In recent years, due to advances in semiconductor technology, particularly advances in microfabrication technology, so-called MO3 type DRAMs are rapidly becoming more highly integrated and have larger capacities.

With this increase in integration, the area of capacitors that store information (charge) has decreased, resulting in problems such as erroneous reading of memory contents or soft errors in which memory contents are destroyed by alpha rays, etc. It has become.

One way to solve these problems and achieve higher integration and larger capacity is to stack MOS capacitors on the memory cell area, and connect one electrode of the capacitor with a MOS capacitor formed on the semiconductor substrate. A memory cell structure called a stacked memory cell has been proposed in which the capacitance of a MOS capacitor is substantially increased by making the capacitance of a MOS capacitor conductive with one electrode of a switching transistor.

As shown in FIG. 20, this stacked memory cell consists of an element isolation insulating film 1 formed in a p-type silicon substrate 101.
In one memory cell area separated by 02, n
a source and drain region 103 made of a type diffusion layer;
Gate insulating film 10 between source and drain regions 103
4 to form a MOSFET as a switching transistor, and the gate electrode 105 of the MOSFET and the gate electrode of the adjacent memory cell MOSFET ( A polycrystalline silicon film 1 formed on an insulating film 106 (silicon oxide film and BPSG film by CVD method) on the word line)
07 and a bit line 109 made of a silicide film 108, and further insulated on this upper layer! 11110 (silicon oxide film 110a and BPSG film 110b formed by CVD method), the first capacitor electrode 112 and the second
The capacitor insulating film 11 is formed by the capacitor electrode 113 of
4 in between to form a capacitor.

This stacked memory cell is implemented as follows.

That is, in this stacked memory cell, a source and drain region 103 made of an n-type diffusion layer is formed in a p-type silicon substrate 101, and a gate electrode 105 is formed between the source and drain regions 103 with a gate insulating film 104 interposed therebetween. Then, a MOSFET as a switching transistor is formed.

Next, a silicon oxide film 1 is formed around the gate electrode 105.
After coating with 06s and 106t, a silicon oxide film and a BPSG film are further formed by CVD as an insulating film 106 over the entire surface of the substrate, flattened by heat treatment, and then a bit for contacting the drain region 103 is formed. A line contact is formed, and a bit line 109 made of a polycrystalline silicon film 107 and a silicide film 108 is formed.

After that, a silicon oxide film 110a and a BPSG film 110b are formed by CVD as an insulating film 110 over the entire surface of the substrate.
After forming, planarization is performed by heat treatment to form a storage node contact 111, and a first capacitor electrode 11 made of a heavily doped polycrystalline silicon layer is formed.
2 patterns are formed.

Then, by sequentially depositing and patterning a capacitor insulating film 113 made of a silicon oxide film and a polycrystalline silicon layer on this first capacitor electrode 112,
A MOS capacitor sandwiching a capacitor insulation 1111113 is formed by the second capacitor electrode 114 and the first capacitor electrode 112, and the MOSFET and MOS
A memory cell consisting of a capacitor is obtained.

In such a configuration, the storage node electrode can be extended to above the element isolation region, and the step of the storage node electrode can be used, so the capacitance of the capacitor can be increased several to several tens of times that of the brainer structure. can.

Therefore, even if the memory cell area is reduced, the amount of stored charge can be prevented from decreasing.

Furthermore, the diffusion layer in the storage node section is only the diffusion layer 103 under the storage node electrode (first capacitor electrode 111), and the area of the diffusion layer that collects charges generated by α rays is extremely small, which may cause soft errors. It has a strong structure.

However, such a cell structure has the following drawbacks.

One of them is poor flatness and the resulting difficulty in processing.

That is, looking at the number of electrodes, since charges are stored in the storage◆node electrode 112, the number of electrodes increases by one layer compared to a planar cell that stores on a normal silicon substrate.

For this reason, the higher the layer, the worse the flatness of the base layer.
Processing using photolithography and etching becomes difficult, and there is a problem in that open defects and short-circuit defects occur frequently in each electrode.

In other words, the difference in level between the gate electrode and bit line increases the level difference between the top surface of the interlayer insulating film and the substrate, which not only reduces the coverage of the storage node electrode but also makes it difficult to process the storage node electrode and plate electrode. Become.

Furthermore, in consideration of lithography misalignment, it is necessary to provide a margin between the gate electrode and the bit line contact, and between the gate electrode and the storage node contact, which poses many problems when achieving high integration.

Furthermore, since a BPSG film is used to flatten the surface, there is a problem in that P is diffused from the BPSG film through the polycrystalline silicon film 108, resulting in a decrease in separation ability.

In addition, when forming contact holes, especially storage node contacts, the etching depth is deep, so the etching time during RIE is long, and the substrate is often gouged due to overetching due to in-plane non-uniformity of the film thickness. , there is a problem that RIE damage is large.

(Problems to be Solved by the Invention) As described above, even in DRAMs with a stacked memory cell structure, as elements become finer due to higher integration, the alignment margin between gate electrodes, bit line contacts, and storage node contacts becomes smaller. The need to take the necessary steps had become a major obstacle.

Furthermore, since a BPSG film is used to planarize the surface, diffusion of P from the BPSG film has been a problem.

Furthermore, since the contact is formed using the RIE method, there is a problem in that the substrate is seriously damaged.

The present invention has been made in view of the above-mentioned circumstances, and is a DRA with a stacked memory cell structure that can be highly integrated and has a high reliability.
The purpose of the present invention is to provide a method for manufacturing M.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, after forming a MOSFET, a resist is formed in the contact formation region, an insulating film is deposited on the upper layer, and etching back is performed to flatten the resist. The resist is removed and contacts are formed.

(Function) According to the above structure, a resist is formed in the contact formation region, an insulating film is deposited on top of the resist, and etching back is performed.Therefore, there is no RIE damage to the sidewalls of the gate electrode. Bit line contacts and/or storage node contacts can be formed in a self-aligned manner, allowing miniaturization.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

1(a) and 1(b) are plan views showing two bits adjacent in the bit line direction of a DRAM having a stacked memory cell structure formed by the method of the embodiment of the present invention, and FIG. -B sectional view.

This DRAM includes a memory cell region formed in a p-type silicon substrate 1 and separated by an element isolation insulating film 2, and a gate electrode 4 formed on the substrate surface via a gate insulator 1lI3, and a gate electrode 4 formed on both sides thereof. Source and drain region 5
and a storage node electrode 13.
and a capacitor formed by sandwiching the capacitor insulating film 14 between the plate electrode 15 and the plate electrode 15.

This DRAM is characterized in that the bit line contact and the storage node contact are formed in self-alignment with the gate electrode of the MOSFET.

This storage node electrode is also connected to the source/drain 5 of the MOSFET via buried layers 9 and 10 in contacts formed in the interlayer insulating film 7.

For other parts, the DRA has a normal stacked memory cell structure.
It is exactly the same as M.

That is, in an active region separated by an element isolation insulating film 2 formed in a p-type silicon substrate 1 having a specific resistance of about 5 Ω·C, an n-type diffusion layer 5 constituting a source/drain region, A gate electrode 4 is formed between these source and drain regions via a gate insulating film 3 to constitute a MOSFET, and an interlayer insulating film 7 is formed on top of this.
A bit line is formed so as to contact this n-type diffusion layer 5 via a buried layer 9.10 formed therein.

In addition, a buried layer 9.10 formed in the glabella insulating film 7
A storage node electrode 16, a capacitor insulating film 17, and a plate electrode 18 are formed to contact the other side of the source/drain via.

The gate electrodes 4 are continuously arranged in one direction of the memory array to form word lines.

Next, a method for manufacturing this DRAM will be explained with reference to the drawings.

2 to 18 are diagrams showing the manufacturing process of this DRAM. In FIGS. 4 to 6, (a) and (b)
) are A-B in the plan view shown in FIG. 4(e), respectively.
This corresponds to a sectional view and a B-C sectional view.

First, as shown in Figure 2, p
After forming an element isolation insulating film 2 on the surface of a molded silicon substrate 1 by a normal method, a film thickness of 10 nm is formed by a thermal oxidation method.
After forming a silicon oxide layer of 200% by CVD method,
A polycrystalline silicon layer and an insulating film of nI are deposited and patterned by photolithography and reactive ion etching to form a gate insulating film 3 and a gate electrode 4.
At the same time, the earthen wall of the gate electrode 4 is covered with an insulating film 6t.

Then, using this gate electrode 4 as a mask, As ions are implanted to form a source/drain region consisting of an n-type diffusion layer 5, and a MO as a switching transistor is formed.
Form an SFET. The depth of this diffusion layer is, for example, 15
It should be about 0 nI. Thereafter, an interlayer insulating film made of a silicon nitride layer with a thickness of about 100 mm is deposited on the entire surface by CVD, and the entire surface is etched by reactive ion etching to form a sidewall insulating film on the side surface of gate electrode 4.
It is left as S in a self-consistent manner. In this way, the source/drain regions are exposed and the contacts C1,
C2 is formed.

Furthermore, as shown in FIG. 3, a resist is applied and the resist R1 is left in the contacts C1 and C2 by photolithography.

Further, as shown in FIGS. 4(a) to 4(C), areas other than the surface of the resist film R1 are formed by liquid phase growth (LPD) using a hydrofluoric acid aqueous solution in which silica is supersaturated. A silicon oxide layer 7 is deposited on the surface. Here, the silica-saturated aqueous solution of hydrofluoric acid is prepared by adding boric acid (Ha Bo3) to the silica-saturated aqueous solution of hydrofluoric acid.
Obtained by adding an aqueous solution or the like. Note that an SOG film may be used instead of the LPD oxide film 7 formed here.

After this, as shown in FIGS. 5(a) and 5(b), an etch-back resist R2 is applied to flatten the surface.
Apply.

Then, as shown in FIGS. 6(a) and 6(b), etchback is performed by reactive ion etching,
Flatten the surface.

After that, as shown in FIG. 7, the resist R1 is removed,
Form a contact.

Furthermore, as shown in FIG. 8, polycrystalline silicon 9 with a thickness of about 50 nm is deposited on this upper layer by the CVD method.
By ion implantation of arsenic or phosphorus or phosphorus diffusion,
After doping, patterning is performed by reactive ion etching.

Subsequently, as shown in FIG. 9, a silicide film 10 is further deposited on this upper layer. Note that this may also be a polycrystalline silicon film.

Then, as shown in FIG. 10, this silicide film 10 and polycrystalline silicon 9 are etched back, and the surface is planarized in such a state that they are buried in the contacts C1 and C2. Note that here, this silicide film 10
Although the polycrystalline silicon 9 constitutes a pad electrode, the bit line may be directly etched.

Furthermore, as shown in FIG. 11, after depositing a silicon oxide film 11 by the CVD method, a resist pattern R2'
Bit line contacts are opened by photolithography and reactive ion etching using as a mask.

Then, as shown in FIG. 12, a silicide film 13 and an insulating film 12 are deposited, and both are etched by reactive ion etching to pattern the bit line 13.

Furthermore, as shown in FIG. 13, a silicon oxide film 14 is deposited on the entire surface and etched back using a reactive ion etching method, leaving the silicon oxide film 14 only on the side walls, and a resist layer is applied to the storage node contact forming area. R3 is formed on this upper layer, and the area other than the surface of resist film R3 is oxidized by liquid phase growth (LPD) using a hydrofluoric acid aqueous solution supersaturated with silica, as shown in FIG. A silicon film 15 is deposited.

Then, as shown in FIG. 14, a resist R4 is applied to flatten the surface.

In this state, as shown in FIG. 15, etchback is performed by reactive ion etching to flatten the surface.

After this, as shown in FIG. 16, the resist R3 is removed and a storage node contact is formed.

Furthermore, as shown in FIG. 17, the surface of the silicide film 10 is exposed by wet etching, and polycrystalline silicon 16 with a thickness of about 50 nm is deposited on this upper layer by the CVD method, and arsenic or phosphorus ions are implanted. Alternatively, doping is performed by phosphorus diffusion or the like.

Thereafter, as shown in FIG. 18, patterning is performed by photolithography and reactive ion etching to form a storage node electrode. R5 is a resist.

Then, the capacitor insulating film 17 and the plate electrode 18
A capacitor is completed, and a RAM as shown in FIG. 1 is completed.

In the DRAM thus formed, the bit line and storage node contact are formed in self-alignment with the gate electrode, and the cell area can be significantly reduced. In addition, when forming contacts, etchback is performed and there is no RIE damage to the sidewalls of the gate electrode, so even if the bit line and storage node contacts are formed in self-alignment with the gate electrode, the insulation It can maintain high voltage resistance and has extremely high reliability.

Furthermore, since no thermal process is required during planarization, the diffusion layer can be formed shallowly.

In the above embodiment, after a contact is opened as shown in FIG. 7, a silicon layer 501 is grown in the contact using a silicon selective epitaxial growth method, as shown in FIG. You can also do this.

After this, steps similar to those shown in FIG. 11 may be performed.

By using the selective epitaxial growth method in this way, the process can be simplified. Furthermore, when a selective growth method of silicon is used, a dense diffusion layer may be formed on the top of the growth layer, and the silicide may be brought into direct contact therewith. In this way, there is no need to form a polycrystalline silicon layer, and it becomes possible to make the layer thinner.

Note that as the Nayabashita insulating film, in addition to a two-layer structure film of a silicon oxide film and a silicon nitride film, a silicon oxide film or a metal oxide film such as tantalum pentoxide (Ta205) may be used.

Further, although a polycrystalline silicon film is used as the first capacitor electrode, it is not necessarily limited to a polycrystalline silicon film, and can be modified as appropriate, such as using a tungsten thin film.

〔Effect of the invention〕

As explained above, according to the method of manufacturing a semiconductor memory device of the present invention, after forming a MOSFET, a resist is formed in a contact formation region, an insulating film is deposited on the upper layer, and an etch-back is performed. Since the contact is formed by planarizing and removing the resist, there is no RIE damage to the sidewalls of the gate electrode, so a bit line contact and/or storage node contact is formed in a self-aligned manner with the gate electrode. This enables miniaturization.

-Also, since RIE is not used when forming contacts,
There is no damage to the insulating film between the gate electrode and the bit line or storage node electrode, resulting in improved dielectric strength and improved yield.

Furthermore, since BPSG is not used, isolation between contacts is improved and yield can be improved.

Further, since planarization by a thermal process is not necessary, it is possible to miniaturize the transistor.

[Brief explanation of drawings]

FIG. 1(a) and FIG. 1(b) are a plan view showing two bits adjacent in the bit line direction of a DRAM having a stacked memory cell structure according to an embodiment of the present invention, and a cross-sectional view taken along line AA'thereof;
2 to 18 are diagrams showing the manufacturing process of this DRAM, FIG. 19 is a diagram showing a part of the manufacturing process of another embodiment of the present invention, and FIG. 20 is a diagram showing a conventional DRAM. be. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Element isolation insulating film, 3... Gate insulating film, 4... Gate electrode, 5...
・N-type diffusion layer, 6, 7.11... interlayer insulating film, 9...
・Polycrystalline silicon film, 10... Silicide film, 12.
...Insulating film, 13...Silicide film (bit line), 1
4.15... Silicon oxide film, 16... First capacitor electrode (storage node electrode), 17... Capacitor insulating film, 18... Second capacitor electrode (plate electrode), 101...・P-type silicon substrate, 102
... Element isolation insulating film, 103... Source/drain region, 104... Gate insulating film, 105... Gate electrode, 106... Insulating film, 107... Polycrystalline silicon film, 108... ... Silicide film, 109... Bit line, 110... Interlayer insulating film, 111... Storage node contact, 112... First capacitor electrode, 113... Capacitor insulating film, 114... Second
capacitor electrode. 5 Figure (a) Figure 4 (b) - C2 Figure 10 Figure 1I Figure 14 Figure 19

Claims (1)

[Claims] This MOS
In a method for manufacturing a semiconductor memory device having a stacked capacitor structure in which a capacitor is stacked on this insulating film such that a first capacitor electrode serving as a storage node electrode of the capacitor is connected to a source or drain region of an FET,
The step of forming a bit line contact and a storage node contact includes forming a resist pattern in the bit line contact and storage node contact formation region, and forming an interlayer insulating film between the resist patterns; and the resist pattern. 1. A method of manufacturing a semiconductor memory device, comprising: a contact forming step of removing and forming a contact.