JPH0365014B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a manufacturing method that is advantageous for a high voltage mesa structure of a semiconductor device.

(Prior Art) A conventional method for manufacturing a high voltage mesa type semiconductor device is shown in Figures 1 to 5 for an example of a P ⁺ N type diode.
This will be explained with reference to the figures.

N-type impurities are diffused at a high concentration on one main surface of an N-type silicon substrate 1 to form an N-type high concentration region 2 for forming an ohmic electrode (FIG. 1). Next, both main surfaces of the substrate are coated with SiO ₂ layers 3a and 3b (second
figure). Of the SiO ₂ layers 3a and 3b, the SiO ₂ layer 3b formed on the main surface opposite to the N-type high concentration region 2 is patterned to define a dicing area, and SiO ₂ is formed on the surface of the dicing area. layer 3c
leave. Then, a doped silicon oxide layer 4 made of low-temperature silicon oxide doped with B is deposited on the opposite main surface (FIG. 3). Next, it is heated to about 1200° C. and doped with B to form a P ⁺ high concentration region 5 (FIG. 4). Next, the electrode layers 6a and 6b are each made of P ⁺
After providing high concentration region 5, N ⁺ high concentration region 2,
Divide into 8 diced chips (5th
figure). Note that 7 is a SiO ₂ layer for surface protection.

(Problems to be Solved by the Invention) According to the conventional manufacturing method described above, the substrate deteriorates due to the influence of positive charges caused by contaminants, moisture, impurities present in the protective film, etc. that enter from the outside during use. N
Electrons accumulate near the main surface on the side, causing electric field concentration near the junction. On the other hand, there is a drawback that hole depletion tends to occur near the main surface on the P side, making it easier for surface leakage current to flow.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that improves the drawbacks of the prior art described above.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes P ⁺ N
In manufacturing a mesa-type silicon semiconductor device having a junction, a step of depositing an SiN layer on the main surface of an N-type semiconductor substrate via a B diffusion source, and a step of laminating and depositing a resist pattern layer on the SiN layer. , the Ga diffusion region by ion implantation is defined by the resist pattern layer, and B and Ga are simultaneously diffused, and B is also diffused overlappingly in the Ga diffusion region so that the surface concentration of Ga is lower than that of B, and the diffusion is performed. A method for manufacturing a semiconductor device including a step of forming Ga to be deeper than B.

(Function) According to the method for manufacturing a semiconductor device according to the present invention,
Because the concentration on the P side of the junction at the periphery of the semiconductor element is low, electric field concentration is less likely to occur than at the center, and the surface leakage path on the P side is also long because the depth from the surface to the junction is deep. Therefore, the leakage path becomes longer, and the leakage current can also be reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In the manufacture of an example of a P ⁺ N type diode, N ⁺ is diffused from one main surface, oxidized to form a dicing pattern, and a B-doped silicon oxide layer is deposited. Since this is the same as the explanation up to Figure 3, it will be omitted. Next, the doped silicon oxide layer 4 is laminated.
A SiN layer 11 is applied, as well as a photoresist layer 12a (FIG. 6). Next, after removing the photoresist layer deposited on the dicing area, Ga ions are implanted (FIG. 7). By this ion implantation, Ga ions are implanted into the substrate in the dicing area, and into the photoresist layer 12b in areas other than the dicing area. Then, heating is applied to bond B of the doped silicon oxide layer 4 and the dicing area.
Diffuse Ga at the same time. P ⁺ at the end of the above diffusion
In the high concentration region 15, diffusion conditions are set such that the diffusion impurity concentration of Ga is lower than that of B at the surface portion, and the diffusion depth of Ga is deeper than that of B (FIG. 7).
Furthermore, after electrode layers 6a and 6b are provided in the P ⁺ high concentration region 15 and the N ⁺ high concentration region 2, respectively, dicing is performed to divide the chips into chips 18 (FIG. 8).

In the device chip formed as described above, unlike the conventional planar junction mesa type, the concentration on the P side of the junction at the periphery is lower, so that electric field concentration is less likely to occur than at the center, and the junction surface from the surface Because the depth is deep, the surface leakage path on the P side is also longer, so the leakage current can be reduced.

It goes without saying that the present invention is not limited to the diodes of the embodiments, but can also be applied to NPN type semiconductor devices and the like.

〔Effect of the invention〕

According to the present invention, SiN layer deposition is added to the conventional method.
It has the remarkable advantage that a device with high breakdown voltage and excellent reliability can be obtained simply by adding a Ga ion implantation process. Furthermore, the resist block used in this method is easily formed because it can be used by inverting the same mask as the dicing pattern.

Next, the device thus obtained is more resistant to electric field concentration on the surface and can suppress surface leakage current to a lower level than conventional planar junction mesa-type devices. This will be further explained with reference to FIGS. 9 and 10. FIG. 9 shows the impurity profile at the center of the device, and FIG. 10 shows the impurity profile at the periphery of the device. In the figure, X is the distance from the substrate surface, N _S1 is the concentration profile of impurity B, N _S2
is the concentration profile of impurity Ga.

As is clear from the above, in the peripheral area, the concentration on the P side near the junction is lower than that in the central area, so the depletion layer (the area shown with dashed lines) expands to the P side, and thus The peak electric field is smaller than that at the center. Also, since the distance from the surface to the edge of the depletion layer becomes longer, it is advantageous for leakage current.
Reliability against charge contamination is also significantly improved compared to the conventional method.

[Brief explanation of drawings]

1 to 3 are cross-sectional views of elements for explaining a method of manufacturing a semiconductor device, and FIGS. 4 and 5 are sectional views of a conventional semiconductor device manufacturing method including FIGS. 1 to 3. 6 to 8 are cross-sectional views of the device for explaining the method, and FIGS. 6 to 8 are cross-sectional views of the device, including FIGS. The cross-sectional views, FIGS. 9 and 10, are all diagrams showing the impurity profile of the device, with FIG. 9 showing the central portion of the device and FIG. 10 showing the peripheral portion of the device. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... N-type high concentration region, 3a, 3b, 3c... SiO ₂ layer, 4... Doped silicon oxide layer, 5, 15... P ⁺ high concentration region, 11... SiN layer, 12a, 12b...photoresist layer.

Claims (1)

[Claims] 1. In manufacturing a mesa-type silicon semiconductor device having a P ⁺ N junction, a step of depositing a SiN layer on the main surface of an N-type semiconductor substrate via a B diffusion source;
A process of laminating and depositing a resist pattern layer on the SiN layer, defining a Ga diffusion region by ion implantation with the resist pattern layer, and simultaneously diffusing B and Ga, and overlappingly diffusing B in the Ga diffusion region. A method for manufacturing a semiconductor device including a step of making the surface concentration of Ga lower than that of B and making the diffusion depth of Ga deeper than that of B.