JPH0365032B2 - - Google Patents

Info

Publication number
JPH0365032B2
JPH0365032B2 JP58220555A JP22055583A JPH0365032B2 JP H0365032 B2 JPH0365032 B2 JP H0365032B2 JP 58220555 A JP58220555 A JP 58220555A JP 22055583 A JP22055583 A JP 22055583A JP H0365032 B2 JPH0365032 B2 JP H0365032B2
Authority
JP
Japan
Prior art keywords
thick film
conductor
thick
layer
multilayer circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58220555A
Other languages
Japanese (ja)
Other versions
JPS60113493A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP22055583A priority Critical patent/JPS60113493A/en
Publication of JPS60113493A publication Critical patent/JPS60113493A/en
Publication of JPH0365032B2 publication Critical patent/JPH0365032B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

発明の技術分野 本発明は厚膜多層回路基板の製造方法の改良に
関するものである。 技術の背景 以下サーマルヘツドに例をとり説明する。サー
マルヘツドは耐熱性基板の上に多数の発熱低抗体
をもち、所望の低抗体に電気的パルスを印加して
発熱させ、感熱記録紙に印字を行なうものであ
り、その製造方法の違いにより薄膜形と厚膜形と
がある。薄膜形サーマルヘツドは印字品質が優れ
ているが高価であり、厚膜形サーマルヘツドは印
字品質は劣るか安価であるという特徴がある。そ
こで両者を組合わせて印字品質が優れ、且つ安価
にできるサーマルヘツドが提案されている。 従来技術と問題点 第1図は薄膜形と厚膜形を組合わせたサーマル
ヘツドを説明するための図である。これはアルミ
ナ等の耐熱性基板1の上に断熱グレーズ層2、薄
膜低抗体3、薄膜導体4、保護膜5よりなる薄膜
ヘツド部Aと、1層目導体6及び誘電体層7、2
層目導体8及び誘電体層9、3層目導体10及び
誘電体層11よりなる厚膜多層回路部Bとで構成
され、薄膜導体4と厚膜導体8がC部で接続され
ている。そして発熱低抗体を駆動するICドライ
バー12が厚膜多層回路の2層目の導体8の上に
樹脂13で接着され、3層目の導体10にワイヤ
ボンデイングされている。 このようなサーマルヘツドにおいて、その厚膜
導体は従来スクリーン印刷のみでパターニングさ
れるが、その場合の最小線幅は100μm以上とさ
れている。従つてドツト密度が高くなり線幅が
100μm以下になるとスクリーン印刷法では形成
困難となる。そのためには厚膜導体を全面に形成
した後、フオトレジスト塗布、露光、エツチング
というフオトリソグラフイーの手法を用いてパタ
ーンの微細化及び高精度化をはかることができる
とされていた。ところが実際には形成される厚膜
導体の表面粗度が大きく(2〜5μm程度)、その
ためレジストが均一に形成されなかつたり、エツ
チング時のバラツキが大きく100μm以下のパタ
ーニングは事実上困難であつた。 発明の目的 本発明は上記従来の問題点に鑑み、厚膜導体を
フオトリソグラフイー法でパターニングできる厚
膜多層回路基板の製造方法を提供することを目的
とするものである。 発明の構成 そしてこの目的は本発明によれば、耐熱性基板
上もしくは誘電体層上の全面に厚膜導体を形成し
た後に、フオトリソグラフイーを用いて導体パタ
ーンを形成する厚膜多層回路基板の製造方法にお
いて、フオトリソグラフイー工程の前に厚膜導体
の表面の凹凸を平坦にして粗度を小さくするため
の機械的な研磨を行うことを特徴とする厚膜回路
基板の製造方法を提供することによつて達成され
る。 発明の実施例 以下、本発明を実施例により詳述する。 試料No.1として97%アルミナ基板上に銅厚膜ペ
ーストを全面に印刷し、乾燥後N2ガス中、900℃
で焼成し約10μm厚の銅厚膜層を形成したもの、
及び試料No.2として97%アルミナ基板上全面に多
層用厚膜誘電体層を形成し、その上に試料No.1と
同様にして銅厚膜層を形成したものを調整し、こ
れらをプリント板用オシレーシヨン研磨機にて
#300→#600→#1000→#2000の研磨ロールを使
用してこの順に研磨を行ない、研磨前後の表面粗
さを測定した。その結果は第1表の如くになつ
た。
TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a thick film multilayer circuit board. Background of the Technology The following is an explanation using a thermal head as an example. A thermal head has a large number of heat-generating low antibodies on a heat-resistant substrate, and prints on heat-sensitive recording paper by applying electrical pulses to the desired low-antibodies to generate heat. There are two types: thick-film type and thick-film type. Thin-film thermal heads have excellent printing quality but are expensive, while thick-film thermal heads have poor printing quality or are inexpensive. Therefore, a thermal head has been proposed that combines the two methods and provides excellent printing quality at a low cost. Prior Art and Problems FIG. 1 is a diagram for explaining a thermal head that combines a thin film type and a thick film type. This consists of a heat-resistant substrate 1 made of alumina or the like, and a thin film head part A consisting of a heat insulating glaze layer 2, a thin film low antibody 3, a thin film conductor 4, and a protective film 5, a first layer conductor 6, and dielectric layers 7, 2.
It is composed of a thick film multilayer circuit section B consisting of a layer conductor 8, a dielectric layer 9, a third layer conductor 10, and a dielectric layer 11, and the thin film conductor 4 and the thick film conductor 8 are connected at a section C. An IC driver 12 for driving the heat-generating low antibody is bonded with resin 13 onto the second layer conductor 8 of the thick film multilayer circuit, and wire bonded to the third layer conductor 10. In such a thermal head, the thick film conductor is conventionally patterned only by screen printing, but the minimum line width in this case is set to be 100 μm or more. Therefore, the dot density increases and the line width increases.
When the thickness is less than 100 μm, it becomes difficult to form using the screen printing method. To this end, it was believed that after forming a thick film conductor over the entire surface, it would be possible to make the pattern finer and more precise by using photolithography techniques, including photoresist coating, exposure, and etching. However, in reality, the surface roughness of the thick film conductor that is formed is large (approximately 2 to 5 μm), and as a result, the resist is not formed uniformly, and there are large variations during etching, making it virtually difficult to pattern with a thickness of 100 μm or less. . OBJECTS OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a method for manufacturing a thick film multilayer circuit board in which thick film conductors can be patterned by photolithography. According to the present invention, this object is to provide a thick film multilayer circuit board in which a thick film conductor is formed on the entire surface of a heat-resistant substrate or a dielectric layer, and then a conductor pattern is formed using photolithography. Provided is a method for manufacturing a thick film circuit board, characterized in that, before the photolithography process, mechanical polishing is performed to flatten and reduce roughness on the surface of the thick film conductor. This is achieved by EXAMPLES OF THE INVENTION The present invention will now be described in detail with reference to examples. As sample No. 1, a copper thick film paste was printed on the entire surface of a 97% alumina substrate, and after drying, it was heated at 900℃ in N2 gas.
A thick copper film layer of about 10 μm is formed by firing with
Sample No. 2 was prepared by forming a multilayer thick dielectric layer on the entire surface of a 97% alumina substrate, and then forming a copper thick film layer on top of it in the same manner as Sample No. 1, and printing these. Polishing was performed in this order using an oscillation polishing machine for plates using polishing rolls of #300 → #600 → #1000 → #2000, and the surface roughness before and after polishing was measured. The results were as shown in Table 1.

【表】 これらの試料について、パターン幅が10、20、
40、80、160、320μmの6種のテストパターンを
用い、(長さ100mm、ギヤツプはパターン幅と同
一、パターン数は100本)フオトリソグラフイー
によりパターニングを行なつてパターン欠陥をシ
ヨート及び断線の点数によつて評価した。各パタ
ーン1000本分につき評価した結果を第2表及び第
3表に示す。なお第2表は試料No.1(97%アルミ
ナ基板上の銅厚膜層をパターニングしたもの)、
第3表は試料No.2(厚膜誘電体層上の銅厚膜層を
パターニングしたもの)評価結果である。表中※
印はシヨートし且つ断線しているために不良率が
100%以上となつている。
[Table] For these samples, the pattern width is 10, 20,
Using six types of test patterns of 40, 80, 160, and 320 μm (length 100 mm, gap equal to pattern width, number of patterns 100), patterning was performed using photolithography to shoot pattern defects and disconnections. Evaluation was based on points. Tables 2 and 3 show the results of evaluating 1000 pieces of each pattern. Table 2 shows sample No. 1 (patterned thick copper film layer on a 97% alumina substrate),
Table 3 shows the evaluation results of sample No. 2 (patterned thick copper film layer on a thick film dielectric layer). In the table*
The defective rate is high because the mark is shot and disconnected.
It is over 100%.

【表】【table】

【表】 第2表及び第3表より試料No.1、No.2共研磨を
行なわないものに比して研磨を行なつたものは欠
陥数が約1桁〜2桁減少することがわかる。また
100mmという長いパターンにもかかわらず(実際
は高密度のまま100mmも引廻すことは少ない)パ
ターン幅40μ程度のパターンまで使用可能となる
ことがわかる。 以上説明した実施例では、プリント基板用オシ
レーシヨン研磨機を使用して厚膜導体表面を研磨
したが、他の研磨方法、例えばセラミツク粉末を
水中に懸濁させた液を導体表面に吹きつけるなど
の装置を使用してもまつたく同等の結果が得られ
る。また厚膜導体は銅に限らず金、銀、銀−パラ
ジウムなどのような厚膜導体材料についても同等
な結果が得られることは勿論である。 発明の効果 以上、詳細に説明したように本発明の厚膜多層
回路基板の製造方法は、厚膜導体表面を研磨し表
面粗度を小さくすることにより厚膜導体をフオト
リソグラフイー法により高密度なパターニングを
可能にするといつた効果大なるものである。
[Table] From Tables 2 and 3, it can be seen that the number of defects in samples No. 1 and No. 2 that were polished was reduced by about one to two orders of magnitude compared to those that were not co-polished. . Also
Although the pattern is as long as 100 mm (in reality, it is rare to extend it even 100 mm with high density), it is possible to use patterns with a pattern width of about 40 μm. In the example described above, the surface of the thick film conductor was polished using an oscillation polisher for printed circuit boards, but other polishing methods, such as spraying a solution of ceramic powder suspended in water, onto the conductor surface may also be used. Equivalent results can be obtained using the same device. Furthermore, it goes without saying that the thick film conductor is not limited to copper, and equivalent results can be obtained with thick film conductor materials such as gold, silver, silver-palladium, and the like. Effects of the Invention As described in detail above, the method for manufacturing a thick film multilayer circuit board of the present invention is to polish the surface of the thick film conductor to reduce the surface roughness, and then to increase the density of the thick film conductor using the photolithography method. This has a great effect in making it possible to create a pattern.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のサーマルヘツドを説明するため
の断面図である。 図面において、Aは薄膜ヘツド部、Bは厚膜多
層回路部をそれぞれ示す。
FIG. 1 is a sectional view for explaining a conventional thermal head. In the drawings, A indicates a thin film head section, and B indicates a thick film multilayer circuit section.

Claims (1)

【特許請求の範囲】 1 耐熱性基板上もしくは誘電体層上の全面に厚
膜導体層を形成した後に、フオトリソグラフイー
を用いて導体パターンを形成する厚膜多層回路基
板の製造方法において、 フオトリソグラフイー工程の前に厚膜導体の表
面の凹凸を平坦にして粗度を小さくするための機
械的な研磨を行うことを特徴とする厚膜多層回路
基板の製造方法。
[Scope of Claims] 1. A method for manufacturing a thick film multilayer circuit board in which a thick film conductor layer is formed on the entire surface of a heat-resistant substrate or a dielectric layer, and then a conductor pattern is formed using photolithography. A method for manufacturing a thick film multilayer circuit board, characterized in that, before a lithography process, mechanical polishing is performed to flatten and reduce roughness on the surface of a thick film conductor.
JP22055583A 1983-11-25 1983-11-25 Method of producing thick film multialyer circuit board Granted JPS60113493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22055583A JPS60113493A (en) 1983-11-25 1983-11-25 Method of producing thick film multialyer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22055583A JPS60113493A (en) 1983-11-25 1983-11-25 Method of producing thick film multialyer circuit board

Publications (2)

Publication Number Publication Date
JPS60113493A JPS60113493A (en) 1985-06-19
JPH0365032B2 true JPH0365032B2 (en) 1991-10-09

Family

ID=16752826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22055583A Granted JPS60113493A (en) 1983-11-25 1983-11-25 Method of producing thick film multialyer circuit board

Country Status (1)

Country Link
JP (1) JPS60113493A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5064767A (en) * 1973-10-12 1975-06-02

Also Published As

Publication number Publication date
JPS60113493A (en) 1985-06-19

Similar Documents

Publication Publication Date Title
US3729819A (en) Method and device for fabricating printed wiring or the like
US5317342A (en) High-density print head
US4897676A (en) High-density circuit and method of its manufacture
JPH0365032B2 (en)
JPS62122102A (en) Thermal recording head and its manufacturing method
US4632845A (en) Process for the fabrication of thermal printing boards in multilayer thick-film technology
US5488394A (en) Print head and method of making same
JPS6334157A (en) Method of forming thermal head conductor
JP3136682B2 (en) Method for manufacturing multilayer wiring board
JPH03219967A (en) Thermal head
JP3129912B2 (en) Manufacturing method of thermal head
JP2002246206A (en) Chip resistor and its manufacturing method
JPS61134099A (en) Manufacture of multilayer thick film ic
JPH0517864B2 (en)
JPH05318799A (en) Thermal head
JPS59106184A (en) Method of forming patter layer of electronic circuit board
JPS63192294A (en) Manufacture of precision electric interconnection
JPS6231515B2 (en)
JPS60227493A (en) Method of forming thick film pattern
JPH0548269A (en) Manufacture of multilayer circuit board
JPH0480050A (en) Thermal head and its manufacture
JPS60113494A (en) Method of forming fine pattern in stepwise portion
JPS5922675B2 (en) Method of manufacturing thermal head
JPS59134896A (en) Method of producing multilayer circuit board
JPS60135930A (en) Structure of filmy photosensitive material