JPH0365828A - reset device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reset device used in a radio paging receiver or the like.

BACKGROUND OF THE INVENTION FIG. 3 shows a conventional reset device used in a radio paging receiver or the like.

In FIG. 3, 1 is a battery for supplying power to system 2, 3 is a power switch for turning on and off the power from battery 1 to system 2, and R is a power switch for connecting switch 1 and system 2. The resistor C connected between the reset signal input terminals is a capacitor whose one end is connected between the resistor R and the reset signal input terminal of the system 2, and whose other end is grounded.

Next, the operation of the above conventional example will be explained.

In FIG. 3, when switch 3 is turned on, power from battery 1 is supplied to system 2, and a time constant circuit consisting of resistor R and capacitor C allows the current from battery 1 to flow for a predetermined period of time. Later, it becomes high level and system 2 is reset.

Therefore, according to the above conventional example, when the power of the battery 1 is turned on to the system 2, the system 2 can be reset by the current from the battery 1 and the time constant circuit.

Problems to be Solved by the Invention However, in the conventional reset circuit described above, since the reset is performed using a single power supply system (battery 1), there is a circuit that directly uses the output voltage of battery 1 as a power source, and a circuit that uses the output voltage of battery 1 as a power source. If there is a circuit that boosts the voltage and uses it as a power source, if the voltage of the battery 1 is momentarily interrupted or the boosted voltage drops due to overload, the entire system 2 cannot be reset, and the system 2
There is a problem that it goes out of control.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a reset device that can reliably output a reset signal regardless of voltage fluctuations in different power supply systems.

Means for Solving the Problems In order to achieve the above object, the present invention provides a circuit for boosting the output voltage of a battery, a circuit for detecting a drop in this boosted voltage, an output signal of a time constant circuit, and a circuit for detecting the drop in the boosted voltage. It is equipped with a circuit that outputs a reset signal based on a logical sum signal of signals.

According to the above-mentioned structure, when there is a circuit that directly uses the output voltage of the battery as a power source and a circuit that uses the output voltage of the battery as a power source by boosting the voltage, both circuits can be reset.
Therefore, regardless of voltage fluctuations in different power supply systems,
A reset signal can be reliably output.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
1 is a block diagram showing one embodiment of a reset device according to the present invention, and FIG. 2 is a timing chart showing main signals of the reset device of FIG. 1.

In Figure 1, 11 is a battery that serves as a power source, and 12 is a
The DC/DCC/equation controller 13 that boosts the voltage (signal S) of the battery 1 is a central processing unit (CPU) that operates using the voltage (signal S2) boosted by the DC/DCC/equation controller 12 as a power source. ), 14 is DC/DCC/formula-ta 12
The voltage detector 14 is a voltage detector that detects a decrease in the voltage (signal SR) boosted by the CPU 13.
A random access memory (RAM) inside detects a voltage that cannot hold data, and outputs the detection signal Ss to one inverting input terminal of the OR circuit 15.

Here, a circuit whose power source is the voltage boosted by the DC/DCC/equation converter 12 is referred to as a CPU side power supply system.

R is a resistor connected between the battery 1 and the other input terminal of the OR circuit IS; one end of C is connected between the battery 11 and the other inverting input terminal of the OR circuit 15; The capacitor Go, which is grounded, is a backup capacitor in case the voltage of the battery 11 is momentarily cut off.

The output terminal of the OR circuit 15 is connected to the reset signal input terminal of the decoder 16, and the decoder 16 operates using the voltage of the battery 11 as a power source, and also resets the CPU 13 by the reset signal from the OR circuit 15.

Here, a circuit whose power source is the voltage of the battery 11 is referred to as a decoder side power supply system.

Next, the operation of the above embodiment will be explained with reference to FIG.

First, when the battery 1 is set, the CPU 13 is reset by the output signal Ss of the OR circuit 15 (state a),
Next, the output signal S4 (decoder side power supply system) of the time constant circuit (R, C) and the output signal S, (CP
When the U-side power supply system) rises together, the output signal S5 of the logic and sum circuit 15 becomes low level.

In this state, if the voltage of the battery 11 is momentarily interrupted, the time constant circuit (R, C) prevents the output signal S4 from becoming completely low level, so the CPU 13 is not reset (state b).

In addition, when the voltage (signal S2) boosted by the DC/DCC/equation converter 12 momentarily drops due to overload and the detection signal S3 of the voltage detector 14 becomes low level, the output signal of the OR diagram ¥115 s6 becomes high level, CPU
13 is reset (state C).

Furthermore, when the voltage of the battery 1 decreases, the voltage of the decoder side power supply system decreases, and only the output signal S4 of the time constant circuit (R, C) becomes low level, the CPU 13 is reset (
Condition d).

Therefore, according to the embodiment described above, in the case of a system that operates using the voltages of the CPU-side electric thread and the decoder-side power supply system, it is possible to reliably reset even if the respective voltages fall below a predetermined level.

As described in detail, the present invention includes a circuit that boosts the output voltage of a battery, a circuit that detects a drop in this boosted voltage, and an OR signal of an output signal of a time constant circuit and this detection signal. Since it is equipped with a circuit that outputs a reset signal, if there is a circuit that uses the battery's output voltage directly as a power source and a circuit that uses the battery's output voltage as a power source by boosting it, both circuits can be reset. Therefore, the reset signal can be reliably output regardless of voltage fluctuations in different power supply systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a reset device according to the present invention, FIG. 2 is a timing chart showing main signals of the reset device in FIG. 1, and FIG. 3 is a diagram showing a conventional reset device. It is a block diagram. 11...Battery, 12...DC/DC converter, 1
3...Central processing unit (CPU), 149.・Voltage detector, 15...OR circuit, 16...decoder, R・
...Resistance, C...Capacitor.

Claims (1)

[Claims] a time constant circuit connected to a battery, a circuit for boosting the output voltage of the battery, a circuit for detecting a drop in the voltage boosted by the booster circuit, and a detection of an output signal of the time constant circuit and the detection circuit. A reset device comprising a circuit that outputs a reset signal based on an OR signal of signals.