JPH0365894B2 - - Google Patents

Info

Publication number
JPH0365894B2
JPH0365894B2 JP59228507A JP22850784A JPH0365894B2 JP H0365894 B2 JPH0365894 B2 JP H0365894B2 JP 59228507 A JP59228507 A JP 59228507A JP 22850784 A JP22850784 A JP 22850784A JP H0365894 B2 JPH0365894 B2 JP H0365894B2
Authority
JP
Japan
Prior art keywords
bonding
wire
pads
wire bonding
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59228507A
Other languages
Japanese (ja)
Other versions
JPS61105851A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP59228507A priority Critical patent/JPS61105851A/en
Publication of JPS61105851A publication Critical patent/JPS61105851A/en
Publication of JPH0365894B2 publication Critical patent/JPH0365894B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07521Aligning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07553Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/537Multiple bond wires having different shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/944Dispositions of multiple bond pads
    • H10W72/9445Top-view layouts, e.g. mirror arrays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To unnecessitate or sharply reduce the correction by hand works by a method wherein the first bonding is performed on the column located outside the boundary line of the first and the second regions, and the second bonding is performed on the column located inside the boundary line. CONSTITUTION:The first ball bonding is performed on the wire pads 4a and 5a of the column located outside the boundary line 9 of substrates 2 and 3, and the second wedge bonding is performed on the wire pads 4b and 5b of the column located inside the boundary line 9. Consequently, as bonding wires 6a and 6b do not come in contact with each other because they are separated in upward direction from the pads 4b and 5b of the inside column on the side they are connected to the pads 4a and 4b of the outside column, the wires 6a and 6b can be made short in length. On the other hand, the wires 6a and 6b are moved in close to the surface of the substrates 2 and 3 on the side where they are connected to the pads 4b and 5b of the inside column, but as there is no other pad in the vicinity of them, they intersect only at the point P located in the neighborhood of the boundary line 9. Accordingly, the wire which is used to correct the contact of the wires and the pads and the correcting work are unnecessitated, or those processes can be reduced substantially.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は千鳥状ワイヤボンデイングを用いたワ
イヤボンデイング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a wire bonding method using staggered wire bonding.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

異なる領域にある配線パターン間や、配線パタ
ーンとICチツプ等のチツプ部品の入出力用ワイ
ヤボンデイングパツドとの間を接続する場合、ワ
イヤボンデイング方法が多く使用されている。近
年、基板上の配線密度およびICチツプの集積度
の増大に伴いワイヤボンデイングもより高密度化
が要求されるようになつているが、高密度化に適
したワイヤボンデイング方法の一つに千鳥状ワイ
ヤボンデイングがある。
Wire bonding is often used to connect wiring patterns in different areas or to connect wiring patterns and input/output wire bonding pads of chip components such as IC chips. In recent years, with the increase in wiring density on substrates and the degree of integration of IC chips, higher density wire bonding has been required, and one of the wire bonding methods suitable for higher density is staggered wire bonding. There is wire bonding.

千鳥状ワイヤボンデイングとは、ボンデイング
位置を千鳥状に配列することによつて、隣接した
ボンデイング位置間の距離を配線パターン間の間
隔より大きくして、高密度ワイヤボンデイングを
可能とした技術である。
Staggered wire bonding is a technique that enables high-density wire bonding by arranging bonding positions in a staggered manner so that the distance between adjacent bonding positions is greater than the interval between wiring patterns.

第4図は従来技術による千鳥状ワイヤボンデイ
ングの具体例を示すもので、第1の領域上の2列
のボンデイングパツド4a,4bに対しボンデイ
ングワイヤ6a,6bの一端をフアーストボンデ
イングし、第2の領域上のワイヤボンデイングパ
ツド5a,5bに対しボンデイングワイヤ6a,
6bの他端をセカンドボンデイングしている。こ
こで、一般にフアーストボンデイングはボンデイ
ングワイヤ先端部に形成させたボールをボンデイ
ング位置に押付けてボンデイングを行なう、いわ
ゆるボールボンデイングが使用され、セカンドボ
ンデイングはボンデイングワイヤの途中の部分を
ボンデイング位置に押付けることによりウエツジ
状ボンドを形成させてボンデイングを行なつた後
ワイヤを切断する、いわゆるウエツジボンデイン
グが使用される。
FIG. 4 shows a specific example of staggered wire bonding according to the prior art, in which one ends of bonding wires 6a, 6b are first bonded to two rows of bonding pads 4a, 4b on a first region, and bonding wires 6a,
The other end of 6b is second bonded. Generally, first bonding involves pressing a ball formed at the tip of the bonding wire to the bonding position, so-called ball bonding, and second bonding involves pressing the middle part of the bonding wire to the bonding position. So-called wedge bonding is used, in which a wedge-shaped bond is formed and the wire is cut after bonding is performed.

しかしながら、従来の千鳥状ボンデイングでは
ウエツジ状ボンデイングであるセカンドボンデイ
ングが共に同じ領域(第2の領域)上のワイヤボ
ンデイングパツド5a,5bに対して施されてい
るため、ボンデイングワイヤが基板面に平行に近
い状態となり易いというウエツジボンデイングの
性質上、第2の領域上の外側の列のワイヤボンデ
イングパツド5aに接続されたボンデイングワイ
ヤ6aが、内側の列のワイヤボンデイングパツド
5bに接触し易いという問題があつた。この問題
を避けるため、従来ではセカンドボンデイングが
施されるワイヤボンデイングパツド5a,5b間
の距離を十分に話す必要があり、ボンデイングワ
イヤのワイヤ長の増大を招いている。ボンデイン
グワイヤには一般に金ワイヤが使用されるから、
ワイヤ長の増大はコスト面、省資源の観点から大
きな問題となる。
However, in conventional staggered bonding, second bonding, which is wedge-shaped bonding, is performed on wire bonding pads 5a and 5b on the same area (second area), so bonding wires are parallel to the substrate surface. Due to the nature of wedge bonding, which tends to be in a state close to There was a problem. In order to avoid this problem, conventionally it has been necessary to provide a sufficient distance between the wire bonding pads 5a and 5b on which second bonding is performed, resulting in an increase in the wire length of the bonding wire. Since gold wire is generally used for bonding wire,
The increase in wire length poses a major problem from the viewpoint of cost and resource conservation.

また、従来の千鳥状ワイヤボンデイングでは、
図に示すように隣接するボンデイングワイヤ6
a,6bが正面から見てP1,P2の2個所で交叉
した形となつているため、これらの交叉点P1
P2でのボンデイングワイヤ6a,6b同士の接
触という問題もある。さらに、第4図においてボ
ンデイングワイヤ6a,6bのボンデイングパツ
ド5a,5bに対するセカンドボンデイングの位
置を入替えて、ワイヤ6aをパツド5bに、ワイ
ヤ6bをパツド5aにそれぞれ接続したとして
も、ボンデイングワイヤ6a,6bが平行に近い
状態で存在する長さが増えるので、同様の問題が
生じる。このようなことから、従来ではワイヤボ
ンデイング工程の後、ワイヤが多数あり、特に高
密度になつた場合には、ほとんど全てのワイヤ6
a,6bについてその位置を手作業により修正す
る必要があつた。
In addition, with conventional staggered wire bonding,
Adjacent bonding wire 6 as shown in the figure
Since a and 6b intersect at two points P 1 and P 2 when viewed from the front, these intersection points P 1 ,
There is also the problem of contact between the bonding wires 6a and 6b at P2 . Furthermore, even if the second bonding positions of the bonding wires 6a and 6b with respect to the bonding pads 5a and 5b are swapped in FIG. 4 and the wire 6a is connected to the pad 5b and the wire 6b is connected to the pad 5a, the bonding wires 6a, A similar problem arises as the length over which 6b exists in a near-parallel state increases. For this reason, conventionally, after the wire bonding process, there are a large number of wires, and when the density is particularly high, almost all the wires are
It was necessary to manually correct the positions of a and 6b.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、第1の領域上にある複数の配
線パターンまたはそれらに接続されたボンデイン
グパツドあるいはチツプ部品のボンデイングパツ
ドと、第2の領域上にある複数の配線パターンま
たはそれらに接続されたボンデイングパツドある
いはチツプ部品のボンデイングパツドとの間を千
鳥状ワイヤボンデイングにより接続するに際し、
ボンデイングワイヤのワイヤ長を必要以上に大き
くとることなくボンデイングワイヤと近傍の配線
パターンやボンデイングパツドとの接触を防止す
るとともに、ボンデイングワイヤ同士の接触も少
なく、ボンデイング工程後の手作業による修正を
不要もしくは大幅に少なくできるワイヤボンデイ
ング方法を提供することにある。
An object of the present invention is to connect a plurality of wiring patterns on a first region or bonding pads connected to them or a bonding pad of a chip component, and a plurality of wiring patterns on a second region or a bonding pad connected to them. When connecting bonding pads that have been bonded or bonding pads of chip components using staggered wire bonding,
This prevents the bonding wire from coming into contact with nearby wiring patterns or bonding pads without making the wire length longer than necessary, and also reduces contact between the bonding wires, eliminating the need for manual corrections after the bonding process. Alternatively, it is an object of the present invention to provide a wire bonding method that can significantly reduce the amount of wire bonding.

〔発明の概要〕[Summary of the invention]

本発明によるワイヤボンデンイング方法は上記
目的を達成するため、第1および第2の領域上に
おける各2列のワイヤボンデイング位置のうち、
各領域の境界線に対し外側の列についてフアース
トボンデイングを施し、内側の列についてセカン
ドボンデイングを施すことを特徴とする。ここ
で、フアーストボンデイングおよびセカンドボン
デイングは従来と同様、それぞれボールボンデイ
ングおよびウエツジボンデイングが適当である
が、フアーストボンデイングに関しては必ずしも
ボールボンデイングでなく、ウエツジボンデイン
グであつてもよい。
In order to achieve the above object, the wire bonding method according to the present invention has two rows of wire bonding positions on the first and second regions.
It is characterized in that first bonding is performed on the outer rows of the boundary line of each region, and second bonding is performed on the inner rows. Here, the first bonding and the second bonding are preferably ball bonding and wedge bonding, respectively, as in the past, but the first bonding is not necessarily ball bonding and may be wedge bonding.

〔発明の効果〕〔Effect of the invention〕

本発明によるワイヤボンデイング方法では、ボ
ンデイングワイヤの角度が基板面に対して平行に
近い状態になり易いウエツジボンデイングによる
セカンドボンデイングを内側の列のワイヤボンデ
イング位置に施し、フアーストボンデイングを外
側の列のワイヤボンデイング位置に施すことによ
り、外側の列のワイヤボンデイング位置に接続さ
れたボンデイングワイヤが内側の列のワイヤボン
デイング位置に接触するという従来技術の問題は
皆無となる。従つて、外側の列のワイヤボンデイ
ング位置と、内側の列のワイヤボンデイング位置
との間隔を最小限に小さくでき、ボンデイングワ
イヤのワイヤ長を短くすることができる。また、
このことは配線基板やチツプ部品上におけるワイ
ヤボンデイングパツド形成のための占有面積の減
少にも寄与する。
In the wire bonding method according to the present invention, second bonding by wedge bonding, in which the angle of the bonding wire tends to be nearly parallel to the substrate surface, is performed at the wire bonding position in the inner row, and first bonding is performed at the wire bonding position in the outer row. By applying it to the wire bonding locations, the problem of the prior art where bonding wires connected to the outer row of wire bonding locations contact the inner row of wire bonding locations is eliminated. Therefore, the distance between the wire bonding positions in the outer row and the wire bonding positions in the inner row can be minimized, and the wire length of the bonding wire can be shortened. Also,
This also contributes to reducing the area occupied for forming wire bonding pads on wiring boards and chip components.

さらに、本発明では隣接するボンデイングワイ
ヤが第1および第2の領域の境界線上でのみ交叉
する形となり、それ以外の所では十分に離れるの
で、ワイヤ同士の接触という問題もほとんどなく
なり、繁雑な手作業による修正を全く不要とする
か、もしくは極く少なくすることが可能である。
Furthermore, in the present invention, adjacent bonding wires intersect only on the boundary line between the first and second regions, and are sufficiently separated elsewhere, so there is almost no problem of wires contacting each other, and complicated procedures are avoided. It is possible to eliminate or minimize the need for manual modifications.

〔発明の実施例〕[Embodiments of the invention]

第1図a,bは本発明の一実施例に係るワイヤ
ボンデイング方法を説明するための平面図および
断面図である。
FIGS. 1a and 1b are a plan view and a sectional view for explaining a wire bonding method according to an embodiment of the present invention.

図において、支持用基板1上に第1の領域であ
る第1の基板2と、第2の領域である第2の基板
3が固定され、これら第1および第2の基板2,
3上にそれぞれ2列のワイヤボンデイングパツド
4a,4bおよび5a,5bが千鳥状に配列され
て形成されている。また、各ワイヤボンデイング
パツド4a,4b,5a,5bには、配線パター
ン7a,7b,8a,8bの一端が接続されてい
る。配線パターン7a,7b,8a,8bの他端
には、例えば同様にワイヤボンデイングパツドが
形成され、それらに図示しないチツプ部品等に接
続されるものとする。
In the figure, a first substrate 2, which is a first region, and a second substrate 3, which is a second region, are fixed on a support substrate 1, and these first and second substrates 2,
3, two rows of wire bonding pads 4a, 4b and 5a, 5b are arranged in a staggered manner. Further, one end of the wiring patterns 7a, 7b, 8a, 8b is connected to each wire bonding pad 4a, 4b, 5a, 5b. For example, wire bonding pads are similarly formed at the other ends of the wiring patterns 7a, 7b, 8a, and 8b, and are connected to chip components (not shown).

そして、第1の基板2上の2列のワイヤボンデ
イングパツド4a,4bのうち、第1の基板2と
第2の基板3との境界線9に対し外側の列のワイ
ヤボンデイングパツド4aと、第2の基板3上の
2列のワイヤボンデイングパツド5a,5bのう
ちの該境界線9に対し内側の列のワイヤボンデイ
ングパツド5bとがボンデイングワイヤ6bによ
り接続され、同様に第1の基板2上の境界線9に
対し内側の列のワイヤボンデイングパツド4b
と、第2の基板3上の境界線9に対し外側の列の
ワイヤボンデイングパツド5aとがボンデイング
ワイヤ6bにより接続されている。
Of the two rows of wire bonding pads 4a and 4b on the first substrate 2, the wire bonding pads 4a and 4b in the outer row with respect to the boundary line 9 between the first substrate 2 and the second substrate 3 are Of the two rows of wire bonding pads 5a, 5b on the second substrate 3, the wire bonding pads 5b in the inner row with respect to the boundary line 9 are connected by bonding wires 6b, and similarly, the wire bonding pads 5b in the inner row are connected to the boundary line 9. Wire bonding pads 4b in the inner row with respect to the boundary line 9 on the substrate 2
and the wire bonding pads 5a in the outer row with respect to the boundary line 9 on the second substrate 3 are connected by bonding wires 6b.

ここで、第1および第2の基板2,3上のいず
れにおいても、1回目のワイヤボンデイング工
程、つまりフアーストボンデイングは境界線9に
対し外側の列のワイヤボンデイングパツド4a,
5aについて施され、また2回目のワイヤボンデ
イング工程、つまりセカンドボンデイングは境界
線9に対し内側の列のワイヤボンデイングパツド
4b,5bについて施される。なお、図ではフア
ーストボンデイングはボールボンデイングによつ
て行なわれ、セカンドボンデイングはウエツジボ
ンデイングによつて行なわれている。
Here, on both the first and second substrates 2 and 3, the first wire bonding step, that is, the first bonding, is performed on the wire bonding pads 4a,
5a, and a second wire bonding step, ie, second bonding, is performed on the wire bonding pads 4b, 5b in the inner row with respect to the boundary line 9. In the figure, the first bonding is performed by ball bonding, and the second bonding is performed by wedge bonding.

このような本発明に基くワイヤボンデイング方
法によれば、ボンデイングワイヤ6a,6bは外
側の列のワイヤボンデイングパツド4a,5aに
接続された側では、フアーストボンデイングであ
るため内側の列のワイヤボンデイングパツド4
b,5b上において該パツド4b,5bから上方
に十分離れるため、パツド4b,5bに接触する
可能性はほとんどない。このため、外側の列のワ
イヤボンデイングパツド4a,5aと、内側の列
のワイヤボンデイングパツド4b,5bとの間隔
を小さくでき、ボンデイングワイヤ6a,6bの
長さを最小限に短くすることができる。
According to the wire bonding method according to the present invention, since the bonding wires 6a and 6b are first bonded on the side connected to the wire bonding pads 4a and 5a in the outer row, the bonding wires 6a and 6b are connected to the wire bonding pads in the inner row. Padded 4
Since the pads are sufficiently spaced upward from the pads 4b, 5b on the pads 4b, 5b, there is almost no possibility of contacting the pads 4b, 5b. Therefore, the distance between the wire bonding pads 4a, 5a in the outer row and the wire bonding pads 4b, 5b in the inner row can be reduced, and the length of the bonding wires 6a, 6b can be minimized. can.

一方、ボンデイングワイヤ6a,6bは内側の
列のボンデイングパツド4b,5bに接続された
側はウエツジボンデイングによるセカンドボンデ
イングであるが故に、基板2,3面に近接した状
態になるが、その近傍には他のワイヤボンデイン
グパツドが存在しないため、なんら問題はない。
On the other hand, the side of the bonding wires 6a and 6b connected to the bonding pads 4b and 5b in the inner row is second bonded by wedge bonding, so they are in a state close to the substrates 2 and 3. Since there are no other wire bonding pads, there is no problem.

さらに、ボンデイングワイヤ6aと6bとは、
正面から見て第1の基板2と第2の基板3との境
界線9上付近の一点Pでのみしか交叉しないの
で、これらが互いに接触する可能性は極めて少な
い。
Furthermore, the bonding wires 6a and 6b are
Since the first substrate 2 and the second substrate 3 intersect only at one point P near the boundary line 9 when viewed from the front, the possibility that they will come into contact with each other is extremely small.

従つて、本発明によればボンデイング工程後、
ボンデイングワイヤとボンデイングパツドとの接
触や、ボンデイングパツド間の接触を直すための
ワイヤの修正作業が不要か、極めて少なくて済む
ことになり、生産性が著しく向上する。
Therefore, according to the present invention, after the bonding process,
Wire modification work for correcting the contact between the bonding wire and the bonding pad or the contact between the bonding pads is unnecessary or can be minimized, resulting in a significant improvement in productivity.

また。上記実施例ではフアーストボンデイング
がボールボンデイングであるため、次の点で有利
である。すなわち、ボールボンデイングはウエツ
ジボンデイングに比べて、ワイヤ材料の潰れによ
る横方向(ワイヤに直交する方向)へのはみ出し
が少ないという特長があるため、ボールボンデイ
ングによるフアーストボンデイングが施される外
側の列のワイヤボンデイングパツド4a,5aの
寸法(特にワイヤに直交する方向の寸法)を小さ
くでき、またワイヤボンデイングパツド4a間お
よび5a間を通過する内側の列のワイヤボンデイ
ングパツド4b,5bからの配線パターン7b,
8bへの接触の危険性も少なくなる。従つて、外
側の列のワイヤボンデイングパツド4a,5aの
密度を内側の列のワイヤボンデイングパツド4
b,5bと同等にまで高くとることが可能であ
り、ボンデイング密度を高くすることができる。
Also. In the above embodiment, since the first bonding is ball bonding, it is advantageous in the following points. In other words, compared to wedge bonding, ball bonding has the advantage that there is less protrusion in the lateral direction (direction perpendicular to the wire) due to the collapse of the wire material. The dimensions of the wire bonding pads 4a and 5a (especially the dimension in the direction perpendicular to the wire) can be reduced, and the distance from the inner row of wire bonding pads 4b and 5b passing between the wire bonding pads 4a and 5a can be reduced. wiring pattern 7b,
The risk of contact with 8b is also reduced. Therefore, the density of the wire bonding pads 4a, 5a in the outer row is changed from that of the wire bonding pads 4 in the inner row.
It is possible to increase the bonding density to the same level as b and 5b, and the bonding density can be increased.

本発明のワイヤボンデイング方法は、千鳥状ワ
イヤボンデイングボンデイングを長い領域にわた
つて行なうような機能デバイス、例えば第2図に
示すように第1の基板2と第2の基板3上に、素
子アレイ21とそれを駆動するための電子回路2
2(ICチツプ等)を分割して設け、両基板2,
3を共通の支持用基板1上に固定してから、各基
板2,3上の配線パターン間をワイヤボンデイン
グにより接続するようなデバイス(長尺イメージ
センサや分割型サーマルヘツド等)に、特に好適
である。このようなデバイスでは素子アレイ(イ
メージセンサの場合は光電変換素子アレイ、サー
マルヘツドの場合は発熱素子アレイ)の配列密度
が8本/mmあるいはそれ以上のものが実用化され
ており、ワイヤボンデイングにもそれと同程度の
密度が要求されるが、本発明を用いればこのよう
な高密度ワイヤボンデイングの要求を高い歩留り
と、高い量産性をもつて応えることができる。
The wire bonding method of the present invention is applied to a functional device in which staggered wire bonding is performed over a long area, for example, an element array 21 on a first substrate 2 and a second substrate 3 as shown in FIG. and electronic circuit 2 to drive it
2 (IC chip, etc.) is provided separately, and both substrates 2,
3 is fixed on a common support substrate 1, and then the wiring patterns on each substrate 2 and 3 are connected by wire bonding (long image sensor, split type thermal head, etc.). It is. In such devices, element arrays (photoelectric conversion element arrays in the case of image sensors, heating element arrays in the case of thermal heads) with an array density of 8/mm or more have been put into practical use, and wire bonding However, the present invention can meet the demand for high-density wire bonding with high yield and high mass productivity.

第3図は本発明の他の実施例を示したもので、
基板31上に形成されたワイヤボンデイングパツ
ド32a,32bと、基板31上に搭載された
ICチツプ等のチツプ部品33上の入出力用ワイ
ヤボンデイングパツド34a,34bとをボンデ
イングワイヤ35a,35bにより千鳥状ボンデ
イングで接続する場合に本発明を適用したときの
状態を示している。基板31上のボンデイングパ
ツド32a,32bには配線パターン36a,3
6bが接続されている。図において、ボンデイン
グワイヤ35a,35bのうち、ワイヤボンデイ
ングパツド32a,34aに接続された側がフア
ーストボンデイング、ワイヤボンデイングパツド
32b,34bに接続された側がセカンドボンデ
イングである。この実施例においても先の実施例
と同様な効果が得られることは明らかである。な
お、第3図においてICチツプ33を基板31と
別の単なる基板に置換えた場合にも同様な効果が
得られる。
FIG. 3 shows another embodiment of the present invention,
Wire bonding pads 32a and 32b formed on the substrate 31 and wire bonding pads 32a and 32b mounted on the substrate 31
This figure shows a state in which the present invention is applied when connecting input/output wire bonding pads 34a and 34b on a chip component 33 such as an IC chip using bonding wires 35a and 35b in a staggered bonding manner. Wiring patterns 36a, 3 are formed on the bonding pads 32a, 32b on the substrate 31.
6b is connected. In the figure, of the bonding wires 35a and 35b, the side connected to the wire bonding pads 32a and 34a is the first bonding, and the side connected to the wire bonding pads 32b and 34b is the second bonding. It is clear that this embodiment also provides the same effects as the previous embodiment. The same effect can be obtained even if the IC chip 33 in FIG. 3 is replaced with a simple board other than the board 31.

本発明はその他、要旨を逸脱しない範囲で種々
変形実施が可能であり、例えば実施例で基板上の
ワイヤボンデイングパツド間、あるいは基板上の
ワイヤボンデイングパツドとチツプ部品における
ワイヤボンデイングパツドとの接続の場合につい
て述べたが、配線パターンにワイヤボンデイング
パツドを設けず、配線パターンと他の配線パター
ンまたは該配線パターン端部に形成されたワイヤ
ボンデイングパツドあるいはチツプ部品上のワイ
ヤボンデイングパツドとの接続を千鳥状ボンデイ
ングで接続する場合等にも本発明を適用できるこ
とはいうまでもない。
The present invention can be modified in various other ways without departing from the scope of the invention. For example, in the embodiments, wire bonding pads on a board may be connected, or wire bonding pads on a board and wire bonding pads on a chip component may be As described above, the wiring pattern does not have a wire bonding pad, and the wiring pattern is connected to another wiring pattern, a wire bonding pad formed at the end of the wiring pattern, or a wire bonding pad on a chip component. It goes without saying that the present invention can also be applied to cases where connections are made using staggered bonding.

また、上記実施例でフアーストボンデイングを
ボールボンデイングとして説明したが、本発明は
フアーストボンデイングがウエツジボンデイング
の場合にも有効である。
Furthermore, although the first bonding was explained as ball bonding in the above embodiments, the present invention is also effective when the first bonding is wedge bonding.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本発明の一実施例に係るワイヤ
ボンデイング方法を説明するための平面図および
断面図、第2図は同実施例のワイヤボンデイング
方法を適用した機能デバイスの一例の概略を示す
図、第3図は本発明の他の実施例に係るワイヤボ
ンデイング方法を説明するための断面図、第4図
a,bは従来の千鳥状ボンデイングを用いたワイ
ヤボンデイング方法を説明するための平面図およ
び断面図である。 1……支持用基板、2……第1の基板(第1の
領域)、3……第2の基板(第2の領域)、4a,
4b,5a,5b……ボンデイングパツド、6
a,6b……ボンデイングワイヤ、7a,7b,
8a,8b……配線パターン、9……第1の領域
と第2の領域との境界線、21……素子アレイ、
22……チツプ部品、31……基板、32a,3
2b…34a,34b……ボンデイングパツド、
33……チツプ部品、35a,35b……ボンデ
イングワイヤ、36a,36b……配線パター
ン。
1A and 1B are a plan view and a sectional view for explaining a wire bonding method according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of an example of a functional device to which the wire bonding method of the embodiment is applied. 3 is a sectional view for explaining a wire bonding method according to another embodiment of the present invention, and FIGS. 4a and 4 b are cross-sectional views for explaining a wire bonding method using conventional staggered bonding. FIG. 2 is a plan view and a sectional view. DESCRIPTION OF SYMBOLS 1... Supporting substrate, 2... First substrate (first region), 3... Second substrate (second region), 4a,
4b, 5a, 5b... bonding pad, 6
a, 6b...bonding wire, 7a, 7b,
8a, 8b... Wiring pattern, 9... Boundary line between the first region and the second region, 21... Element array,
22... Chip parts, 31... Board, 32a, 3
2b...34a, 34b...bonding pad,
33... Chip parts, 35a, 35b... Bonding wire, 36a, 36b... Wiring pattern.

Claims (1)

【特許請求の範囲】 1 第1の領域上にある複数の配線パターンまた
はそれらに接続されたボンデイングパツドあるい
はチツプ部品のボンデイングパツドと、第2の領
域上にある複数の配線パターンまたはそれらに接
続されたボンデイングパツドあるいはチツプ部品
のボンデイングパツドとの間を千鳥状ワイヤボン
デイングにより接続するワイヤボンデイング方法
において、前記第1および第2の領域上における
各2列のワイヤボンデイング位置のうち、各領域
の境界線に対し外側の列についてフアーストボン
デイングを施し、内側の列についてセカンドボン
デイングを施すことを特徴とするワイヤボンデイ
ング方法。 2 フアーストボンデイングはボールボンデイン
グであり、セカンドボンデイングはウエツジボン
デイングであることを特徴とする特許請求の範囲
第1項記載のワイヤボンデイング方法。 3 第1の領域は所定の素子アレイが形成された
基板であり、第2の領域はこの素子アレイに接続
される電子回路が構成された基板であることを特
徴とする特許請求の範囲第1項記載のワイヤボン
デイング方法。
[Claims] 1 A plurality of wiring patterns on a first region or a bonding pad connected to them or a bonding pad of a chip component, and a plurality of wiring patterns on a second region or a bonding pad connected to them. In a wire bonding method in which connected bonding pads or bonding pads of chip components are connected by staggered wire bonding, each of the two rows of wire bonding positions on the first and second regions is A wire bonding method characterized by performing first bonding on the outer rows and performing second bonding on the inner rows with respect to the boundary line of the area. 2. The wire bonding method according to claim 1, wherein the first bonding is ball bonding and the second bonding is wedge bonding. 3. Claim 1, wherein the first area is a substrate on which a predetermined element array is formed, and the second area is a substrate on which an electronic circuit connected to this element array is formed. Wire bonding method described in section.
JP59228507A 1984-10-30 1984-10-30 Wire bonding method Granted JPS61105851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59228507A JPS61105851A (en) 1984-10-30 1984-10-30 Wire bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59228507A JPS61105851A (en) 1984-10-30 1984-10-30 Wire bonding method

Publications (2)

Publication Number Publication Date
JPS61105851A JPS61105851A (en) 1986-05-23
JPH0365894B2 true JPH0365894B2 (en) 1991-10-15

Family

ID=16877521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59228507A Granted JPS61105851A (en) 1984-10-30 1984-10-30 Wire bonding method

Country Status (1)

Country Link
JP (1) JPS61105851A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140095044A (en) * 2010-11-25 2014-07-31 미쓰비시덴키 가부시키가이샤 Semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695538B2 (en) * 1987-06-29 1994-11-24 日本電気株式会社 Method for manufacturing semiconductor device
JP6196092B2 (en) * 2013-07-30 2017-09-13 ルネサスエレクトロニクス株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140095044A (en) * 2010-11-25 2014-07-31 미쓰비시덴키 가부시키가이샤 Semiconductor device

Also Published As

Publication number Publication date
JPS61105851A (en) 1986-05-23

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