JPS6185832A - Wire-bonding - Google Patents

Wire-bonding

Info

Publication number
JPS6185832A
JPS6185832A JP59207782A JP20778284A JPS6185832A JP S6185832 A JPS6185832 A JP S6185832A JP 59207782 A JP59207782 A JP 59207782A JP 20778284 A JP20778284 A JP 20778284A JP S6185832 A JPS6185832 A JP S6185832A
Authority
JP
Japan
Prior art keywords
lead bonding
semiconductor chip
bonding pads
inner lead
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59207782A
Other languages
Japanese (ja)
Inventor
Yoshikatsu Fukumoto
福本　好克
Makoto Takahata
高畠　真
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59207782A priority Critical patent/JPS6185832A/en
Publication of JPS6185832A publication Critical patent/JPS6185832A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明は回路基板上にダイボンドされた半導体チップと
インナーリードボンディングパッドと同じ回路基板上に
設けられｌ〔アウターリードボンディングパッドとをボ
ンディングワイヤにより電気的に接続する方法に関する
。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor chip that is die-bonded on a circuit board and an inner lead bonding pad provided on the same circuit board. related to how to connect.

［発明の技術的背景とその問題点］ 近年、ゲートの高密度化およびそれに伴う多ピン化に対
処して、上面に入出力用の複数のインナーリードボンデ
ィングパッドを千鳥状に２列に配設した半導体チップが
開発されている。[Technical background of the invention and its problems] In recent years, in response to the increasing density of gates and the resulting increase in the number of pins, a plurality of inner lead bonding pads for input/output are arranged in two staggered rows on the top surface. Semiconductor chips have been developed.

このような半導体チップを回路基板上に実装する場合に
は、１１２図に示すように、回路基板１上のリードフレ
ーム先端にもこれら半導体チップ２−ヒのインナーリー
ドボンディングパッド３と対向して千鳥状に複数のアウ
ターリードボンディングパッド４を設け、しかもそれぞ
れのボンディングに要するボンディングワイヤ５の長さ
を均等にするために半導体チップ２の外周に近い方のイ
ンナーリードボンディングパッド３の列と、この半導体
チップ２から離れた方のアウターリードボンディングパ
ッド４の列とを対向させて配置させ、これらのボンディ
ングパッド間をボンディングワイヤ５で順に接続する方
法がとられている。When mounting such a semiconductor chip on a circuit board, as shown in FIG. In order to provide a plurality of outer lead bonding pads 4 in a shape and to equalize the length of bonding wires 5 required for each bonding, a row of inner lead bonding pads 3 near the outer periphery of the semiconductor chip 2 and a row of inner lead bonding pads 3 near the outer periphery of the semiconductor chip 2 are provided. A method is used in which a row of outer lead bonding pads 4 located away from the chip 2 are arranged to face each other, and these bonding pads are successively connected by bonding wires 5.

しかしながら、このような方法では、隣り合ったボンデ
ィングエリアが極めて狭いため、ボンディングワイヤ５
の引き出しおよび圧着を行なうキャピラリーの先端がす
でに接続されたボンディングワイヤ５に接触し、これを
倒したり断線させたりし易いという問題があった。However, in such a method, since the adjacent bonding areas are extremely narrow, the bonding wire 5
There has been a problem in that the tip of the capillary for pulling out and crimping comes into contact with the bonding wire 5 that has already been connected, making it easy to knock it over or break it.

また、前述のように配列されたインナーリードボンディ
ングパッド３とアウターリードボンディングパッド４と
の間を、配列順通りではイｉく、まず１つおきにボンデ
ィングを行ない、次に間の残ったボンディングパッド四
を接続する方法も考えられる。In addition, bonding is performed between the inner lead bonding pads 3 and the outer lead bonding pads 4 arranged as described above, even if they are not arranged in the order in which they are arranged. Another possible method is to connect four.

しかしながら、この方法でも後からのボンディング工程
では、インナーリードボンディングパッド３かアウター
リードボンディングパッド４かのいずれかへのボンディ
ングワイヤ５の接続をすでに張られたボンディングワイ
Ａ’　５の間の狭いエリアで行なわなければならず好ま
しくなかった。However, even with this method, in the subsequent bonding process, the bonding wire 5 is connected to either the inner lead bonding pad 3 or the outer lead bonding pad 4 in a narrow area between the bonding wires A' 5 that have already been stretched. I had to do it and it was not good.

［発明の目的］ 本発明はこれらの問題を解決するためになされたもので
、キャピラリー先端の接触によりすでに張られたボンデ
ィングワイヤが変形したり断線したりすることがほとん
どなく、作業が容易なワイヤボンディング方法を提供す
ることを目的とする。[Object of the Invention] The present invention has been made to solve these problems, and provides a bonding wire that is easy to work with and hardly deforms or breaks due to contact with the tip of the capillary. The purpose is to provide a bonding method.

［発明の概要］ すなわち本発明のワイヤボンディング方法は、回路基板
上にダイボンドされた半導体チップ上に千鳥状に配列さ
れた複数のインナーリードボンディングパッドと、前記
回路基板上にこれらのインナーリードボンディングパッ
ドと対向して千鳥状に設けられた複数のアウターリード
ボンディングパッドとを、ボンディングワイヤによりそ
れぞれ電気的に接続する方法において、半導体チップの
外周に近い方のインナーリードボンディングパッドの列
の各ボンディングパッドと該半導体チップに近い方のア
ウターリードボンディングパッドの列の各ボンディング
パッドを対向させ、かつ残りの列のインナーリードボン
ディングパッドと各アウターリードボンディングパッド
とをそれぞれ対向させるとともに、これらのボンディン
グパッド間を１つおきにしかも前記半導体チップの外周
に近い方のインナーリードボンディングパッドとこれと
対向する半導体チップに近い方のアウターリードボンデ
ィングパッドと順に接続した後、次に残された半導体チ
ップの外周から離れた方のアウターリードボンディング
パッドとこれと対向する半導体チップから離れた方のア
ウターリードボンディングパッドとを順に電気的に接続
することを特徴としている。[Summary of the Invention] That is, the wire bonding method of the present invention includes a plurality of inner lead bonding pads arranged in a staggered manner on a semiconductor chip die-bonded on a circuit board, and a plurality of inner lead bonding pads arranged on the circuit board. In a method of electrically connecting a plurality of outer lead bonding pads facing each other in a staggered manner using bonding wires, each bonding pad in a row of inner lead bonding pads closer to the outer periphery of a semiconductor chip is The bonding pads in the row of outer lead bonding pads closer to the semiconductor chip are made to face each other, and the inner lead bonding pads and each outer lead bonding pad in the remaining rows are made to face each other. After connecting the inner lead bonding pad that is closer to the outer periphery of the semiconductor chip and the outer lead bonding pad that is closer to the opposing semiconductor chip in order, It is characterized in that the outer lead bonding pad on one side and the outer lead bonding pad on the opposite side away from the semiconductor chip are electrically connected in order.

［発明の実施例］ 以下本発明の実施例を図面に基づいて説明する。[Embodiments of the invention] Embodiments of the present invention will be described below based on the drawings.

なお、以下の図面においては第２図と同じ部分には同一
符号を付している。In the following drawings, the same parts as in FIG. 2 are designated by the same reference numerals.

実施例においては、第１図（ａ）に示すように、インナ
ーリードボンディングパッド３の２つの列とアウターリ
ードボンディングパッド４の２つの列を、半導体チップ
２の外周に近い方に並置されたインナーリードボンディ
ングパッド３のダ１の各ボンディングパッドが半導体チ
ップ２に近い方に１ｉｆｆされたアウターリードボンデ
ィングパッド１１の列の各ボンディングパッドと対向し
、半導体チップ２の外周から遠い方のインナーリードボ
ンディングパッド３の列の各ボンディングパッドと半導
体チップ２から離れた方のインナーリードボンディング
パッド３の列の各ボンディングパッドとが対向するよう
に配置する。In the embodiment, as shown in FIG. 1(a), two rows of inner lead bonding pads 3 and two rows of outer lead bonding pads 4 are arranged in parallel on the inner side closer to the outer periphery of the semiconductor chip 2. Each of the bonding pads of the lead bonding pads 3 faces each bonding pad of the row of outer lead bonding pads 11 that is arranged closer to the semiconductor chip 2, and is an inner lead bonding pad that is farther from the outer periphery of the semiconductor chip 2. The bonding pads in the row of inner lead bonding pads 3 and the bonding pads in the row of inner lead bonding pads 3 located away from the semiconductor chip 2 are arranged so as to face each other.

このように配置されたそれぞれ対向するボンディングパ
ッドの間を、まず最初は１つおきになるように、半導体
チップ２の外周に近い位胃に配置されたインナーリード
ボンディングパッド３と半導体チップ２に近い方のアウ
ターリードボンディングパッド４とをボンディングワイ
ヤ５で順に接続し、次いで第１図（ｂ）に示すように、
残された半導体チップ２の外周および半導体チップ２自
体から遠い方に配設されたインナーリードボンディング
パッド３およびアウターリードボンディングパッド４間
を順に接続する。Between the opposing bonding pads arranged in this way, first, every other bonding pad is placed between the inner lead bonding pads 3 arranged near the outer periphery of the semiconductor chip 2 and the inner lead bonding pads 3 arranged near the outer periphery of the semiconductor chip 2. The other outer lead bonding pad 4 is connected in order with the bonding wire 5, and then, as shown in FIG. 1(b),
Inner lead bonding pads 3 and outer lead bonding pads 4 disposed on the outer periphery of the remaining semiconductor chip 2 and on the side far from the semiconductor chip 2 itself are connected in order.

このように構成される実施例によれば、最初のボンディ
ングは１つおきで周囲に十分な余裕があるため支障なく
行なうことができる。また、第１図（ｂ）のＣ−Ｃ線に
沿う側面図である同図（Ｃ）に示すように、次の残りの
接続すべきインナーリードボンディングパッド３とアウ
ターリードボンディングパッド４の両方ともがすでに張
られたボンディングワイヤ５の間に配置されていないの
で、ボンディングの際に隣接するボンディングワイヤ５
にキャピラリー６の先端が接触し、これに損傷を与えた
りすることがない。According to the embodiment configured in this manner, the first bonding can be performed without any problem because there is sufficient margin around every other bond. In addition, as shown in FIG. 1(C), which is a side view taken along line C-C in FIG. 1(b), both the inner lead bonding pad 3 and outer lead bonding pad 4 to be connected are is not placed between the bonding wires 5 that have already been stretched, so the adjacent bonding wires 5 are not placed between the bonding wires 5 that have already been stretched.
The tip of the capillary 6 will not come into contact with the capillary and damage it.

［発明の効果］ 以上の記載から明らかなように本発明によれば、すでに
接続されたボンディングワイヤに損（真を与えることな
く、簡単にボンディングを行なうことができる。[Effects of the Invention] As is clear from the above description, according to the present invention, bonding can be easily performed without causing any loss to the bonding wires that have already been connected.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の詳細な説明するだめの平面図、第２図
は従来のワイヤボンディング方法を示す平面図である。 １・・・・・・・・・・・・回路基板 ２・・・・・・・・・・・・半導体チップ３・・・・・
・・・・・・・インナーリードボンディングパッド ４・・・・・・・・・・・・アウターリードボンディン
グパッド ５・・・・・・・・・・・・ボンディングワイヤ６・・
・・・・・・・・・・キャピラリー代理人弁理士　　　
須　山　佐　− 第１図FIG. 1 is a plan view for explaining the present invention in detail, and FIG. 2 is a plan view showing a conventional wire bonding method. 1......Circuit board 2...Semiconductor chip 3...
......Inner lead bonding pad 4...Outer lead bonding pad 5...Bonding wire 6...
・・・・・・・・・Capillary Patent Attorney
Satoshi Suyama - Figure 1

Claims (1)

【特許請求の範囲】[Claims] （１）回路基板上にダイボンドされた半導体チップ上に
千鳥状に配列された複数のインナーリードボンディング
パッドと、前記回路基板上にこれらのインナーリードボ
ンディングパッドと対向して千鳥状に設けられた複数の
アウターリードボンディングパッドとを、ボンディング
ワイヤによりそれぞれ電気的に接続する方法において、
半導体チップの外周に近い方のインナーリードボンディ
ングパッドの列の各ボンディングパッドと該半導体チッ
プに近い方のアウターリードボンディングパッドの列の
各ボンディングパッドを対向させ、かつ残りの列のイン
ナーリードボンディングパッドと各アウターリードボン
ディングパッドとをそれぞれ対向させるとともに、これ
らのボンディングパッド間を１つおきにしかも前記半導
体チップの外周に近い方のインナーリードボンディング
パッドとこれと対向する半導体チップに近い方のアウタ
ーリードボンディングパッドと順に接続した後、次に残
された半導体チップの外周から離れた方のアウターリー
ドボンディングパッドとこれと対向する半導体チップか
ら離れた方のアウターリードボンディングパッドとを順
に電気的に接続することを特徴とするワイヤボンディン
グ方法。(1) A plurality of inner lead bonding pads arranged in a staggered manner on a semiconductor chip die-bonded on a circuit board, and a plurality of inner lead bonding pads arranged in a staggered manner on the circuit board facing these inner lead bonding pads. In the method of electrically connecting the outer lead bonding pads of
Each bonding pad in the row of inner lead bonding pads closer to the outer periphery of the semiconductor chip is opposed to each bonding pad in the row of outer lead bonding pads closer to the semiconductor chip, and the inner lead bonding pads in the remaining rows are The outer lead bonding pads are arranged to face each other, and every other bonding pad is connected to an inner lead bonding pad that is closer to the outer periphery of the semiconductor chip and an outer lead bonding pad that is closer to the opposing semiconductor chip. After sequentially connecting the pads, electrically connect the remaining outer lead bonding pad away from the outer periphery of the semiconductor chip and the opposing outer lead bonding pad away from the semiconductor chip in order. A wire bonding method characterized by:
JP59207782A 1984-10-03 1984-10-03 Wire-bonding Pending JPS6185832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59207782A JPS6185832A (en) 1984-10-03 1984-10-03 Wire-bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59207782A JPS6185832A (en) 1984-10-03 1984-10-03 Wire-bonding

Publications (1)

Publication Number Publication Date
JPS6185832A true JPS6185832A (en) 1986-05-01

Family

ID=16545415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59207782A Pending JPS6185832A (en) 1984-10-03 1984-10-03 Wire-bonding

Country Status (1)

Country Link
JP (1) JPS6185832A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647530A (en) * 1987-06-29 1989-01-11 Nec Corp Manufacture of semiconductor device
JPH0287637A (en) * 1988-09-26 1990-03-28 Nec Corp Semiconductor integrated circuit device and manufacture thereof
WO2001020669A3 (en) * 1999-09-16 2001-10-04 Koninkl Philips Electronics Nv Use of additional bonding finger rows to improve wire bond density
JP2012028429A (en) * 2010-07-21 2012-02-09 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647530A (en) * 1987-06-29 1989-01-11 Nec Corp Manufacture of semiconductor device
JPH0287637A (en) * 1988-09-26 1990-03-28 Nec Corp Semiconductor integrated circuit device and manufacture thereof
WO2001020669A3 (en) * 1999-09-16 2001-10-04 Koninkl Philips Electronics Nv Use of additional bonding finger rows to improve wire bond density
JP2012028429A (en) * 2010-07-21 2012-02-09 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

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