JPH0366100A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To use a filter with a few stage number for a post-stage filter and to realize save space by inserting a signal resulting from succeeding and preceding signals subject to mean value interpolation to a joint of sample-and-hold signals. CONSTITUTION:At first a gate 2 is switched and an input signal is held in a capacitor C 10, and a signal inputted to an amplifier 15 is subject to sample- and-hold by a gate 6 and the result is outputted. Then a gate 3 is switched and the input signal is held in a capacitor C 11, the signal inputted to an amplifier 16 is averaged with a signal inputted to the amplifier 15 by a gate 19 and subject to sample-and-hold by a gate 7 and outputted. The operation above is repeated and an output repeating alternately a sample-and-hold signal and a mean value interpolation signal is obtained, and a sampling frequency is 2fCR to allow the use of a filter with a few order-number for the post-stage filter and saving of space is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a sample and hold circuit that utilizes an average value interpolation signal.

BACKGROUND OF THE INVENTION In recent years, in the field of signal processing, sample-and-hold circuits have come into widespread use amid the trend toward digitalization.

A conventional sample and hold circuit will be explained below.

FIG. 4 is a schematic diagram of the configuration of a conventional sample and hold circuit, in which 21 is a sampling gate, 22 is a hold capacitor, and 23 is an amplifier. 24 is an input, and 25 is an output.

FIG. 5 is a time chart for controlling the sampling gate 21 of this conventional sample and hold circuit.

Regarding the sample hold circuit configured in this way,
The operation will be explained below.

First, when a signal voltage is applied to the input 24 and the sampling gate 21 is closed, the signal voltage is applied to the input of the amplifier 23 and transmitted to the output 25. When the sampling gate 21 is opened after a certain period of time according to the time chart in FIG. 2, the signal voltage is stored in the form of charge by the hold capacitor 22, and the output 25 is held. By repeating the above operations, a signal voltage is transmitted according to the opening and closing of the sampling gate.

If the opening/closing frequency of the sampling gate is fc, then the signal frequency f wig that can be handled by this sample and hold circuit is
and the switching frequency fcK, f wig<2 f C
It is known that a relationship of K is required, and since the signal of output 25 includes a component of fcK, this fcK relationship is required.
It is necessary to remove the CK component by adding a filter at a subsequent stage. Although this filter needs to have the characteristics shown in FIG. 6, it is difficult to achieve this in practice, so a filter with similar characteristics is used instead.

Problems to be Solved by the Invention However, with the above conventional configuration, it is difficult to obtain an ideal post-stage filter, and even when a filter with similar characteristics is substituted, it is difficult to obtain a low-cost, space-saving filter. .

The present invention is intended to solve the above-mentioned conventional problems, and aims to provide a sample-and-hold circuit that can reduce the cost and space of a subsequent filter.

Means for Solving the Problems In order to achieve this object, the sample-and-hold circuit of the present invention has a configuration in which a signal obtained by interpolating the average value of previous and subsequent signals is inserted into the connecting portion of the sample-and-hold signal. .

Effect: With this configuration, it is possible to realize cost reduction and space saving of the post-stage filter.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of the configuration of an average value interpolation sample and hold circuit according to an embodiment of the present invention.

In Figure 1, 1, 2, 3, 4, 5, 6 degrees 7.8 are sampling gates, 9.10, 11 degrees 12.13 are hold capacitors, 14, 15 degrees 16, 17 and 18 are amplifiers, 19 .20 is the gate.

FIG. 2 is a time chart of control signals applied to each gate.

Regarding the average value interpolation sample hold circuit of this embodiment,
The operation will be explained with reference to the time chart in FIG.

First, gate 2 opened at time tl closes at time t2, the input signal is held in capacitor 10, and the signal input to amplifier 15 is sampled and held by gate 6 at time ts-t4 and output.

Next, the gate 3 that opened at time t5 closes at time t6, and the input signal is held in the capacitor 11 and the amplifier 16
The signal input to the amplifier 15 is averaged with the signal input to the amplifier 15 by the gate 19 from time t7 to t8, and at time t
Sample and hold by gate 7 from 9 to tlO,
Output.

Further, the gate 4 opened at time t5 is closed at time t8, and the input signal is held in the capacitor 12 and the amplifier 17
The input signal is sampled and held by the gate 8 from time t2 to t12, and is output.

Next, gate 1, which opened at time tl3, closes the time,
The input signal is held in the capacitor 9 and sent to the amplifier 14.
The signal input to the amplifier 17 is averaged with the signal input to the amplifier 17 by the gate 20 from time t16 to TI8,
The signal is sampled and held by the gate 5 from time tI7 to t1g and output.

By repeating the above operations, an output is obtained in which the sample-hold signal and the average value interpolation signal are repeated alternately, the sampling frequency becomes 2fCK within the same scratch, and the subsequent filter is
A filter with the characteristics shown in the figure can now be used. This filter becomes a filter with a small number of first orders, and it is possible to reduce manufacturing costs and downsize.

As described above, according to this embodiment, by inserting a signal obtained by interpolating the average value of the preceding and succeeding signals into the connection portion of the sample-and-hold signal, it is possible to realize cost reduction and space saving of the subsequent filter. .

In this embodiment, all the sampling gates 1 to 8 are N-channel MO8FETs, and the gates 19.20 are N-channel MO8FETs.
The 3FET may be used as a simple on/off switch with the same function.

Effects of the Invention As described above, by using the present invention, it is possible to realize a sample-and-hold circuit that has the effect of reducing cost by reducing the manufacturing cost of the post-stage filter and saving space by reducing the order.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a sample and hold circuit according to an embodiment of the present invention, FIG. 2 is a time chart of sampling gate control in the same embodiment, FIG. 3 is a characteristic diagram of a subsequent filter, and FIG.
FIG. 5 is a configuration diagram of a conventional sample and hold circuit, FIG. 5 is a time chart of conventional sampling gate control, and FIG. 6 is a characteristic diagram of a conventional post-stage filter. 1-8...Sampling gate, 9-13...
...Hold capacitor, 14-18...
Amplifier, 19°20...gate. The industry diagram is also field 2fα! ! , -8...-Sampling gate 9,/3--Hold content 14-18...Increase sJk/9. υ−°Kate−Pf=to

Claims (1)

[Claims] a plurality of sampling gates, a plurality of capacitors that hold signal charges held by the sampling gates, one or more gates that average the held signal charges, and a plurality of outputs that output the held signals. A sample and hold circuit comprising an amplifier, a plurality of sampling gates for sequentially sampling signals of the plurality of output amplifiers, a capacitor for holding the sequentially sampled signal charge, and an amplifier for outputting the held signal.