JPH036626A - Input/output controller - Google Patents

Input/output controller

Info

Publication number
JPH036626A
JPH036626A JP14146089A JP14146089A JPH036626A JP H036626 A JPH036626 A JP H036626A JP 14146089 A JP14146089 A JP 14146089A JP 14146089 A JP14146089 A JP 14146089A JP H036626 A JPH036626 A JP H036626A
Authority
JP
Japan
Prior art keywords
interrupt
processing unit
central processing
circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14146089A
Other languages
Japanese (ja)
Inventor
Tatsuo Noguchi
野口 辰生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14146089A priority Critical patent/JPH036626A/en
Publication of JPH036626A publication Critical patent/JPH036626A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain an effective reinterruption processing in accordance with the state of a CPU by instructing a waiting time via the CPU when a reinterruption is carried out. CONSTITUTION:An interruption answer discriminating circuit 113 discriminates whether an interruption is accepted or not. If not, the circuit 113 discriminates whether a reinterruption is requested or not. If so, the circuit 113 starts a reinterruption processing to a control circuit 115. Thus the circuit 115 issues an instruction to an interruption control circuit 111 to start the transfer of the interruption after a time designated by a parameter and based on the contents of an answer parameter receiving circuit 114. Then the circuit 111 carries out an interruption to a CPU via a common bus control circuit 110. Thus it is possible to attain a highly efficient reinterruption process in accordance with the state of the CPU.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、データ処理装置の入出力制御装置に関し、特
に、入出力制御装置の割込み制御に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output control device for a data processing device, and more particularly to interrupt control of the input/output control device.

従来の技術 従来、この種の入出力制御装置は、中央処理装置が割込
みを拒否した際の再割込みを行う場合に、予め設定され
た一定時間の後に再割込みを行っていた。
2. Description of the Related Art Conventionally, this type of input/output control device performs the re-interruption after a preset certain period of time when re-interrupting when the central processing unit rejects the interrupt.

発明が解決しようとする課題 上述した従来の入出力制御装置は、再割込み待ち時間が
予め設定された値に固定されている為に、中央処理装置
の状態に関係なく再割込みを実行しており、割込みの効
率が悪かった。
Problems to be Solved by the Invention In the conventional input/output control device described above, the re-interrupt wait time is fixed to a preset value, so the re-interrupt is executed regardless of the state of the central processing unit. , the interrupt efficiency was poor.

本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記課題
を解決し、高効率的な再割込み処理を実現することを可
能とした新規な入出力制御装置を提供することにある。
The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a novel input/output control device that solves the above-mentioned problems inherent in the conventional technology and makes it possible to realize highly efficient re-interrupt processing.

課題を解決するための手段 上記目的を達成する為に、本発明に係る入出力制御装置
は、中央処理装置に対して割込みの起動を行う割込み制
御回路と、共通バスを介して割込みを中央処理装置へ伝
達する為にバス転送を制御する共通バス制御回路と、中
央処理装置が割込みを受け付けたか拒否したかを判別す
る割込み応答判別回路と、割込み拒否時の再割込みパラ
メータを受信する応答パラメータ受信回路と、指定され
たパラメータに従い再割込みを行う為の再割込み制御回
路とを備えて構成される。
Means for Solving the Problems In order to achieve the above object, an input/output control device according to the present invention includes an interrupt control circuit that initiates an interrupt to a central processing unit, and an interrupt control circuit that initiates an interrupt to a central processing unit, and a central processing unit that initiates an interrupt via a common bus. A common bus control circuit that controls bus transfer for transmission to devices, an interrupt response determination circuit that determines whether the central processing unit has accepted or rejected an interrupt, and a response parameter receiver that receives re-interrupt parameters when an interrupt is rejected. and a re-interrupt control circuit for re-interrupting according to specified parameters.

実施例 次に、本発明をその好ましい一実施例について図面を参
照して具体的に説明する。
Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

第1図は本発明に係る入出力制御装置の一実施例を示す
ブロック構成図である。
FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention.

第1図を参照するに、本発明に係る入出力制御装置10
0は、共通バス101を介して中央処理装置(図示せず
)と接続されている。
Referring to FIG. 1, an input/output control device 10 according to the present invention
0 is connected to a central processing unit (not shown) via a common bus 101.

主制御回路112は、入出力制御装置100の各部を制
御する中央制御回路であり、入出力制御装置100の動
作は主制御回路112により制御される。
The main control circuit 112 is a central control circuit that controls each part of the input/output control device 100, and the operation of the input/output control device 100 is controlled by the main control circuit 112.

入出力制御装置100が中央処理装置に対して割込みを
発生する場合には、先ず主制御回路112が割込み制御
回路111に対して割込みの起動を指示する。を指示を
受けた割込み制御回路111は共通バス制御回路110
及び共通バス101を介して中央処理装置に割込みを実
行する。中央処理装置は、割込みが受け付けられないと
きには、再割込みを要求する応答及び再割込みの待ち時
間を指示するパラメータを入出力制御装置100に対し
て通知する。
When the input/output control device 100 generates an interrupt to the central processing unit, the main control circuit 112 first instructs the interrupt control circuit 111 to start the interrupt. The interrupt control circuit 111 that received the instruction executes the common bus control circuit 110.
and executes an interrupt to the central processing unit via the common bus 101. When the interrupt is not accepted, the central processing unit notifies the input/output control device 100 of a response requesting a re-interrupt and a parameter instructing the wait time for the re-interrupt.

入出力制御装置100は前記応答及びパラメータを共通
バス制御回路110をfPして割込み応答判別回路11
3及び応答パラメータ受信回路114にて受信する0割
込み応答判別回路1.13は、割込みが受け付けられた
か拒否されたかどうかを判別し、また拒否された場合に
はそれが再割込みを要求しているかどうかを判別する。
The input/output control device 100 transmits the response and parameters to the common bus control circuit 110 and transmits them to the interrupt response determination circuit 11.
3 and response parameter receiving circuit 114, the interrupt response determination circuit 1.13 determines whether the interrupt has been accepted or rejected, and if rejected, whether it is requesting another interrupt. determine whether

再割込みを要求する応答であったならば、割込み応答判
別回路113は再割込み制御回路115に対して再割込
み処理の起動を行う。
If the response is a request for a re-interrupt, the interrupt response determination circuit 113 instructs the re-interrupt control circuit 115 to start a re-interrupt process.

再割込み制御回路115は、応答パラメータ受信回路1
14の内容に従い、パラメータで指定された時間だけ待
った後に割込み転送の起動を割込み制御回路111に対
して指示する0割込み制御回路111は共通バス制御回
路110を介して中央処理装置に対して割込みを実行す
る。
The re-interrupt control circuit 115 is the response parameter receiving circuit 1
14, the interrupt control circuit 111 instructs the interrupt control circuit 111 to start interrupt transfer after waiting the time specified by the parameter.0 The interrupt control circuit 111 sends an interrupt to the central processing unit via the common bus control circuit 110 Execute.

発明の詳細 な説明したように、本発明によれば、入出力制御装置が
再割込みを行う際の待ち時間を中央処理装置から指示さ
れるようにすることにより、中央処理装置の状態に応じ
た効果的な再割込み処理を行うことができる。
As described in detail, according to the present invention, the waiting time when the input/output control unit performs a re-interrupt is instructed by the central processing unit, so that the waiting time is adjusted according to the state of the central processing unit. Effective re-interrupt processing can be performed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る入出力制御装置の一実施例を示す
ブロック構成図である。 100・・・入出力制御装置、101・・・共通バス、
110・・・共通バス制御回路、111・・・割込み制
御回路、112・・・主制御回路、113・・・割込み
応答判別回路、114・・・応答パラメータ受信回路、
115・・・再割込み制御回路
FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention. 100... Input/output control device, 101... Common bus,
110... Common bus control circuit, 111... Interrupt control circuit, 112... Main control circuit, 113... Interrupt response determination circuit, 114... Response parameter receiving circuit,
115... Re-interrupt control circuit

Claims (1)

【特許請求の範囲】[Claims] 共通入出力バスを介して中央処理装置に接続され中央処
理装置に対して割込みにより処理動作の起動を行う入出
力制御装置において、前記中央処理装置に対する割込み
の起動を行う割込み制御回路と、共通バスを介して割込
みを中央処理装置へ伝達するようにバス転送を制御する
共通バス制御回路と、前記中央処理装置が割込みを受け
付けたか拒否したかを判別する割込み応答判別回路と、
割込み拒否時の再割込みパラメータを受信する応答パラ
メータ受信回路と、指定されたパラメータに従い再割込
みを行う為の再割込み制御回路とを有し、当該入出力制
御装置が前記中央処理装置に対して実行した割込みが拒
否された際に該中央処理装置から拒否応答と共に通知さ
れる再割込みパラメータに従い、再割込みを発生するこ
とを特徴とする入出力制御装置。
In an input/output control device that is connected to a central processing unit via a common input/output bus and starts processing operations by interrupting the central processing unit, the input/output control device includes an interrupt control circuit that starts an interrupt for the central processing unit, and a common bus. a common bus control circuit that controls bus transfer so as to transmit the interrupt to the central processing unit via the central processing unit; and an interrupt response determination circuit that determines whether the central processing unit has accepted or rejected the interrupt;
It has a response parameter receiving circuit that receives a re-interrupt parameter when an interrupt is rejected, and a re-interrupt control circuit that performs a re-interrupt according to the specified parameters, and the input/output control device executes the command for the central processing unit. 1. An input/output control device that generates a re-interruption in accordance with a re-interruption parameter notified from the central processing unit along with a rejection response when the interrupt is rejected.
JP14146089A 1989-06-02 1989-06-02 Input/output controller Pending JPH036626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14146089A JPH036626A (en) 1989-06-02 1989-06-02 Input/output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14146089A JPH036626A (en) 1989-06-02 1989-06-02 Input/output controller

Publications (1)

Publication Number Publication Date
JPH036626A true JPH036626A (en) 1991-01-14

Family

ID=15292404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14146089A Pending JPH036626A (en) 1989-06-02 1989-06-02 Input/output controller

Country Status (1)

Country Link
JP (1) JPH036626A (en)

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