JPH036628A - Self-diagnosis circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a self-diagnosis circuit in a signal processing circuit system.

BACKGROUND OF THE INVENTION In recent years, with the advancement of LSI technology, digital processing of audio and video has progressed rapidly, and audio and video equipment capable of digital transmission and recording/playback has begun to become widespread.

As devices and systems become more digitalized and circuits become larger and more complex, self-diagnosis functions for fault checking, which are already incorporated in computer equipment, become necessary.

However, the self-diagnosis function of a computer is slightly different from that of an audio/video device. In the case of a computer, a predetermined set of several hundred instructions checks the hardware and software, including peripheral devices such as memory and disks, to ensure that they can be executed without any problems. We check to ensure that arithmetic processing, etc., are performed correctly at the specified timing of actual operation for a huge amount of random data flow, and that there are no problems with the final audio/video output data. must be shown.

A conventionally used method is shown in FIG. In the figure, 41 is a signal input terminal, 42 is a transmission and recording (recording is omitted hereafter) image signal processing circuit, 43 is a transmission and recording/playback (hereinafter, recording and playback is omitted) system system, and 44 is a reception and playback (hereinafter, recording is omitted) system system. , reproduction omitted) image signal processing circuit, 45 is a field memory on the transmitting side, 46 is a field memory on the receiving side, 47 is a delay memory for input signals used for self-diagnosis, 4
8 is a coincidence detection circuit, 49 is a signal output terminal, and 50 is a coincidence signal output terminal.

Briefly explaining the operation, digitized data signals are input from the terminal 41 in chronological order, and the transmitting side signal processing circuit 4
In step 2, signal processing that constitutes a transmission format in field units is performed through reading and writing to and from the field memory 45. After the transmission signal passes through the transmission system 43, it is received again (1111 and input to the signal processing circuit 44).

On the receiving side, the signal is restored to the original time-series input signal through communication with the field memory 46, and is outputted from the terminal 48, in the opposite manner to that on the transmitting side. In the above system, the time difference between input and output signals is field memo 1J45. Since reading and writing to -46 are performed twice each, at least two fields or more are generated.

In this signal processing system, when attempting to verify whether an output signal is exactly the same as the original input signal, a delay memory 47 with a capacity of two fields or more delays the input signal, and a coincidence detection circuit 48 detects the output signal on the receiving side. Seeing the agreement with
This can be realized by outputting the result from the terminal 50.

Problems to be Solved by the Invention However, in the case of the above configuration, a huge amount of memory is required in order to match the transmitted (recorded) data and received (played) data in a timely manner, which is difficult to solve in terms of cost. However, it cannot be applied to all uses. Furthermore,
At present, it is technically difficult to incorporate these self-diagnosis functions into LSIs in order to make devices smaller and cheaper.

An object of the present invention is to overcome the above-mentioned problems and realize a self-diagnosis function using a small-scale circuit configuration that can be integrated into an LSI.

Means for Solving the Problems The present invention transmits the results of signal processing such as computation and time series conversion on a human-powered signal sequence, and upon reception, performs inverse calculations on the detected signals and reverses them to the original time series. In a signal processing circuit system that restores the input signal sequence through signal processing such as conversion, the signal processing circuits on the transmission (recording) side and the reception (reproduction) side are each divided into a plurality of blocks, and each block is configured to restore the input signal sequence. check code generating means for providing a short-circuit path for short-circuiting between the output of the side block and the input of the receiving side block, and sequentially generating error check codes from the input signal sequence of the transmitting side circuit block; It is characterized by comprising a buffer means for temporarily accumulating error check codes, and an error detection means for detecting errors from the output signal of the received signal block corresponding to the transmitting side circuit block and the generated error check code. It is something to do.

Effect With the above-described configuration, in the present invention, error detection between the output signal of the receiving side signal processing circuit on the upstream side of the short circuit path of the signal processing circuit system and the error check code generated from the input signal of the transmitting side signal processing circuit is performed. As a result, if there is no error, it can be determined that the circuit system to be diagnosed on the upstream side of the short circuit path is operating normally, and if an error is detected, it is possible to estimate the failure location for each circuit block.

Embodiment FIG. 1 is a configuration diagram of a signal processing circuit system including a self-diagnosis circuit according to an embodiment of the present invention.

In the same figure, 1 is a digitized voice or
video signal input terminal; 2. ..., 21. ...2n is each block of n transmission (recording) image signal processing circuits, and each block is divided by processing function. For example, block 2 is an input processing circuit, block 21 is an error processing circuit during transmission. Block 2n is a modulation processing circuit for transmitting a signal in a form suitable for the transmission path. Therefore, the audio or video signal input to the input terminal 1 is sequentially transferred while undergoing signal processing through each block of the n transmission (recording) image signal processing circuits. 3 is a transmission (recording/reproduction) system, 4,..., 41
．． . . , 4n is each block of n reception (reproduction) image signal processing circuits, which form a pair in exactly the same way as on the transmission side,
It is divided by processing function. For example, corresponding to each example above, block 4n is a demodulation processing circuit, block 41 is an error correction processing circuit, block 4 is an output processing circuit, and the received signal is passed between n blocks while undergoing signal processing. transferred in order. Here, each block 2 of the transmitting side signal processing circuit,
..., 21. ...+2n and each block 4 of the receiving side signal processing circuit. ..., 41. . . , 4n are divided into blocks so that the inputs and outputs of each of them are not exactly the same, but are almost the same and have a considerable portion in common. In other words, in addition to the path that goes through transmission system 3, a short circuit path can be provided between each block to perform bypass, and the final output signal will not change whether it goes through transmission system 3 or the bypass. It is structured so that you can get something. 5. ..., 51. ..., 5
n represents each block 2.n of the transmitting side signal processing circuit. ...,
21. ...2n, and each block 4 of the receiving side signal processing circuit. ...41+ ...+4n, each block of the self-diagnosis circuit provided in the short-circuit path of each block, and since each block has the same configuration, the details are shown as a representative of block 5. ing.

Next, the self-diagnosis circuit 5 will be explained in detail.

The self-diagnosis circuit 5 supplies a check code generation circuit 6 that generates a check code for self-diagnosis from an input signal string, a buffer memory 7 that is a buffer means for storing the generated check code, and a timing signal for self-diagnosis operation. A timing generation circuit 8, an error detection circuit 9 that performs error detection based on the signal processing result of the signal processing block to be self-diagnosed and the generated error check code, It consists of a bypass short-circuit switch 10. 11. ...+11i+ ..., 11n are self-diagnosis circuits 51 ..., 51. . . . , a failure determination signal output terminal provided for each block of 5n, 12
is an output terminal for audio or video signals, and the same signal as the input signal is restored.

FIG. 2 is a configuration diagram of a signal processing circuit system including a self-diagnosis circuit according to another embodiment of the present invention.

In the figure, parts common to those in FIG. 1 are given the same numbers and their explanations are omitted. Reference numeral 13 designates the transmitting side signal processing circuits 2°...21.
. . , 2n is selected as an input to the self-diagnosis circuit 5, and 14 is each block 4° . . . 41 of the receiving signal processing circuit. ..., 4
A receiving side multiplexer which selects one of n and inputs it to the self-diagnosis circuit 5, the multiplexer 13.1
4 are for using one self-diagnosis circuit 5 by time-sharing processing. Reference numeral 15 denotes a failure determination circuit that determines a failure location from the self-diagnosis results of a plurality of circuit blocks performed in a time-sharing manner, and 16 is an output terminal for a failure determination signal.

FIG. 3 is a timing chart diagram for explaining the operation according to an embodiment of the present invention, and shows input signal sequences and check codes generated for self-diagnosis for each of (A) and (B).

Next, moving on to an explanation of the operation, the operation of the signal processing system shown in FIG.
The audio signal is first input to the transmission side signal processing circuit 2, which is the first circuit block, and then..., 21. ...+
Each of the 2n blocks is sequentially transferred and transmitting side signal processing is performed. Common examples of signal processing here include interleaving processing to change the order of transmitted signals, and generation and addition of error detection and correction codes to detect and correct errors during transmission. Conversion to signal format is performed in each circuit block.

The received signal inputted again to the receiving side signal processing circuit 4n via the transmission system 3 undergoes operations in the reverse order as on the transmitting side, and finally the same signal as the original input signal is restored from the terminal 12 and output. do. For example, it performs processing such as dinterleaving processing and error detection/correction.

At this time, the input signal of any transmitting side signal processing circuit 2j,
It is assumed that the signal processing circuits are divided into blocks so that the output signals of any corresponding receiving side signal processing circuit 4j are mostly common, if not exactly the same. For example, if the transmitting side signal processing circuit 21 generates and adds an error correction signal, the corresponding receiving side signal processing circuit 41 has an error correction function, and even if the transmitting side signal processing circuit 2n is a modulation circuit, the corresponding receiving side signal processing circuit 41 has an error correction function. For example, it is assumed that the receiving side signal processing circuit 4n is a demodulation circuit. However, during the above-mentioned normal operation, it is assumed that all the short circuit switches 10 in the arbitrary self-diagnosis circuit 5 are in an open state.

In the self-diagnosis mode for failure detection according to the present invention, in order to verify that the signal processing system described above is operating reliably, this is performed by the method described below. That is, in the present invention, a short circuit path including a self-diagnosis circuit is provided for each signal processing circuit block, and the self-diagnosis circuit determines whether the input/output signals are scattered in the portion to be verified.

Inside the self-diagnosis circuit 5 provided in the short-circuit path, the short-circuit switch 10 is first closed, and the check code generation circuit 6 generates a check code based on a predetermined generation polynomial in response to the input signal from the terminal 1. generation is performed. The check code used in this case is not particularly limited, but if a well-known shortened cyclic code (CRCC) is used, the error detection ability is high even for long data lengths, and the circuit configuration is also comparable to that of cyclic registers. It can be realized using a simple configuration.

Also, if a well-known parity code is used, the error detection ability will be low, but if the simplest circuit (+ is formed and a small number of check codes is stored), it can be realized with the smallest bit capacity.

Figure 3 shows the timing of generating a check code for an input signal sequence. It shows how check codes are generated in units of units, and (B) shows the case where different check codes are generated for input data and parity codes. Furthermore, instead of generating check codes in units of blocks, check codes may be generated in units of multiple blocks, which reduces the detection ability but saves memory capacity.

The generated check code is stored in the -H buffer memory 7, read out as needed, and continues generating check codes for the input signal string. These operations are controlled by the address signal supplied from the timing generation circuit 8 to the buffer memory 7 and the timing signal that extracts only the part to be verified from the input signal string supplied to the check code generation circuit 6 and generates a check code. Ru.

On the other hand, the signal processed by the transmitting side signal processing circuit 2 passes through the switch 10 and is immediately inputted to the receiving side signal processing circuit 4. The receiving side signal processing circuit 4 performs the opposite processing to that on the transmitting side and outputs it to the terminal 12. In addition, the timing is adjusted to the output processed by the receiving side signal processing circuit 4,
The error check code generated by the check code generation circuit is read out from the buffer memory 7 according to the read address supplied by the timing generation circuit 8, and both are input to the error detection circuit 9.

Since the error detection circuit 9 performs error detection using the same generating polynomial as the check code generation circuit 6, the output of the receiving side signal processing circuit 4 is the same as that of the original transmitting side only in the section to be verified in which the check code was generated. If the input signal is the same as the input signal of the signal processing circuit 2, no error will be detected; if there is a failure in either the transmitting or receiving circuit and the output signal is not the same, an error will be detected. It becomes. At this time, the timing generation circuit 8 supplies the gate signal of the inspection target section to the error detection circuit 9. A match/mismatch signal of the error detection result is output from the terminal 1, and although not shown in this figure, the user is eventually notified of the location of the failure using a display device or the like.

Furthermore, in order to identify detailed failure locations, it is effective to subdivide the generation sequence of check codes, for example, by circuit function. That is, as shown in FIG. 3(B), data and parity codes are configured as different check code sequences,
If an error is detected only in the parity part, it can be shown that there is a high possibility of a failure in the signal processing part related to the generation and detection/correction processing of error detection/correction codes. In addition, a different check code sequence is applied to each bit of parallel data, and when only a specific bit of parallel data shows an abnormality, it can be detected that a failure such as a disconnection has occurred in that bit line. can.

Repeat the above operation in the direction of the right hand side of the self-diagnosis circuit 5.
..., 51. ... + 5n, if the self-diagnosis operation is repeated while sequentially closing the internal short-circuit switches 10, it is possible to identify the failure location for the entire signal processing system.

FIG. 2 shows the embodiment shown in FIG. 1, but instead of holding multiple self-diagnosis circuits, the verification target is scanned while switching selections using the multiplexers 13 and 14, and the error detection results are sent to the fault discrimination circuit 15. If information for specifying the location of a fault is stored in the memory and decoded in advance from a combination of detected error patterns, it is possible to realize a more effective circuit configuration with fewer fault determinations.

In the embodiment of the present invention described above, the signal processing circuit is divided into blocks so that the input and output signals on the transmitting side and the receiving side are almost the same for each processing stage, and the As a means of verifying whether the output signals are the same or not, an error check code is generated from the input signal string, and errors are detected from the output signal string and the generated error check code, thereby making the self-diagnosis function for fault detection more efficient. It can be accomplished well. Furthermore, the buffer memory 7 for temporarily storing the check codes inside the self-diagnosis circuit 5 only needs to have a small capacity, and it is quite possible to incorporate the self-diagnosis circuit 5 internally as a part of the signal processing LSI.

Effects of the Invention In the present invention, with the configuration described above, it is possible to efficiently estimate a failure location using simple logic, compared to the conventional method of comparing and verifying input and output signals using a large-capacity delay memory.

Furthermore, the self-diagnosis circuit 5 as a means for detecting a failure location can be realized with a small-scale circuit configuration suitable for LSI implementation, which is highly effective in reducing the size and cost of the signal processing system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal processing circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a signal processing circuit according to another embodiment of the present invention, and FIG. 3 is a block diagram of a signal processing circuit according to another embodiment of the present invention. A timing diagram of processing, FIG. 4, is a configuration diagram of a conventional example. 2... Transmission side signal processing circuit, 4... Receiving side signal processing circuit, 5... Self-diagnosis circuit, 6... Check code generation circuit, 7... Buffer memory, 9
...Error detection circuit, 13,14...Multiplexer.

Claims (1)

[Claims] The results of signal processing such as computation and time series conversion on the input signal string are transmitted, and upon reception, the input signal string is converted into the input signal string by signal processing such as inverse calculation and inverse conversion to the original time series. In the signal processing circuit system to be restored, the signal processing circuits on the transmitting side and the receiving side are each divided into a plurality of blocks, and the output of the transmitting side block and the input of the receiving side block are short-circuited for each block. A check code generating means for providing a short circuit path and sequentially generating error check codes from the input signal sequence of the transmitting side circuit block, a buffer means for temporarily accumulating the generated error check codes, and a check code generating means for temporarily storing the generated error check codes; A self-diagnosis circuit comprising: error detection means for detecting errors from the output signal of the corresponding received signal block and the generated error check code.