JPH0366441U - - Google Patents
Info
- Publication number
- JPH0366441U JPH0366441U JP12730789U JP12730789U JPH0366441U JP H0366441 U JPH0366441 U JP H0366441U JP 12730789 U JP12730789 U JP 12730789U JP 12730789 U JP12730789 U JP 12730789U JP H0366441 U JPH0366441 U JP H0366441U
- Authority
- JP
- Japan
- Prior art keywords
- dram
- data bus
- processing unit
- central processing
- address strobe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Description
第１図は本考案を実施したＤＲＡＭ制御装置を
表わす回路図、第２図は第１図に示した本考案回
路の動作を表わすタイムチヤート、第３図は従来
のＤＲＡＭ制御装置の構成を表わす図である。
１……ＣＰＵ、２……分離回路、３……ＤＲＡ
Ｍ制御部、Ｂ０，Ｂ１……双方向バツフア、Ｍ０
，Ｍ１……ＤＲＡＭバンク、ＤＢ，ＤＢ０，ＤＢ
１……データ・バス。
Fig. 1 is a circuit diagram showing a DRAM control device implementing the present invention, Fig. 2 is a time chart showing the operation of the circuit of the present invention shown in Fig. 1, and Fig. 3 shows the configuration of a conventional DRAM control device. It is a diagram. 1...CPU, 2...Separation circuit, 3...DRA
M control section, B0, B1...bidirectional buffer, M0
, M1...DRAM bank, DB, DB0, DB
1...Data bus.
Claims (1)
アドレス・ストローブ信号及びカラム・アドレス
・ストローブ信号を共通に与えてアクセスするイ
ンターリーブ方式のＤＲＡＭ制御装置であつて、
各ＤＲＡＭバンクのデータ・バスを中央処理装置
のデータ・バスにオア結線し、前記中央処理装置
から与えられるアクセス情報よりアクセスすべき
ＤＲＡＭバンクのみにアウトプツト・イネーブル
信号を与えることを特徴とするＤＲＡＭ制御装置
。 Row memory in at least two or more DRAM banks.
An interleaved DRAM control device that provides access by commonly applying an address strobe signal and a column address strobe signal,
A DRAM control characterized in that a data bus of each DRAM bank is OR-connected to a data bus of a central processing unit, and an output enable signal is provided only to the DRAM bank to be accessed based on access information provided from the central processing unit. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12730789U JPH0366441U (en) | 1989-10-31 | 1989-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12730789U JPH0366441U (en) | 1989-10-31 | 1989-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0366441U true JPH0366441U (en) | 1991-06-27 |
Family
ID=31675067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12730789U Pending JPH0366441U (en) | 1989-10-31 | 1989-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0366441U (en) |
-
1989
- 1989-10-31 JP JP12730789U patent/JPH0366441U/ja active Pending