JPH0366487U - - Google Patents
Info
- Publication number
- JPH0366487U JPH0366487U JP12582689U JP12582689U JPH0366487U JP H0366487 U JPH0366487 U JP H0366487U JP 12582689 U JP12582689 U JP 12582689U JP 12582689 U JP12582689 U JP 12582689U JP H0366487 U JPH0366487 U JP H0366487U
- Authority
- JP
- Japan
- Prior art keywords
- control unit
- transmission processing
- memory
- processing device
- supervisory control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000007689 inspection Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Landscapes
- Alarm Systems (AREA)
- Fire Alarms (AREA)
Description
第１図は本考案の伝送処理装置を適用した監視
制御システムの概略ブロツク図、第２図は端末器
の構成図、第３図ａ，ｂは中央監視制御装置から
送出される指令のフオーマツト、中央監視制御装
置からの指令に応答して端末器から送出される情
報のフオーマツトをそれぞれ示す図、第４図は伝
送処理装置のブロツク図、第５図は第４図に示す
伝送処理装置の具体的な構成例を示す図、第６図
はメモリに保持される内容の一例を示す図、第７
図ａ，ｂはモードＭＤ１，ＭＤ２が指定される場
合の中央監視制御装置からの指令のフオーマツト
をそれぞれ示す図、第８図は論理アドレスを変更
する場合の処理の流れを示すフローチヤート、第
９図は保守点検を行なう場合の処理の流れを示す
フローチヤートである。
１……中央監視制御装置、２……端末器、３…
…伝送線路、１０……伝送処理装置、１１……入
出力回路、２０……制御部、２１……メモリ、３
１……伝送タイプレジスタ、３２……アドレスレ
ジスタ、３３……データレジスタ、３４……タイ
プ識別部、３５……物理アドレスバツフア、３６
……論理アドレスバツフア、３７……アドレスコ
ンパレータ、３８……ラツチ回路、３９……サン
プリング回路、４０……Ａ／Ｄ変換器、４１……
返送データレジスタ、４３……閾値バツフア、４
４……マグニチユードコンパレータ。
FIG. 1 is a schematic block diagram of a supervisory control system to which the transmission processing device of the present invention is applied, FIG. 2 is a configuration diagram of a terminal device, and FIGS. 3 a and b are formats of commands sent from the central supervisory control device. Figures illustrating the formats of information sent from terminals in response to commands from the central supervisory control unit, Figure 4 is a block diagram of the transmission processing unit, and Figure 5 is a detailed diagram of the transmission processing unit shown in Figure 4. Fig. 6 is a diagram showing an example of the contents held in memory; Fig. 7 is a diagram showing an example of the contents held in memory;
Figures a and b are diagrams showing the format of commands from the central supervisory control unit when modes MD 1 and MD 2 are specified, respectively, and Figure 8 is a flowchart showing the flow of processing when changing a logical address. FIG. 9 is a flowchart showing the flow of processing when performing maintenance and inspection. 1...Central monitoring and control device, 2...Terminal device, 3...
...Transmission line, 10...Transmission processing device, 11...Input/output circuit, 20...Control unit, 21...Memory, 3
1...Transmission type register, 32...Address register, 33...Data register, 34...Type identification section, 35...Physical address buffer, 36
...Logic address buffer, 37...Address comparator, 38...Latch circuit, 39...Sampling circuit, 40...A/D converter, 41...
Return data register, 43...Threshold buffer, 4
4...Magnitude comparator.
Claims (1)
と、該制御部と同一の基板上に実装され、制御部
からの指示によつて所定の情報が書込まれ読出さ
れる書込み可能なメモリとを有していることを特
徴とする伝送処理装置。 ２ 前記メモリは、不揮発性のものであることを
特徴とする請求項１記載の伝送処理装置。[Claims for Utility Model Registration] 1. A control unit that performs predetermined control regarding transmission processing, and a control unit that is mounted on the same board as the control unit, and in which predetermined information is written and read according to instructions from the control unit. A transmission processing device comprising: a writable memory; and a writable memory. 2. The transmission processing device according to claim 1, wherein the memory is nonvolatile.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989125826U JPH0739035Y2 (en) | 1989-10-27 | 1989-10-27 | Terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989125826U JPH0739035Y2 (en) | 1989-10-27 | 1989-10-27 | Terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0366487U true JPH0366487U (en) | 1991-06-27 |
| JPH0739035Y2 JPH0739035Y2 (en) | 1995-09-06 |
Family
ID=31673676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989125826U Expired - Fee Related JPH0739035Y2 (en) | 1989-10-27 | 1989-10-27 | Terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0739035Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182937A (en) * | 1982-04-20 | 1983-10-26 | Nec Corp | In-trouble switching system of communication controller |
-
1989
- 1989-10-27 JP JP1989125826U patent/JPH0739035Y2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182937A (en) * | 1982-04-20 | 1983-10-26 | Nec Corp | In-trouble switching system of communication controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0739035Y2 (en) | 1995-09-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |