JPH0420143U - - Google Patents
Info
- Publication number
- JPH0420143U JPH0420143U JP5976990U JP5976990U JPH0420143U JP H0420143 U JPH0420143 U JP H0420143U JP 5976990 U JP5976990 U JP 5976990U JP 5976990 U JP5976990 U JP 5976990U JP H0420143 U JPH0420143 U JP H0420143U
- Authority
- JP
- Japan
- Prior art keywords
- relay
- board
- under test
- cpu
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は、本考案の実施例を説明するためのブ
ロツク図、第２図従来の一般的な試験装置を表わ
すブロツク図である。
１１，１２……被試験基板、１３，１５……通
常「開」「閉」の接点を有するリレー、１４，１
６……一般的なリレー、１７……アドレスデコー
ダ、１８……データレジスタ、３１，３３……バ
ツフア、３２……割込みロジツク、５１，５２…
…ストローブ信号入力端子、５３，５４……バス
信号入出力端子、５５，５７……割込み制御信号
入力端子、５６……割込み制御信号出力端子、５
８，６１……通常「閉」の接点、５９……通常「
閉」の接点、６０，６２……コモン、６３，６４
……ジヤンパ端子。
FIG. 1 is a block diagram for explaining an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional general testing device. 11, 12... Board under test, 13, 15... Relay with normal "open" and "close" contacts, 14, 1
6... General relay, 17... Address decoder, 18... Data register, 31, 33... Buffer, 32... Interrupt logic, 51, 52...
... Strobe signal input terminal, 53, 54 ... Bus signal input/output terminal, 55, 57 ... Interrupt control signal input terminal, 56 ... Interrupt control signal output terminal, 5
8, 61...Normally "closed" contact, 59...Normally "closed" contact
"Closed" contact, 60, 62...Common, 63, 64
... Jumper terminal.
Claims (1)
毎に入力するストローブ信号と連鎖状に接続する
割込み制御信号とにリレーを設けたことを特徴と
する被試験基板の制御装置。 (2) 前記リレーの制御を行うためにＣＰＵバス
上にロジツク回路を用いたことを特徴とする請求
項１記載の被試験基板の制御装置。[Claims for Utility Model Registration] (1) A device under test characterized in that a relay is provided for a strobe signal input to each test board mounted on an external bus of a CPU and an interrupt control signal connected in a chain. Board control device. (2) The control device for a board under test according to claim 1, characterized in that a logic circuit is used on a CPU bus to control the relay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5976990U JPH0420143U (en) | 1990-06-06 | 1990-06-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5976990U JPH0420143U (en) | 1990-06-06 | 1990-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420143U true JPH0420143U (en) | 1992-02-20 |
Family
ID=31586562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5976990U Pending JPH0420143U (en) | 1990-06-06 | 1990-06-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420143U (en) |
-
1990
- 1990-06-06 JP JP5976990U patent/JPH0420143U/ja active Pending
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