JPH036649B2 - - Google Patents
Info
- Publication number
- JPH036649B2 JPH036649B2 JP56111767A JP11176781A JPH036649B2 JP H036649 B2 JPH036649 B2 JP H036649B2 JP 56111767 A JP56111767 A JP 56111767A JP 11176781 A JP11176781 A JP 11176781A JP H036649 B2 JPH036649 B2 JP H036649B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- monitor
- reticle
- regular
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70058—Mask illumination systems
- G03F7/70066—Size and form of the illuminated area in the mask plane, e.g. reticle masking blades or blinds
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Projection-Type Copiers In General (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Description
【発明の詳細な説明】 本発明は縮小投影露光方法の改善に関する。[Detailed description of the invention] The present invention relates to improvements in reduction projection exposure methods.
半導体装置の高密度化と共に、微細加工の基幹
となるリソグラフイ技術はめざましく進歩してき
た。フオトマスクパターンを基板上に転写する露
光方法も、従来の密着露光方式から10:1又は
5:1などの比率で縮小する縮小投影露光方法が
採られるようになつてきた。これは密着露光方式
に比べて、解像力にすぐれ、高精度にアライメン
トができる利点があるためである。このような縮
小投影露光方法において、パターン原板は拡大さ
れたマスク(通常、10倍が多い)であるから、レ
チクルと呼んでいるが、レチクルにも複数の同一
パターンが形成されており、これは大型化した基
板上への露光処理効率を向上するためである。 As the density of semiconductor devices has increased, lithography technology, which is the basis of microfabrication, has made remarkable progress. The exposure method for transferring a photomask pattern onto a substrate has changed from the conventional contact exposure method to a reduction projection exposure method that reduces the pattern by a ratio of 10:1 or 5:1. This is because, compared to the contact exposure method, it has the advantage of superior resolution and highly accurate alignment. In such reduction projection exposure methods, the pattern original plate is a mask that has been enlarged (usually 10x), so it is called a reticle, but the reticle also has multiple identical patterns formed on it. This is to improve the efficiency of exposure processing on larger substrates.
しかし、半導体基板上にパターンを焼き付ける
フオトプロセスは数回ないしは十数回にも及び、
又熱処理・エツチング処理も同様に多く、これら
ウエハー処理工程途中で、間違いなく所要特性の
素子が形成されつヽあるかどうかの検出を行う必
要がある。そのため、電気的特性を検査するモニ
タパターンが基板上の任意位置に数個形成され
て、そのモニタパターンによりトランジスタ特
性、絶縁耐圧、接触抵抗、その他の配線層抵抗も
検査されている。又、ウエハー処理工程後、所要
特性の半導体素子が得られなかつたとき、特性解
析が行われるが、正規パターンでは微細なためプ
ローバーによる検出が不可能で、その場合にもモ
ニタパターンが利用される。したがつて、是非基
板上に数個のモニタパターンを形成することが必
要であり、従来の密着露光方式はフオトマスクに
はそのまゝ基板と同数のパターンが形成されてい
るから、これら多数の正規パターン内に数個のモ
ニタパターンを形成せしめておくことは容易であ
つた。ところが、縮小投影露光方法では、一枚の
レチクルに複数の正規パターンを形成しておい
て、一度の露光で複数の正規パターンを転写する
のが量産性がよい。しかしこのような縮小投影露
光方法では、わずか一個のモニタパターンをレチ
クルに同居させただけでも、一回の転写ごとにモ
ニタパターンが必ず一個は形成されることになつ
て、転写されるウエハの表面には不必要に多数の
モニタパターンが形成されることとなる。例えば
レチクル上に4個の正規パターンが形成されてお
り、被露光基板上には200個の集積回路パターン
が形成されるとすると、50回のステツプアンドレ
ピートが繰り返えされ、合計で50個のモニタパタ
ーンが形成されることになり、そのように基板の
使用の使用効率の悪いパターンニングをすること
はできない。モニタパターンは精々数個あればよ
いから、縮小投影露光方式では、現在、モニタパ
ターンのみ形成したレチクルを別に用意してお
き、正規パターンが形成されているレチクルと
時々交換して、基板上の所要位置にモニタパター
ンを形成せしめている。 However, the photo process to print the pattern on the semiconductor substrate takes several to ten or more times.
Further, there are many heat treatments and etching treatments as well, and it is necessary to detect during these wafer processing steps whether or not elements with desired characteristics are being formed without fail. Therefore, several monitor patterns for testing electrical characteristics are formed at arbitrary positions on the substrate, and transistor characteristics, dielectric strength voltage, contact resistance, and other wiring layer resistances are also tested using the monitor patterns. In addition, when a semiconductor element with the required characteristics cannot be obtained after the wafer processing process, characteristic analysis is performed, but the regular pattern is so minute that it is impossible to detect it with a prober, and in that case, the monitor pattern is also used. . Therefore, it is necessary to form several monitor patterns on the substrate, and in the conventional contact exposure method, the same number of patterns as the substrate are formed on the photomask, so it is necessary to form these many regular patterns. It was easy to form several monitor patterns within the pattern. However, in the reduction projection exposure method, it is better for mass production to form a plurality of regular patterns on one reticle and transfer the plurality of regular patterns in one exposure. However, in such a reduction projection exposure method, even if only one monitor pattern is placed on the reticle, at least one monitor pattern will be formed in each transfer, and the surface of the wafer to be transferred will be affected. In this case, an unnecessarily large number of monitor patterns are formed. For example, if 4 regular patterns are formed on the reticle and 200 integrated circuit patterns are formed on the exposed substrate, the step repeat will be repeated 50 times, for a total of 50 integrated circuit patterns. This results in the formation of a monitor pattern of 1,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000,000. At most, only a few monitor patterns are required, so in the reduction projection exposure method, a reticle with only the monitor pattern formed is prepared separately, and is occasionally exchanged with a reticle on which the regular pattern is formed, so that the necessary A monitor pattern is formed at the position.
しかしながら、レチクルの交換は予想以上に低
スループツトとなり、露光処理効果が激減するこ
ととなる。即ち、レチクルは交換毎に洗浄し、露
光装置に装着すると位置を調整し、更には装着後
検査基板に焼き付けを行つて異物付着の検査がな
され、その処理工数は著しく増大する。又、交換
回数が増えれば、レチクルパターンを損傷する危
険もそれだけ大きい。 However, the throughput of exchanging the reticle is lower than expected, and the effectiveness of the exposure process is drastically reduced. That is, the reticle is cleaned each time it is replaced, its position is adjusted when it is installed in an exposure device, and furthermore, after installation, the test substrate is printed and inspected for foreign matter adhesion, which significantly increases the number of processing steps. Furthermore, the more frequently the reticle pattern is replaced, the greater the risk of damaging the reticle pattern.
そこで従来、例えば正規パターン一個に加えて
モニタパターン一個を同居形成したものをレチク
ルパターンとして用い、モニタパターンを要しな
い場合にはシヤツターでレチクル面のモニタパタ
ーン表面だけを覆つてモニタパターンが多数形成
されることを防いだ方法が用いられてきた。この
方法によれば、確かに必要量しかモニタパターン
が形成されないことになつて、ウエハの無駄遣い
はなくなる。しかし一回の露光で一個の正規パタ
ーンしか形成されないことになつて、量産的では
ない。 Conventionally, for example, one normal pattern and one monitor pattern were formed together as a reticle pattern, and when a monitor pattern was not required, a shutter was used to cover only the surface of the monitor pattern on the reticle surface to form multiple monitor patterns. Methods have been used to prevent this. According to this method, only the required amount of monitor patterns are formed, and wafers are not wasted. However, since only one regular pattern is formed in one exposure, it is not suitable for mass production.
本発明はかような問題点を解消させる縮小投影
露光方法を提案するもので、
モニタパターンと複数の正規パターンとを有す
るレチクルを用い、被露光基板表面に該レチクル
の正規パターンの転写像を形成する第1の工程
と、
該レチクルを用い、該被露光基板表面に該レチ
クルのモニタパターンの転写像を形成する第2の
工程と
を含むステツプアンドレピートにより、空きパタ
ーン領域が形成されないようにして行う縮小投影
露光方法において、
前記第1の工程では、
前記複数の正規パターンのうち、前記第2の工
程で前記モニタパターンが転写される位置に重な
る該正規パターンを遮蔽しつつ、残りの該正規パ
ターンを転写することにより、
該正規パターンと該モニタパターンとが互いに
重ねて形成されないようにすることを特徴とする
縮小投影露光方法であり、以下実施例により詳細
に説明する。 The present invention proposes a reduction projection exposure method that solves these problems, and uses a reticle having a monitor pattern and a plurality of regular patterns to form a transferred image of the regular pattern of the reticle on the surface of a substrate to be exposed. and a second step of forming a transfer image of the monitor pattern of the reticle on the surface of the substrate to be exposed using the reticle, so that no empty pattern area is formed. In the reduction projection exposure method, in the first step, among the plurality of regular patterns, one of the regular patterns that overlaps a position where the monitor pattern is transferred in the second step is shielded, while the remaining regular patterns are shielded. This is a reduction projection exposure method characterized by transferring a pattern so that the regular pattern and the monitor pattern are not formed overlapping each other, and will be described in detail below with reference to Examples.
第1図は従来のレチクル1の平面図を示し、中
央に9個の正規パターンP1〜P9が形成され、レ
チクルの有効面積は100mm角程度で、周囲部分は
蒸着クロムで遮光されている。このようなレチク
ルは前記したように露光装置に装着されると、先
づ検査用基板に焼き付けして、ゴミ付着、損傷な
どの異常有無を検査した後、被露光基板上に焼き
付け(転写)される。第2図は被露光用半導体基
板2の平面図で、Mはモニタパターンを示し、密
着露光法で3個のモニタパターンを基板上に形成
せしめた例を示している。半導体基板2を直径4
インチ(100mm)の大きさとすれば、第1図に示
すレチクル縮小率1/10で転写する場合、100回近
くのステツプアンドレピート露光が行われるが、
その間に第2図のように3個のモニタパターンを
焼き付けることは不可能になる。1シヨツト9個
のモニタパターンを焼き付ける事は出来るが、そ
れではレチクル交換の手間もかかり、又チツプが
むだになる。 Figure 1 shows a plan view of a conventional reticle 1. Nine regular patterns P 1 to P 9 are formed in the center, the effective area of the reticle is approximately 100 mm square, and the surrounding area is shielded from light by vapor-deposited chromium. . When such a reticle is attached to an exposure device as described above, it is first printed onto a substrate for inspection, inspected for abnormalities such as dust adhesion and damage, and then printed (transferred) onto the substrate to be exposed. Ru. FIG. 2 is a plan view of the semiconductor substrate 2 to be exposed, where M indicates a monitor pattern, and shows an example in which three monitor patterns are formed on the substrate by a contact exposure method. Semiconductor substrate 2 has a diameter of 4
If the size is inch (100 mm), when transferring the reticle at a reduction rate of 1/10 as shown in Figure 1, step repeat exposure will be performed nearly 100 times.
During this time, it becomes impossible to print three monitor patterns as shown in FIG. Although it is possible to print nine monitor patterns in one shot, it takes time to change the reticle and wastes the chip.
第3図は本発明にかヽるレチクルであり、9個
の正規パターンP1〜P9の周囲部分に1個のモニ
タパターンMを作成したレチクル11である。そ
して、第4図に示すモデル図のように、レチクル
11の両側にパターンシヤツタ12,13を設け
て、これを左右にスライドさせ、正規パターン
P1とモニタパターンMとを交互に遮蔽又は露出
させて、適宜にモニタパターンを被露光基板2上
に転写する。第5図a,b,cはこれらのパター
ンとシヤツタとの関係を示しており、第5図aは
正規パターンのみ焼き付ける関係位置で、パター
ンシヤツタ13がモニタパターンMを遮蔽してい
る。第5図bはモニタパターンMを焼き付ける関
係位置で、パターンシヤツタ12が正規パターン
P1を遮蔽し、パターンシヤツタ13は開いてモ
ニタパターンMを露出させている。第5図cはパ
ターンシヤツタ12が正規パターンを遮蔽し、パ
ターンシヤツタ13がモニタパターンMを遮蔽し
ている。また、これら三つの関係位置の他に、何
も遮蔽せず正規パターンとモニタパターンをすべ
て焼き付ける関係位置がある。 FIG. 3 shows a reticle according to the present invention, which is a reticle 11 in which one monitor pattern M is formed around nine regular patterns P1 to P9 . Then, as shown in the model diagram shown in FIG. 4, pattern shutters 12 and 13 are provided on both sides of the reticle 11, and by sliding them left and right, the regular pattern is
P1 and the monitor pattern M are alternately covered or exposed, and the monitor pattern is appropriately transferred onto the substrate 2 to be exposed. 5a, b, and c show the relationship between these patterns and the shutter, and FIG. 5a shows the position where only the regular pattern is printed, and the pattern shutter 13 shields the monitor pattern M. Figure 5b shows the relevant position for printing the monitor pattern M, where the pattern shutter 12 is the regular pattern.
P1 is shielded, and the pattern shutter 13 is opened to expose the monitor pattern M. In FIG. 5c, the pattern shutter 12 shields the regular pattern, and the pattern shutter 13 shields the monitor pattern M. In addition to these three related positions, there is a related position where all regular patterns and monitor patterns are printed without blocking anything.
レチクルパターンをステツプアンドレピートし
て、ウエハ表面の左から右へ転写を続ける際に、
まず最初の転写ではモニタパターンのみをシヤツ
タで覆つて第5図aの状態を採る。続いて何も遮
蔽しない関係位置を採り、モニタパターンを初め
て一個形成する。この後、3番目に転写されるパ
ターンは、2番目に転写したパターンに隣接して
いた方がウエハが無駄なく利用できる。そのため
には、次に第5図cの状態を選んで、2番目の転
写できたモニタパターン部の輪郭に3番目のパタ
ーンを輪郭を継ぎ合わせるようにする。 When step repeating the reticle pattern and continuing to transfer it from left to right on the wafer surface,
In the first transfer, only the monitor pattern is covered with a shutter to obtain the condition shown in FIG. 5a. Next, a relative position is taken where nothing is shielded, and a single monitor pattern is formed for the first time. Thereafter, if the third pattern to be transferred is adjacent to the second pattern to be transferred, the wafer can be used without waste. To do this, next, select the state shown in FIG. 5c and join the outline of the third pattern to the outline of the second transferred monitor pattern section.
あるいは別の例としては、まず何も遮蔽しない
関係位置で転写した後、次いで第5図c、第5図
a、第5図aと順に転写を続ける。 Alternatively, as another example, first transfer is performed at a related position that does not block anything, and then the transfer is continued in the order of FIG. 5c, FIG. 5a, and FIG. 5a.
このように二つのパターンシヤツタで遮蔽、露
光を変化させ、モニタパターン転写位置に、正規
パターンの一部を重ねて転写する際には、パター
ン中のモニタパターンに重なる部分の正規パター
ンを遮蔽して残りの正規パターンを転写すること
によつて、モニタパターンを形成してできる転写
パターンの輪郭の凹凸をうまく継ぎ合わせること
ができる。このため、従来のパターンシヤツタを
用いて行う縮小投影露光よりもずつとウエハの無
駄がない。 In this way, when changing the shielding and exposure using two pattern shutters and transferring a part of the regular pattern overlappingly to the monitor pattern transfer position, the regular pattern in the part of the pattern that overlaps with the monitor pattern is shielded. By transferring the remaining regular pattern, the unevenness of the outline of the transfer pattern created by forming the monitor pattern can be successfully joined together. Therefore, there is less wastage of wafers than in reduction projection exposure performed using a conventional pattern shutter.
このようなパターンシヤツタ12,13は縮小
投影露光装置の本体に付設せしめて、モニタパタ
ーンを焼き付けたいときは、手動操作に切り換え
て転写するが、勿論自動的にシヤツタを動作させ
て、電子計算機操作により制御プログラムに組み
入れることも可能である。尚、第4図において、
14は縮小レンズ系を示している。 Such pattern shutters 12 and 13 are attached to the main body of the reduction projection exposure apparatus, and when you want to print a monitor pattern, you can switch to manual operation and transfer it, but of course you can operate the shutter automatically and print it on the computer. It is also possible to incorporate it into the control program by manipulation. In addition, in Figure 4,
14 indicates a reduction lens system.
以上が本発明の一実施例である。さらに本発明
には、この一実施例に限定されることなく、多数
の変形が可能である。例えば正規パターンからな
るレチクルパターンの外周に形成すべきモニタパ
ターンは、正規パターンがなす長方形の大パター
ンの隅に配置されたものを一例として採り上げた
が、外周中央であつて何ら差支えない。以上から
明らかなように、本発明によれば、モニタパター
ンを転写するためのレチクル交換をなくすころが
できるのに加えて、転写すべきパターン相互をぴ
つたり接合でき、転写すべきウエハの面積を無駄
なく有効に利用できるという効果がある。 The above is one embodiment of the present invention. Moreover, the present invention is not limited to this one embodiment, but can be modified in many ways. For example, the monitor pattern to be formed on the outer periphery of a reticle pattern consisting of a regular pattern is arranged at the corner of a large rectangular pattern formed by the regular pattern, but there is no problem with the monitor pattern being placed at the center of the outer periphery. As is clear from the above, according to the present invention, in addition to being able to eliminate the need to change the reticle for transferring a monitor pattern, the patterns to be transferred can be closely bonded to each other, and the area of the wafer to be transferred can be reduced. It has the effect of being able to be used effectively without waste.
第1図は従来方式のレチクル平面図、第2図は
モニタパターンを形成した基板の平面図、第3図
は本発明にかゝるレチクル平面図、第4図は同じ
く本発明にかゝる方式のモデル図、第5図はパタ
ーンシヤツタとパターンとの関係位置を示す図で
ある。
図中、1,11はレチクル、2は基板、12,
13はパターンシヤツタ、14は縮小レンズ系、
Pは正規パターン、Mはモニタパターンを示して
いる。
FIG. 1 is a plan view of a reticle of a conventional method, FIG. 2 is a plan view of a substrate on which a monitor pattern is formed, FIG. 3 is a plan view of a reticle according to the present invention, and FIG. 4 is a plan view of a reticle according to the present invention. A model diagram of the method, FIG. 5, is a diagram showing the relative position between the pattern shutter and the pattern. In the figure, 1 and 11 are reticles, 2 is a substrate, 12,
13 is a pattern shutter, 14 is a reduction lens system,
P indicates a regular pattern, and M indicates a monitor pattern.
Claims (1)
するレチクルを用い、被露光基板表面に該レチク
ルの正規パターンの転写像を形成する第1の工程
と、該レチクルを用い、該被露光基板表面に該レ
チクルのモニタパターンの転写像を形成する第2
の工程と を含むステツプアンドレピートにより、空きパタ
ーン領域が形成されないようにして行う縮小投影
露光方法において、 前記第1の工程では、 前記複数の正規パターンのうち、前記第2の工
程で前記モニタパターンが転写される位置に重な
る該正規パターンを遮蔽しつつ、残りの該正規パ
ターンを転写することにより、 該正規パターンと該モニタパターンとが互いに
重ねて形成されないようにすることを特徴とする
縮小投影露光方法。[Scope of Claims] 1. A first step of forming a transferred image of the regular pattern of the reticle on the surface of the substrate to be exposed using a reticle having a monitor pattern and a plurality of regular patterns; A second step for forming a transferred image of the monitor pattern of the reticle on the surface of the exposed substrate.
In the reduction projection exposure method performed by step repeat in such a manner that no empty pattern area is formed, in the first step, out of the plurality of regular patterns, in the second step, the monitor pattern is The reduction projection is characterized in that the regular pattern and the monitor pattern are prevented from being formed overlapping each other by transferring the remaining regular pattern while shielding the regular pattern that overlaps the position where the regular pattern is transferred. Exposure method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111767A JPS5814137A (en) | 1981-07-16 | 1981-07-16 | Exposure system by reduced projection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111767A JPS5814137A (en) | 1981-07-16 | 1981-07-16 | Exposure system by reduced projection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5814137A JPS5814137A (en) | 1983-01-26 |
| JPH036649B2 true JPH036649B2 (en) | 1991-01-30 |
Family
ID=14569657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56111767A Granted JPS5814137A (en) | 1981-07-16 | 1981-07-16 | Exposure system by reduced projection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814137A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6281727A (en) * | 1985-10-05 | 1987-04-15 | Fujitsu Ltd | Method for forming buried-type element isolation groove |
| JP3035297B1 (en) * | 1999-05-27 | 2000-04-24 | 株式会社ケムテックジャパン | Apparatus and method for manufacturing printed circuit board |
| CN100347841C (en) * | 2001-02-27 | 2007-11-07 | Nxp股份有限公司 | Semiconductor wafer with process control components |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5226902A (en) * | 1975-08-25 | 1977-02-28 | Hitachi Ltd | Method of making photomask pattern |
| JPS55129333A (en) * | 1979-03-28 | 1980-10-07 | Hitachi Ltd | Scale-down projection aligner and mask used for this |
| JPS5679431A (en) * | 1979-12-03 | 1981-06-30 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor integrated circuit device |
| JPS5748233A (en) * | 1980-09-08 | 1982-03-19 | Toshiba Corp | Exposure system for semiconductor substance |
-
1981
- 1981-07-16 JP JP56111767A patent/JPS5814137A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5814137A (en) | 1983-01-26 |
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