JPH036680U - - Google Patents
Info
- Publication number
- JPH036680U JPH036680U JP6687689U JP6687689U JPH036680U JP H036680 U JPH036680 U JP H036680U JP 6687689 U JP6687689 U JP 6687689U JP 6687689 U JP6687689 U JP 6687689U JP H036680 U JPH036680 U JP H036680U
- Authority
- JP
- Japan
- Prior art keywords
- current
- mirror circuit
- current mirror
- circuit
- vertical deflection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Details Of Television Scanning (AREA)
Description
第１図は本考案の一実施例に係わる垂直偏向電
流の振幅制御回路の構成を示す回路図、第２図は
第１図の各部の波形を示す波形図、第３図は本考
案の他の実施例に係わる垂直偏向電流の振幅制御
回路の構成を示す回路図、第４図は従来の垂直偏
向電流の振幅制御回路の構成を示す回路図である
。
１１……カレントミラー回路、１２……コンデ
ンサ、１３……放電回路、１４……差動増幅回路
、１５……帰還回路、１６……振幅制御部、１６
ａ……増幅回路、１６ｂ……ピークホールド回路
、１６ｃ……調整回路、１６ｄ……トランジスタ
、１６ｅ，１６ｆ……差動増幅回路、ＶＤ……偏
向出力回路。
FIG. 1 is a circuit diagram showing the configuration of a vertical deflection current amplitude control circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms of each part of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing the configuration of a vertical deflection current amplitude control circuit according to the embodiment. FIG. 4 is a circuit diagram showing the configuration of a conventional vertical deflection current amplitude control circuit. 11... Current mirror circuit, 12... Capacitor, 13... Discharge circuit, 14... Differential amplifier circuit, 15... Feedback circuit, 16... Amplitude control section, 16
a...Amplification circuit, 16b...Peak hold circuit, 16c...Adjustment circuit, 16d...Transistor, 16e, 16f...Differential amplifier circuit, VD...Deflection output circuit.
Claims (1)
カレントミラー回路と、 このカレントミラー回路の第１の直流電流によ
つて充電されると共に垂直同期パルスに同期して
放電されるコンデンサと、 このコンデンサの出力と垂直偏向電流のモニタ
値に基づき垂直偏向出力回路に垂直偏向電圧を供
給する差動増幅回路と、 前記垂直偏向電流のモニタ値と外部から入力さ
れる振幅設定値に基づき前記カレントミラー回路
の第２の直流電流を制御する振幅制御部とを備え
たことを特徴とする垂直偏向電流の振幅制御回路
。[Claims for Utility Model Registration] A current mirror circuit that outputs first and second DC currents of substantially the same value; and a current mirror circuit that is charged by the first DC current of the current mirror circuit and synchronized with a vertical synchronization pulse. a differential amplifier circuit that supplies a vertical deflection voltage to a vertical deflection output circuit based on the output of this capacitor and a monitored value of vertical deflection current; and an amplitude control section for controlling the second DC current of the current mirror circuit based on an amplitude setting value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6687689U JPH036680U (en) | 1989-06-07 | 1989-06-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6687689U JPH036680U (en) | 1989-06-07 | 1989-06-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH036680U true JPH036680U (en) | 1991-01-23 |
Family
ID=31599959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6687689U Pending JPH036680U (en) | 1989-06-07 | 1989-06-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH036680U (en) |
-
1989
- 1989-06-07 JP JP6687689U patent/JPH036680U/ja active Pending
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