JPH0366816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-voltage, high-speed power transistor in which an insulated gate field effect transistor (hereinafter referred to as MISFET) and a bipolar transistor are formed on one semiconductor substrate.

Typical power semiconductor devices include bipolar power transistors and vertical structure power devices.
There is a MOSFET. Among these, bipolar power transistors have advantages such as low on-resistance, high current capacity, high withstand voltage, and large GM, but on the other hand, they have low switching speed and low drive power. It has drawbacks such as being large and, in particular, not achieving a low saturation voltage unless a base current flows. On the other hand, power MOSFETs have advantages such as high switching speed, low drive power, no need for DC current, and can be operated only by charging and discharging the input capacitance. It has drawbacks such as being limited by the resistance of the resistivity layer and increasing extremely, and therefore having a small current capacity.

The inventor of the present application has focused on making use of the above-mentioned individual advantages and eliminating disadvantages by combining such bipolar power transistors and power MOSFETs to form a composite power transistor.

Therefore, an object of the present invention is to provide a semiconductor device that is formed on a single semiconductor substrate and is capable of high speed, low drive power, and large current.

The present invention will be specifically described below with reference to Examples.

FIG. 1 is a circuit diagram showing the basic structure of a composite power transistor according to the present invention. This composite power transistor is an enhancement type in the drive stage.
MOSFET Q has a bipolar transistor T in the output stage, and these are connected in Darlington, that is, the source of Q and the base of T are connected, and the drain of Q is made a common terminal with the collector of T.
The gate of Q and the emitter of T are taken out as terminals, and a diode D is inserted between the gate of Q and the base of T to flow a reverse base current _IRB .

The third type of composite power transistor compared to conventional
Two bipolar transistors as shown
A structure in which T ₁ and T ₂ are connected in Darlington is known, and this case has the advantages and disadvantages of the bipolar transistor described above. On the contrary,
As shown in Figure 4, MOSFET Q is used as the drive stage.
By darlington-connecting the bipolar transistor T as an output stage, it is possible to create a composite power transistor that has both the large current capacity, which is an advantage of a bipolar transistor, and the high speed, which is an advantage of a MOSFET. However, the structure shown in FIG. 4 has the following problems. Conventional Darlington-connected composite transistors using only bipolar transistors operate using current, but MOSFETs and
A composite transistor made of bipolar transistors performs switching operation by applying (+) and (-) voltages to MOSFET Q. At the gate of Q (+)
When a voltage is applied, base current I _B flows and transistor T is turned on. When − voltage is applied to the gate of Q
MOSFET Q is turned off and current does not flow to the MOS element (indicated by dotted arrows _IRB in the figure). Therefore, the carriers accumulated in the bipolar transistor T have no place to live and have no choice but to disappear naturally. Therefore, it is necessary to increase the base current in order to forcefully draw out the charge instantaneously. −
MOSFET gate G and source S when voltage is applied
No current flows between them. In this way, since the reverse base current I _RB of the output transistor does not flow, the off-time t _pff (=t _ptg + t _f ) does not become faster.

In the composite power transistor according to the present invention, as _shown in FIG. When a +) voltage is applied to the drive MOSFET Q (on), no base current flows through the diode D, and the output transistor T is turned on, and when a - voltage is applied (off), the base current flows in the opposite direction _. (direction indicated by a dashed arrow) flows through the diode D between the gate and source.

In the present invention, the bipolar transistor T in the output stage is a transistor T1 with a built-in commutating diode, in which a resistor R is inserted between the base and emitter, and a diode _D1 is inserted between the emitter and collector, as shown in Fig. ₂ . Good too.

According to the present invention described above, the following effects can be obtained.

(1) Speed can be increased. Between the collector and base of the output stage bipolar transistor T is I _D ×R _ON (power
The MOSFET is clamped by the MOSFET's internal resistance (internal resistance) and does not reach full saturation, and the diode D allows reverse base current to flow, achieving higher speeds.

(2) Low drive power can be achieved. In the forward direction, only the drive current of MOSFET Q is required, and almost no current is required as a whole.
Since only the reverse base current needs to flow, it is possible to save drive power.

(3) Can handle large current. The output stage is a bipolar transistor, which allows the power MOSFET to flow a current equal to 1/h _FE of the collector current _I.sub.C.

FIG. 5 is a sectional view showing an embodiment of a composite power transistor according to the present invention formed on one semiconductor substrate, and FIG. 6 is a plan view of this composite power transistor.

As shown in Figure 6, this composite power transistor consists of vertical N-channel MOSFETs in the drive stage surrounding the central part of one main surface of the N ⁺ N type Si substrate.
Q is formed, a bipolar NPN transistor T is formed in the peripheral part, and a poly(polycrystalline) Si diode D is formed on a thick oxide film in the central part. In Figure 5, 1 is a high concentration N ⁺ type Si
The substrate 2 is a low concentration N-type Si layer and constitutes a semiconductor substrate which becomes the drain of the drive stage MOSFET and the collector of the output stage transistor. A metal layer 3 serving as a collector electrode C is formed on the back surface of the N ⁺ type Si substrate 1.
4, 5, 6, and 7 are B (boron) from the surface of the N-type Si layer.
This is a P-type well into which 5 is introduced and diffused, of which 5 becomes the base of the drive stage MOSFET, the part directly under the thin gate insulating film on its surface becomes the channel part, and 6 becomes the base of the output stage bipolar transistor. 7 is a field limiting ring for increasing the peripheral voltage.

8, 9, and 10 are high concentration N ⁺ type layers in which As (arsenic), P (phosphorus), etc. are introduced and diffused on the surface of the Si layer,
Of these, 8 is the source of the MOSFET, 9 is the emitter of the bipolar transistor, and 10 is the peripheral guard link. On the source N ⁺ layer 8, there is provided an Al layer 11 which serves as a source electrode and is short-circuited with the P layer 5. A part of the Al layer 11 is connected to the base P layer 6, and the emitter N ⁺
An Al layer 12 serving as an emitter electrode is provided on the layer 9, and an Al layer 13 serving as a guard link is provided on the peripheral guard link N ⁺ layer 10. Reference numeral 14 indicates a thin SiO ₂ film serving as a gate insulating film, numeral 15 indicates a thick SiO ₂ film serving as a field portion, and numeral 16 indicates an SiO ₂ film serving as an interlayer insulating film. 17, 18, and 19 are poly-Si layers formed on the insulating film and are doped with impurities to lower their resistance. Of these, 17 is an N ⁺ doped (phosphorous or arsenic doped) gate, and 18 is a P ⁺ doped (boron doped) gate. ) layer, 19 is an N ⁺ doped (phosphorous or arsenic doped) layer, and the NPN junction constitutes a poly-Si diode. Of these, the N ⁺ doped gate 17 is connected to an Al layer 20 serving as a gate electrode, and the P ⁺ doped layer 18 is connected to an extension of the Al electrode of the source electrode 11 .

FIG. 7 is an enlarged plan view of the diode part, where the part surrounded by solid lines shows the Al layer which becomes the ate and source electrodes, and the dashed line shows the poly-Si layer.
The NPN junction is shown, and the area surrounded by the dashed line is poly-Si
This is the contact part of the Al layer to the layer. FIG. 8 shows a section taken along the line AA' in FIG. 7, and FIG. 9 shows a section taken along the line BB' in FIG. FIG. 10 is a circuit diagram equivalently showing the diode shown in FIG. 7, in which the central N ⁺ doped layer 19, the peripheral (insulated gate side) N ⁺ doped layer 18, and the P ⁺ A doped layer 17 is shown.

In the composite power transistor described above, referring to Figure 1, when a (+) voltage is applied to the gate of MOSFET Q (on operation), carriers from the source to the drain (N substrate) move in the direction of the dashed arrow. ( _ID current flows in the opposite direction of the arrow),
In an NPN transistor, carriers flow from the base P layer to the collector (N substrate) (I _C current is in the opposite direction to the arrow). Further, when a - voltage is applied (off operation), the base reverse current _IRB flows from the base source to the gate electrode via the PN junction of the poly-Si diode.

The present invention described in the embodiments above uses a vertical N-channel MOSFET formed on an N ⁺ N type Si substrate as a drive stage, a bipolar NPN transistor formed around it as an output stage, and a poly-Si diode as a transistor between the base and gate. For the same reasons as explained in the example using the circuit diagram in Figure 1, the composite power transistor inserted in ) Not only is it possible to increase the current, but it also has the following effects.

(4) High voltage resistance is possible. By configuring the drive stage MOSFET as a vertical type, it can share the same high-voltage substrate as the output-stage bipolar transistor, making it possible to increase the voltage resistance and manufacture a power transistor with high current and high power.

(5) Easy to manufacture. Poly-Si gate in drive stage
Since it uses MOSFETs and poly-Si diodes, it can be manufactured without adding any special or new processes. The poly-Si diode can also double as a gate protection diode.

The present invention is not limited to the above embodiments,
In addition to this, there are other variations as described below.

(1) An output stage bipolar transistor T using a transistor with a built-in commutation diode shown in FIG. 2 is formed on the same semiconductor substrate as the drive stage MOSFET.

(2) Instead of the poly-Si diode, it is also possible to use a PN junction diode formed on the substrate surface by selective diffusion. But in this case, the base of the output stage bipolar transistor and the drive stage
Since a parasitic transistor occurs between the gates of the MOSFET, consideration must be given to its arrangement and structure, such as keeping the current amplification factor extremely low so as not to cause the parasitic transistor to operate as a parasitic transistor.

(3) Change the semiconductor substrate, the conductivity type of the diffusion layer, the layout of the diffusion layer, the layout of the electrodes, etc. as necessary.

The present invention is mainly applied to high-speed, high-voltage, and large-current power transistors, such as:
For 1200V class deflection (character display, etc.)
It is extremely effective when applied to transistors and motor drive transistors.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the basic structure of a composite power transistor according to the present invention, FIG. 2 is a partial circuit diagram showing an application example of the present invention, and FIGS. 3 and 4 explain the principle of the present invention. FIG. 5 is a longitudinal sectional view showing one embodiment of the composite power transistor according to the present invention, FIG. 6 is a plan view of the composite power transistor shown in FIG. 5, and FIG. An enlarged plan view of the poly-Si diode portion, FIG. 8 is a cross-sectional view taken along line A-A' in FIG. 7, FIG. 9 is a cross-sectional view taken along line B-B' in FIG. 7, and FIG.
10 is an equivalent circuit diagram of the poly-Si diode shown in FIG. 9. FIG. Q...MOSFET, T...bipolar transistor, D...diode, 1...N ⁺ type Si substrate,
2... N-type Si layer, 3... Collector electrode, 4, 5,
6, 7... P type well, 8, 9, 10... N ⁺ type layer, 11, 12, 13... Al layer, 14, 15,
16...SiO ₂ film, 17, 18, 19... PolySi
Layer, 20...Al layer.

Claims (1)

[Claims] 1. An insulated gate field effect transistor in the front stage,
A bipolar transistor is provided at a subsequent stage, the drain of the field effect transistor is connected to the collector of the bipolar transistor, the source of the field effect transistor is connected to the base of the bipolar transistor, and the gate of the field effect transistor is connected to the collector of the bipolar transistor. A composite transistor characterized in that a diode is inserted between the base of the bipolar transistor and a diode in a direction in which a reverse base current of the bipolar transistor flows. 2 the insulated gate field effect transistor, the bipolar transistor and the diode;
2. The composite transistor according to claim 1, wherein the composite transistor and the interconnection wiring thereof are formed on one semiconductor substrate. 3. The composite transistor according to claim 2, wherein the gate of the insulated gate field effect transistor and the diode are integrally formed in a polycrystalline semiconductor layer.