JPH0366849B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase shift circuit used in digital communications, and relates to a variable phase shift circuit that arbitrarily delays or shifts the phase of a signal with a waveform duty such as a clock pulse or a data burst signal. .

In general, waveform phase shifting methods for clock pulses and data burst signals include creating a delay time using a delay element, such as a delay line, or integrating the input waveform and slicing it at a specified voltage to create a delay time. There are some that generate.

In the former method, since the delay time depends on the dimension of the delay element, fine adjustment becomes difficult once the pattern of the element is determined.

The latter method is constructed using two monostable multivibrators (hereinafter referred to as monomultivibrators) as shown in FIG.

That is, the first mono-multivibrator 1 delays the input signal by a delay time τ ₁ , and the second mono-multivibrator 2 generates a pulse with a predetermined pulse width T having a delay time τ ₁ . The shaped pulse has a duty of 50%.

FIG. 2 shows the waveforms at the 1st, 2nd, and 3rd points. In FIGS. 1 and 2, the clock pulse generator 3
A clock pulse 1 with a pulse width T outputted from the clock pulse 1 is input to the monomultiviprator 1, and at the rising edge of the clock pulse 1, the delay time τ ₁ C ₁ · R ₁ delay pulse 2
occurs. In this case, an arbitrary value can be obtained for τ ₁ by varying the resistance R ₁ .

The delayed pulse 2 is input to the mono multivibrator 2, and at the rising edge of the delayed pulse 2, the time constant T
A pulse 3 with a pulse width T determined by C ₂ ·R ₂ is generated. That is, a pulse 3 having a predetermined delay time τ ₁ , a pulse width T, and a duty of 50% is output. In this case, since the values of both the capacitor C ₂ and the resistor R ₂ fluctuate due to temperature changes, it is difficult to keep the pulse width T constant all the time.

As described above, in the conventional technology, it is difficult to finely adjust the delay time, the pulse width T changes depending on the temperature, and the duty of the pulse waveform is 50%.
There are drawbacks and limitations in use, such as being usable only when the time is %.

In order to solve the above-mentioned problems, the present invention provides a novel variable phase shift circuit that allows easy adjustment of the delay time and provides an arbitrary delay time to an input pulse signal having an arbitrary non-constant period and duty. It provides: This purpose also includes a gate circuit that detects a change in an input signal and outputs a pulse, and a mono-multivibrator that outputs a signal that becomes an unstable value when the output pulse of the gate circuit is input and returns to a stable value after a predetermined period of time. and a flip-flop circuit that inverts the output when the output signal of the mono-multivibrator changes from an unstable value to a stable value and is reset by the rising edge of the input signal. This is achieved by

That is, in order to phase-shift an input pulse with an arbitrary period or duty, the rising and falling signals of the input pulse to be phase-shifted are used to drive a mono multivibrator to generate a delayed pulse with a predetermined delay time. The delayed pulse is input as a clock pulse to a flip-flop circuit which inverts its output every time a clock pulse is applied, thereby shaping a pulse having a predetermined amount of delay.

Further, the rising signal is used as a reset signal for the flip-flop circuit to control the flip-flop, thereby eliminating phase uncertainty when the power is turned on.

The embodiment of FIG. 3 will be explained below based on the time chart of FIG. 4.

In the figure, an input pulse waveform A whose period and duty are not constant is input from an input terminal 4, a desired delay is applied to the waveform A by an inverter 5 and a capacitor 6, and the delayed waveform is transferred to a NAND gate 7.
It is compared with waveform A at , and waveform B corresponding to the rising signal of waveform A is generated. Also, inverters 8, 9
The circuit of capacitor 10 and NAND gate 11 also generates waveform C corresponding to the falling edge of waveform A based on the same principle as described above. Waveforms B and C generate waveform D at NAND gate 12. By activating the mono multivibrator 13 with the rising signal of the waveform D, a certain delay determined by the resistor R ₃ and the capacitor C ₃ of the mono multivibrator 13 is generated at the leading and trailing edges of the input pulse waveform A. A waveform E having a time width τR ₃ ·C ₃ is generated. Using this waveform E as a clock pulse, a D-type flip
The flop circuit 14 (hereinafter referred to as D-F・F)
When input to the C1 terminal, the frequency of the input pulse A is divided by 1/2 to generate a desired waveform F with a constant delay time τ. The D-type flip-flop circuit (D
-F・F) 14 inverts the output every time a clock pulse is applied, so the
As shown in the figure, the circuit has a T-type flip-flop connection with one of the outputs connected to the D input, and therefore operates like a 1/2 frequency divider or a binary counter.

Generally, in such a circuit that inverts the output every time a clock pulse is applied, the inversion between 0 and 1 may be in the opposite direction depending on the state when the power is turned on, and this is referred to as phase uncertainty. This is an unavoidable phenomenon that haunts circuits like this.

As a countermeasure for this, if a narrow pulse waveform B obtained from the leading edge of the input pulse A is input to the reset terminal R of the D-F/F14, and the D-F/F14 is controlled using the waveform B as a reset signal, the phase can be adjusted. Uncertainty can be removed.

FIG. 5 shows an application example of the present invention, and is a circuit example in which one gate circuit is omitted from the case of FIG. For the purpose of explanation, the time chart shown in FIG. 4 will be used.

The input waveform A is delayed by a minute time determined by an inverter 5 and a capacitor 6, and the delayed waveform is sliced at a specified level by the next inverter 16, and the sliced level is exclusive ORed.
It is compared with input waveform A at gate 17 to generate waveform D. When this waveform D and the input waveform A are input to an AND gate 18 and the output thereof is inverted by an inverter 19, a waveform B is generated. Waveforms D and B operate the phase shift circuit of this figure based on the same principle as in FIG.

As described above, according to the present invention, a delayed waveform is generated from the rising and falling signals of an input pulse, and this is used as the clock pulse of a circuit that operates to invert the output every time a clock pulse is applied, so that the output of this circuit is always equal to the input pulse signal. Arbitrarily delayed and phase shifted output pulse signals having the same period and duty are produced.

[Brief explanation of drawings]

Fig. 1 shows a conventional example, Fig. 2 shows a time chart of Fig. 1, Fig. 3 shows an embodiment of the present invention, Fig. 4 shows a time chart of Fig. 3, and Fig. 5 shows an application example of the present invention. . In the figure, 1 is a clock pulse generator, 2 and 3 are mono multivibrators, 4 is an input terminal, 5, 8,
9, 16, 19 are inverters, 6, 10 are capacitors, 7, 11, 12 are NAND gates, 13 is a mono multivibrator, 14 is D-F・F, 1
5 indicates an output terminal.

Claims (1)

[Claims] 1. A gate circuit that detects a change in an input signal and outputs a pulse, and a monomultiplier that outputs a signal that becomes an unstable value when the output pulse of the gate circuit is input and returns to a stable value after a predetermined time. A variable phase shift circuit comprising: a vibrator; and a flip-flop circuit that inverts the output when the output signal of the mono-multivibrator changes from an unstable value to a stable value and is reset by the rising edge of the input signal.